Four-level pulse amplitude modulation high-speed serial port transmitter circuit based on DAC

Abstract

The present invention provides a DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuit, a high-speed serial port transmitter, and an electronic device, and relates to the field of integrated circuit design. A low-speed digital combiner receives multiple parallel low-speed non-return-to-zero code data signals, combines them, generates 8 high-speed non-return-to-zero code data signals, and transmits them to a four-level pulse amplitude modulation module; the four-level pulse amplitude modulation module receives 8 high-speed non-return-to-zero code data signals, converts them into 4 four-level pulse amplitude modulation signals, and transmits them to an analog combining module; the analog combining module receives 4 four-level pulse amplitude modulation signals, combines them, and performs 2-tap feedforward equalization to generate 1 serial high-speed data signal for output. The present invention adopts an analog combiner to combine data and realizes feedforward equalization at the same time. It has high working speed, high combining rate, extended bandwidth, simplified structure, small area, low power consumption, and reduced parasitic capacitance of the output node.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuit, a high-speed serial port transmitter, and electronic equipment. Background Art

[0002] With the continuous advancement of information technology, users' demand for data transmission speeds is increasing. For interfaces between electronic devices, which require high transmission speeds while minimizing the use of physical resources, high-speed serial interfaces (SerDes) are the right solution.

[0003] The design of high-speed serial port circuit transmitters has always been a popular research topic in wired transmission. In recent years, with the continuous evolution of process nodes and the introduction of new circuit structures, the single-channel data rate has shown a trend of doubling every three to four years.

[0004] Technically, existing high-speed serial port transmitters have a relatively uniform circuit structure, primarily consisting of a combiner, output driver circuits, and feed-forward equalization (FFE) circuitry. The transmitter's primary function is to combine low-speed parallel data through a series of combiners to generate high-speed serial data. Combiners are typically implemented as multiplexers based on MOS switches, using a clock signal to select different data points to achieve the combining function. This approach utilizes digital circuits, but due to the speed limitations of the MOS switches, it struggles to operate at very high frequencies.

[0005] Because the output stage operates at the highest speed and needs to drive a large load, the transmitter requires a specially designed output-stage circuit. This is typically based on a DAC output stage, with specific implementations primarily classified as CML drive and SST voltage drive. A disadvantage of traditional DAC output stages is the need to integrate a large array of driver circuits at the output node, introducing significant parasitic capacitance and occupying a large area. To improve the transmission quality of the output signal within the channel, feedforward equalization is required within the transmitter.

[0006] The traditional approach to feedforward equalization is to retime multiple channels of parallel data to form multiple taps. The output stage DAC then performs a weighted summation of the data from these channels to generate an equalized signal for output. This approach requires a large data path and places high demands on the linearity of the output stage DAC. With the evolution of process nodes, much recent work has shifted to implementing feedforward equalization in the DSP. This approach has the advantage of implementing complex logic functions in the digital domain, reducing the complexity of fully custom circuit design. However, the disadvantage is that after equalization, a single bit of data becomes multiple bits, resulting in a large number of parallel data lines and increasing circuit size. Summary of the Invention

[0007] In view of the above problems, the present invention is proposed to provide a DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuit, a high-speed serial port transmitter and an electronic device that solve the above problems or partially solve the above problems.

[0008] A first aspect of an embodiment of the present invention provides a DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuit, the four-level pulse amplitude modulation high-speed serial port transmitter circuit comprising: a low-speed digital combiner, a four-level pulse amplitude modulation module, an analog combiner module, and a clock generation module;

[0009] The low-speed digital combiner receives multiple parallel low-speed non-return-to-zero code data signals, combines them, generates 8 high-speed non-return-to-zero code data signals and transmits them to the four-level pulse amplitude modulation module;

[0010] The four-level pulse amplitude modulation module receives the eight-channel high-speed non-return-to-zero code data signals, converts them into four-channel four-level pulse amplitude modulation signals, and transmits them to the analog combining module;

[0011] The analog combining module receives the four-way four-level pulse amplitude modulation signals, combines them, and performs 2-tap feedforward equalization to generate one-way serial high-speed data signal for output;

[0012] The clock generation module is connected to the low-speed digital combiner and the analog combiner module respectively, and the clock generation module is used to provide a clock signal to the low-speed digital combiner and the analog combiner module;

[0013] The one-channel serial high-speed data signal output by the analog combining module is bandwidth-expanded by using inductive peaking technology before being output off-chip.

[0014] Optionally, the analog combiner module includes: a first 2:1 analog combiner, a second 2:1 analog combiner, a first return-to-zero code generating unit, a second return-to-zero code generating unit, and a return-to-zero code summing unit;

[0015] The first 2:1 analog combiner receives any two four-level pulse amplitude modulation signals from the four four-level pulse amplitude modulation signals, and the second 2:1 analog combiner receives the remaining two four-level pulse amplitude modulation signals from the four four-level pulse amplitude modulation signals;

[0016] The first 2:1 analog combiner combines the two received four-level pulse amplitude modulation signals to obtain a first four-level pulse amplitude modulation signal with a higher frequency and transmits the signal to the first return-to-zero code generating unit;

[0017] The second 2:1 analog combiner combines the two received four-level pulse amplitude modulation signals to obtain a second four-level pulse amplitude modulation signal with a higher frequency and transmits the signal to the second return-to-zero code generating unit;

[0018] The first return-to-zero code generating unit converts the first four-level pulse amplitude modulation signal with a higher frequency into a first return-to-zero code signal, and transmits the first return-to-zero code signal to the return-to-zero code summing unit;

[0019] The second return-to-zero code generating unit converts the second four-level pulse amplitude modulation signal with a higher frequency into a second return-to-zero code signal, and transmits the second return-to-zero code signal to the return-to-zero code summing unit;

[0020] The return-to-zero code summing unit performs staggered addition of the first return-to-zero code signal and the second return-to-zero code signal to obtain the one-channel serial high-speed data signal.

[0021] Optionally, the two four-level pulse amplitude modulation signals are two differential data signals;

[0022] The first 2:1 analog combiner and the second 2:1 analog combiner have the same structure. The first 2:1 analog combiner includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor;

[0023] The first end of the first MOS transistor and the first end of the second MOS transistor respectively receive one differential data signal of the two differential data signals, and the first end of the third MOS transistor and the first end of the fourth MOS transistor respectively receive the other differential data signal of the two four-level pulse amplitude modulation signals;

[0024] The second end of the first MOS transistor is connected to the second end of the third MOS transistor, and outputs the first four-level pulse amplitude modulation signal with a higher frequency;

[0025] The third end of the first MOS transistor and the third end of the second MOS transistor are connected, and both are connected to the second end of the fifth MOS transistor;

[0026] The second end of the second MOS transistor is connected to the second end of the fourth MOS transistor, and outputs the first four-level pulse amplitude modulation signal with a higher frequency;

[0027] The third end of the third MOS transistor is connected to the third end of the fourth MOS transistor, and both are connected to the second end of the sixth MOS transistor;

[0028] The first end of the fifth MOS transistor and the first end of the sixth MOS transistor respectively receive the clock signal, where the clock signal is a differential clock signal;

[0029] The third end of the fifth MOS transistor and the third end of the sixth MOS transistor are connected, and are both connected to the first current source and grounded through the first current source;

[0030] Wherein, after the second end of the first MOS transistor and the second end of the third MOS transistor are connected, they are also connected to the first power supply through a set of resistors and inductors connected in series;

[0031] After the second end of the second MOS transistor is connected to the second end of the fourth MOS transistor, the second end is further connected to a second power supply through a group of resistors and inductors connected in series.

[0032] Optionally, the first four-level pulse amplitude modulation signal with a higher frequency and the second four-level pulse amplitude modulation signal with a higher frequency are both differential input signals;

[0033] The first return-to-zero code generating unit and the second return-to-zero code generating unit have the same structure. The first return-to-zero code generating unit includes: a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor; a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, and an eighteenth MOS transistor;

[0034] The first end of the seventh MOS transistor, the first end of the eighth MOS transistor, the first end of the ninth MOS transistor, the first end of the tenth MOS transistor, the first end of the eleventh MOS transistor, the first end of the twelfth MOS transistor, the first end of the thirteenth MOS transistor, and the first end of the fourteenth MOS transistor all receive the differential input signal;

[0035] The second end of the seventh MOS transistor, the second end of the tenth MOS transistor, the second end of the eleventh MOS transistor, and the second end of the fourteenth MOS transistor are all connected and output the first return-to-zero code signal;

[0036] The second end of the eighth MOS transistor, the second end of the ninth MOS transistor, the second end of the twelfth MOS transistor, and the second end of the thirteenth MOS transistor are all connected and output the first return-to-zero code signal;

[0037] The third end of the seventh MOS transistor is connected to the third end of the eighth MOS transistor, and both are connected to the second end of the fifteenth MOS transistor;

[0038] The third end of the ninth MOS transistor is connected to the third end of the tenth MOS transistor, and both are connected to the second end of the sixteenth MOS transistor;

[0039] The third end of the eleventh MOS transistor is connected to the third end of the twelfth MOS transistor, and both are connected to the second end of the seventeenth MOS transistor;

[0040] The third end of the thirteenth MOS transistor is connected to the third end of the fourteenth MOS transistor, and both are connected to the second end of the eighteenth MOS transistor;

[0041] The first end of the fifteenth MOS transistor and the first end of the sixteenth MOS transistor respectively receive the clock signal;

[0042] The first end of the seventeenth MOS transistor and the first end of the eighteenth MOS transistor respectively receive a bias voltage;

[0043] The third end of the fifteenth MOS transistor and the third end of the sixteenth MOS transistor are connected, and are both connected to the second current source and grounded through the second current source;

[0044] The third end of the seventeenth MOS transistor and the third end of the eighteenth MOS transistor are connected, and are both connected to a third current source and grounded through the third current source;

[0045] The second end of the seventh MOS transistor, the second end of the tenth MOS transistor, the second end of the eleventh MOS transistor, and the second end of the fourteenth MOS transistor are all connected and then connected to a third power supply through a group of resistors and inductors connected in series.

[0046] The second end of the eighth MOS transistor, the second end of the ninth MOS transistor, the second end of the twelfth MOS transistor, and the second end of the thirteenth MOS transistor are all connected and then connected to a fourth power supply through a group of series-connected resistors and inductors.

[0047] Optionally, the low-speed digital combiner adopts serial port technology for processing, and realizes the function of synthesizing the multiple parallel low-speed non-return-to-zero code data signals into 8 high-speed non-return-to-zero code data signals by cascading multiple stages of combiners;

[0048] The number of cascade stages of the multi-stage combiner cascade is determined by the number of the multi-channel parallel low-speed non-return-to-zero code data signals.

[0049] Optionally, the four-level pulse amplitude modulation module comprises: two sets of differential amplifiers with adjustable tail current sources, wherein the magnitude of the differential pair tail current corresponding to the MSB is twice the magnitude of the differential pair tail current corresponding to the LSB;

[0050] Two groups of CML structure differential amplifiers are connected to the same output, and the voltages generated by the two currents flowing through the load are the four-channel four-level pulse amplitude modulation signals obtained by conversion.

[0051] Optionally, the clock generation module includes: a driver, a frequency divider and a phase interpolator, wherein the frequency divider is used to generate a low-speed clock from a high-speed clock, and the phase interpolator is used to adjust the relative phase of the clocks between different cascaded combiners.

[0052] Optionally, the multiple parallel low-speed non-return-to-zero code data signals are 160 parallel low-speed non-return-to-zero code data signals generated by a pseudo-random binary sequence signal source.

[0053] A second aspect of the embodiments of the present invention provides a high-speed serial port transmitter, comprising the DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuit as described in any one of the first aspects.

[0054] A third aspect of the embodiments of the present invention provides an electronic device, comprising the DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuit as described in any one of the first aspects.

[0055] The present invention provides a DAC-based four-level pulse amplitude modulation (PAM) high-speed serial port transmitter circuit, comprising a low-speed digital combiner, a four-level PAM module, an analog combiner module, and a clock generation module. The low-speed digital combiner receives multiple parallel low-speed NRZ data signals, combines them, and generates eight high-speed NRZ data signals, which are then transmitted to the four-level PAM module.

[0056] The four-level pulse amplitude modulation module receives eight high-speed non-return-to-zero code data signals, converts them into four four-level pulse amplitude modulation signals, and transmits them to the analog combiner module; the analog combiner module receives four four-level pulse amplitude modulation signals, combines them, and performs 2-tap feedforward equalization to generate one serial high-speed data signal for output.

[0057] The clock generation module is connected to the low-speed digital combiner and the analog combiner module respectively, and is used to provide clock signals to the low-speed digital combiner and the analog combiner module. Among them, the one-channel serial high-speed data signal output by the analog combiner module is bandwidth-expanded using inductive peaking technology before being output off-chip.

[0058] The four-level pulse amplitude modulation high-speed serial port transmitter circuit of the present invention proposes a new DAC-based PAM4 (four-level pulse amplitude modulation) high-speed serial port transmitter architecture, adopts an analog combiner for data combining, and can achieve feedforward equalization while combining.

[0059] The four-level pulse amplitude modulation high-speed serial port transmitter circuit operates at a high speed. Compared to traditional digital combiners, this analog combiner DAC architecture has the advantage of using CML differential pairs, which increases switching speed and enables higher combining rates. Furthermore, the simple output stage structure facilitates the integration of inductors at the load end, enabling the use of inductor peaking technology to further expand bandwidth. Simulations have verified that this architecture can achieve an output data rate of 144Gb / s using a 65nm CMOS process, comparable to world-leading results using FinFET technology. The higher transistor cutoff frequency, faster switch turn-on speed, and shorter trace distances achieved by advanced processes can further improve the architecture's maximum operating rate.

[0060] The circuit structure of a four-level pulse amplitude modulation high-speed serial transmitter is simplified and compact. Conventional serial transmitter architectures require extensive retiming circuitry and numerous parallel data paths to implement feedforward equalization. The analog-combining-based feedforward equalization architecture of the present invention reduces the number of parallel data paths, simplifying the transmitter structure while avoiding the need for large-scale transistor arrays in the output stage, thereby reducing parasitic capacitance at the output node.

[0061] The four-level pulse amplitude modulation high-speed serial port transmitter circuit has low power consumption. The feedforward equalization architecture of the present invention reduces the number of parallel data paths, thereby saving power in the corresponding data paths. Furthermore, the smaller data path load reduces the clock driver requirements and reduces the clock driver power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0063] Figure 1 This is a modular schematic diagram of a DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuit in an embodiment of the present invention;

[0064] Figure 2 It is a relatively detailed modular schematic diagram in an embodiment of the present invention;

[0065] Figure 3 This is a detailed modular schematic diagram of the analog combiner module ACM in an embodiment of the present invention;

[0066] Figure 4 1 is a schematic diagram of a preferred first 2:1 analog combiner in an embodiment of the present invention;

[0067] Figure 5 This is a schematic diagram of the circuit structure of a preferred first return-to-zero code generating unit in an embodiment of the present invention. DETAILED DESCRIPTION

[0068] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0069] The present invention proposes a DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuit, which includes: a low-speed digital combiner, a four-level pulse amplitude modulation module, an analog combiner module and a clock generation module.

[0070] The low-speed digital combiner receives multiple parallel low-speed non-return-to-zero (NRZ) data signals, combines them, and generates eight high-speed NRZ data signals, which are then transmitted to the four-level pulse amplitude modulation module. The four-level pulse amplitude modulation module then receives these eight high-speed NRZ data signals, converts them into four four-level pulse amplitude modulation (PAM4) signals, and transmits them to the analog combiner module.

[0071] Finally, the analog combiner module receives four PAM4 signals, combines them, and performs 2-tap feedforward equalization to generate a single serial high-speed data signal for output. This single serial high-speed data signal can be bandwidth-expanded using inductive peaking technology before being output off-chip. The clock generation module is connected to the low-speed digital combiner and the analog combiner module, providing clock signals to both.

[0072] Reference Figure 1 , which exemplarily shows a modular schematic diagram of a DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuit of the present invention. Figure 1 The medium and low speed digital combiner LSDC receives multiple parallel low speed NRZ data signals ( Figure 1 These multiple parallel low-speed NRZ data signals are combined to generate 8 high-speed NRZ data signals and transmitted to the four-level pulse amplitude modulation module PAM4.

[0073] The four-level pulse amplitude modulation module PAM4 receives 8 high-speed NRZ data signals, converts them into 4 PAM4 signals, and transmits them to the analog combiner module ACM. The analog combiner module ACM receives 4 PAM4 signals, combines them, and performs 2-tap feedforward equalization to generate 1 serial high-speed data signal for output. Figure 1 OUT represents the output of a serial high-speed data signal. The clock generation module CGM is connected to the low-speed digital combiner LSDC and the analog combiner module ACM, respectively. The clock generation module CGM receives the reference clock CLK input and generates a clock signal for the low-speed digital combiner LSDC and the analog combiner module ACM.

[0074] In an embodiment of the invention, the low-speed digital combiner LSDC can implement its function in a variety of ways. A preferred method is to use serial port technology for processing. It can realize the function of synthesizing multiple parallel low-speed NRZ data signals into 8 high-speed NRZ data signals by cascading multiple-stage combiners; wherein the number of cascade levels of the multi-stage combiner cascade is determined by the number of multiple parallel low-speed NRZ data signals.

[0075] The four-level pulse amplitude modulation (PAM4) module can also implement its functions in a variety of ways. A preferred method is as follows: the four-level pulse amplitude modulation (PAM4) module consists of two sets of differential amplifiers with adjustable tail current sources, where the magnitude of the differential pair tail current corresponding to the MSB is twice the magnitude of the differential pair tail current corresponding to the LSB. The two sets of CML-structured differential amplifiers are connected to the same output, and the voltage generated by the two currents flowing through the load is the converted four-channel PAM4 signal.

[0076] The clock generation module CGM can also implement its functions in a variety of ways. A preferred way is: the clock generation module CGM includes: a driver, a divider and a phase interpolator, wherein the divider is used to generate a low-speed clock from a high-speed clock, and the phase interpolator is used to adjust the relative phase of the clocks between different cascaded combiners.

[0077] In the embodiment of the present invention, the multi-channel parallel low-speed NRZ data signal can be a 160-channel parallel low-speed NRZ data signal generated by a pseudo-random binary sequence (PRBS) signal source. Taking this type of multi-channel parallel low-speed NRZ data signal as an example, assuming that the frequency of the reference clock CLK received by the clock generation module CGM is 36GHz, refer to Figure 2 , which exemplifies a more detailed modular schematic diagram. Figure 2The central clock generation module CGM generates clock signals of 900 MHz, 9 GHz, 18 GHz, and 36 GHz, respectively, and provides them to the pseudo-random binary sequence signal source PRBS, the low-speed digital combiner LSDC, and the analog combiner module ACM, respectively. Among them, the analog combiner module ACM receives 18 GHz and 36 GHz clock signals.

[0078] The pseudo-random binary sequence signal source (PRBS) generates 160 parallel PRBS31 sequences in NRZ mode at a data rate of 900 Mb / s, which serve as the multiple parallel low-speed NRZ data input signals for the low-speed digital combiner (LSDC). Eight parallel 20:1 low-speed serial port combiner modules (low-speed digital combiner LSDC) then convert the 160 900 Mb / s parallel low-speed NRZ data signals into eight 18 Gb / s high-speed NRZ data signals.

[0079] The four-level pulse amplitude modulation (PAM4) module receives eight 18Gb / s high-speed NRZ data signals and converts them into four 36Gb / s PAM4 signals. The analog combiner (ACM) module receives four 36Gb / s PAM4 signals, combines them, and performs two-tap feedforward equalization to generate a single 144Gb / s serial high-speed data signal for output.

[0080] The analog combiner module (ACM) in this embodiment of the present invention combines and outputs four PAM4 signals in a 4-to-1 fashion. Because this data rate is relatively high, traditional serial port technologies based on digital circuits struggle to operate at this rate. Therefore, the analog combiner module (ACM) in this embodiment of the present invention differs from the output stage circuitry and feedforward equalization employed in the prior art by directly processing the four PAM4 signals in the analog domain. Using analog combining technology, it simultaneously combines the signals and implements 2-tap feedforward equalization, replacing the output stage circuitry and feedforward equalization employed in the prior art.

[0081] An analog combiner module (ACM) according to an embodiment of the present invention includes a first 2:1 analog combiner, a second 2:1 analog combiner, a first return-to-zero code generation unit, a second return-to-zero code generation unit, and a return-to-zero code summing unit. The first 2:1 analog combiner receives any two of the four PAM4 signals, and the second 2:1 analog combiner automatically receives the remaining two of the four PAM4 signals.

[0082] The first 2:1 analog combiner combines the two received PAM4 signals to obtain a first PAM4 signal with a higher frequency and transmits it to the first return-to-zero code generation unit; the second 2:1 analog combiner combines the two received PAM4 signals to obtain a second PAM4 signal with a higher frequency and transmits it to the second return-to-zero code generation unit.

[0083] The first return-to-zero code generating unit converts the first PAM4 signal with a higher frequency into a first return-to-zero code signal, and transmits the first return-to-zero code signal to the return-to-zero code summing unit; the second return-to-zero code generating unit converts the second PAM4 signal with a higher frequency into a second return-to-zero code signal, and transmits the second return-to-zero code signal to the return-to-zero code summing unit.

[0084] The return-to-zero code summing unit adds the first return-to-zero code signal and the second return-to-zero code signal in an offset manner to obtain a serial high-speed data signal.

[0085] Take the analog combiner module ACM receiving 4 36Gb / s PAM4 signals and combining them as an example, refer to Figure 3 , shows a detailed modular schematic diagram of the analog combiner module ACM in an embodiment of the present invention. Figure 3 In the figure, the first 2:1 analog combiner ACM10 and the second 2:1 analog combiner ACM20 receive two 36Gb / s PAM4 signals respectively. Since the functions of the first 2:1 analog combiner ACM10 and the second 2:1 analog combiner ACM20 are exactly the same, taking the first 2:1 analog combiner ACM10 as an example: the first 2:1 analog combiner ACM10 combines the two 36Gb / s PAM4 signals into one 72Gb / s PAM4 signal based on an 18GHz clock signal, and transmits it to the first return-to-zero code generation unit RZ10.

[0086] Since the functions of the first return-to-zero code generation unit RZ10 and the second return-to-zero code generation unit RZ20 are exactly the same, taking the first return-to-zero code generation unit RZ10 as an example: the first return-to-zero code generation unit RZ10 receives a 72Gb / s PAM4 signal, and based on a 36GHz clock signal, converts the 72Gb / s PAM4 signal into a 72Gb / s RZ signal (i.e., the first return-to-zero code signal), and transmits it to the return-to-zero code summation unit RZ+.

[0087] The return-to-zero code summing unit RZ+ receives two 72Gb / s RZ signals (i.e., the first return-to-zero code signal and the second return-to-zero code signal), performs staggered addition on the two 72Gb / s RZ signals, and obtains a 144Gb / s serial high-speed data signal, thereby completing the combining function and outputting it from the output terminal OUT. In an embodiment of the present invention, the final combining is processed in the analog domain, avoiding the large-scale array of the output stage circuit. While reducing the parasitic capacitance of the output stage circuit, the bandwidth can be expanded using inductor peaking technology. In order to expand the bandwidth, a large number of peaking inductors are also used in the clock path in this example, and drawing on the practice in the RF circuit, inductors are stacked to reduce the area of ​​the chip, achieving a compromise between chip area and speed.

[0088] by Figure 2 、 Figure 3 Taking the detailed structure shown as an example, simulations have demonstrated that an output data rate of 144 Gb / s can be achieved down to low frequencies using a 65nm CMOS process, comparable to world-leading FinFET technology. The higher transistor cutoff frequency, faster switch turn-on speed, and shorter trace lengths achieved using advanced processes further enhance the maximum operating speed of the transmitter circuit in this embodiment of the present invention.

[0089] In order to more clearly explain the specific structure of the analog combining module ACM in the embodiment of the present invention, refer to Figure 4 、 Figure 5 , respectively showing the preferred circuit structures of the first 2:1 analog combiner and the first return-to-zero code generating unit. Since the structures of the first 2:1 analog combiner and the second 2:1 analog combiner are exactly the same, and the structures of the first return-to-zero code generating unit and the second return-to-zero code generating unit are exactly the same, the structures of the second 2:1 analog combiner and the second return-to-zero code generating unit are not shown again. Figure 4 、 Figure 5 You can get it easily.

[0090] Figure 4 1 shows that the first 2:1 analog combiner includes: a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6. Figure 4 The NMOS transistor is used as an example. The corresponding junction of the PMOS transistor can be obtained by simple transformation and will not be described in detail. The PAM4 signal is a differential data signal.

[0091] The first end of the first MOS transistor M1 and the first end of the second MOS transistor M2 respectively receive one differential data signal D1P, D1N of the two differential data signals, and the first end of the third MOS transistor M3 and the first end of the fourth MOS transistor M4 respectively receive the other differential data signal D2P, D2N.

[0092] The second end of the first MOS transistor M1 is connected to the second end of the third MOS transistor M3, and outputs the first PAM4 signal with a higher frequency. Figure 4 The output of OUTN is the first PAM4 signal with a higher frequency.

[0093] The third end of the first MOS transistor M1 is connected to the third end of the second MOS transistor M2, and both are connected to the second end of the fifth MOS transistor M5; the second end of the second MOS transistor M5 is connected to the second end of the fourth MOS transistor M4, and outputs the first PAM4 signal with a higher frequency. Figure 4 The output of OUTP is the first PAM4 signal with a higher frequency. Therefore, it can be seen that the first PAM4 signal with a higher frequency is also a differential signal.

[0094] The third end of the third MOS transistor M3 and the third end of the fourth MOS transistor M4 are connected, and are both connected to the second end of the sixth MOS transistor M6; the first end of the fifth MOS transistor M5 and the first end of the sixth MOS transistor M6 respectively receive clock signals CLKP and CLKN, which are also differential clock signals.

[0095] The third terminal of the fifth MOS transistor M5 and the third terminal of the sixth MOS transistor M6 are connected, and are both connected to the first current source I1 and grounded through the first current source I1. Furthermore, the second terminal of the first MOS transistor M1 is connected to the second terminal of the third MOS transistor M3, and is then connected to the first power supply VDD1 via a series resistor and inductor. The second terminal of the second MOS transistor M2 is connected to the second terminal of the fourth MOS transistor M4, and is then connected to the second power supply VDD2 via a series resistor and inductor.

[0096] The differential clock signals CLKP and CLKN control the switching of two data branches through the two lower MOS transistors M5 and M6, with the left and right branches alternately conducting. When the left branch conducts, one differential data signal, D1P and D1N, is transmitted to the output through the differential pair. When the right branch conducts, the other differential data signal, D2P and D2N, is transmitted to the output through the differential pair, thus completing a 2-to-1 combining operation.

[0097] Figure 5 : It is shown that the first return-to-zero code generating unit includes: a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12; a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, and an eighteenth MOS transistor M18.

[0098] The first end of the seventh MOS transistor M7, the first end of the eighth MOS transistor M8, the first end of the ninth MOS transistor M9, the first end of the tenth MOS transistor M10, the first end of the eleventh MOS transistor M11, the first end of the twelfth MOS transistor M12, the first end of the thirteenth MOS transistor M13, and the first end of the fourteenth MOS transistor M14 all receive differential input signals NRZP and NRZN. The differential input signals NRZP and NRZN are Figure 4 The signal output by OUTN and OUTP.

[0099] The second end of the seventh MOS transistor M7 , the second end of the tenth MOS transistor M10 , the second end of the eleventh MOS transistor M11 , and the second end of the fourteenth MOS transistor M14 are all connected and output the first return-to-zero code signal.

[0100] The second end of the eighth MOS transistor M8, the second end of the ninth MOS transistor M9, the second end of the twelfth MOS transistor M10, and the second end of the thirteenth MOS transistor M13 are all connected and output a first return-to-zero code signal. Figure 5 RZN and RZP together constitute the differential first return-to-zero code signal.

[0101] The third end of the seventh MOS transistor M7 is connected to the third end of the eighth MOS transistor M8, and both are connected to the second end of the fifteenth MOS transistor M15; the third end of the ninth MOS transistor M9 is connected to the third end of the tenth MOS transistor M10, and both are connected to the second end of the sixteenth MOS transistor M16.

[0102] The third end of the eleventh MOS transistor M11 is connected to the third end of the twelfth MOS transistor M12, and both are connected to the second end of the seventeenth MOS transistor M17; the third end of the thirteenth MOS transistor M13 is connected to the third end of the fourteenth MOS transistor M14, and both are connected to the second end of the eighteenth MOS transistor M18.

[0103] The first end of the fifteenth MOS transistor M15 and the first end of the sixteenth MOS transistor M16 receive the clock signals CLKP and CLKN respectively; the first end of the seventeenth MOS transistor M17 and the first end of the eighteenth MOS transistor M18 receive the bias voltage signal V BIASP and V BIASN .

[0104] A third end of the fifteenth MOS transistor M15 and a third end of the sixteenth MOS transistor M16 are connected, and are both connected to the second current source I2, and are grounded through the second current source I2; a third end of the seventeenth MOS transistor M17 and a third end of the eighteenth MOS transistor M18 are connected, and are both connected to the third current source I3, and are grounded through the third current source I3.

[0105] In addition, after the second end of the seventh MOS transistor M7, the second end of the tenth MOS transistor M10, the second end of the eleventh MOS transistor M11, and the second end of the fourteenth MOS transistor M14 are all connected, they are further connected to the third power supply VDD3 via a group of series resistors and inductors. After the second end of the eighth MOS transistor M8, the second end of the ninth MOS transistor M9, the second end of the twelfth MOS transistor M12, and the second end of the thirteenth MOS transistor M13 are all connected, they are further connected to the fourth power supply VDD4 via a group of series resistors and inductors.

[0106] NRZN and NRZP are the input differential data signals in NRZ format. The RZ signal is generated by adding the signal generated by the right-half circuit to the signal mixed by the left-half clock signals CLKP and CLKN. Bias voltages VBIASP and VBIASN are used to adjust the weight and sign of the added original signal, thereby implementing a 2-tap feedforward equalization function. RZP and RZN are the output differential data signals, i.e., return-to-zero signals in RZ format.

[0107] above Figure 4 、 Figure 5 The specific structure is shown as an example in order to better explain the structure of the analog combiner module ACM, and does not mean that the analog combiner module ACM can only have the above structure. All components and combinations that can achieve the above functions can be replaced accordingly.

[0108] Based on the above-mentioned DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuit, an embodiment of the present invention further proposes a high-speed serial port transmitter, which includes any of the above-mentioned DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuits.

[0109] Based on the above-mentioned DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuit, an embodiment of the present invention further provides an electronic device, which includes any of the above-mentioned DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuits.

[0110] Through the above examples, the DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuit provided by the present invention proposes a new DAC-based PAM4 (four-level pulse amplitude modulation) high-speed serial port transmitter architecture, which uses an analog combiner for data combining and can achieve feedforward equalization while combining.

[0111] The four-level pulse amplitude modulation high-speed serial port transmitter circuit operates at a high speed. Compared to traditional digital combiners, this analog combiner DAC architecture has the advantage of using CML differential pairs, which increases switching speed and enables higher combining rates. Furthermore, the simple output stage structure facilitates the integration of inductors at the load end, enabling the use of inductor peaking technology to further expand bandwidth. Simulations have verified that this architecture can achieve an output data rate of 144Gb / s using a 65nm CMOS process, comparable to world-leading results using FinFET technology. The higher transistor cutoff frequency, faster switch turn-on speed, and shorter trace distances achieved by advanced processes can further improve the architecture's maximum operating rate.

[0112] The circuit structure of a four-level pulse amplitude modulation high-speed serial transmitter is simplified and compact. Conventional serial transmitter architectures require extensive retiming circuitry and numerous parallel data paths to implement feedforward equalization. The analog-combining-based feedforward equalization architecture of the present invention reduces the number of parallel data paths, simplifying the transmitter structure while avoiding the need for large-scale transistor arrays in the output stage, thereby reducing parasitic capacitance at the output node.

[0113] The four-level pulse amplitude modulation high-speed serial port transmitter circuit has low power consumption. The feedforward equalization architecture of the present invention reduces the number of parallel data paths, thereby saving power in the corresponding data paths. Furthermore, the smaller data path load reduces the clock driver requirements and reduces the clock driver power consumption.

[0114] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0115] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuit, characterized in that: The four-level pulse amplitude modulation high-speed serial port transmitter circuit includes: a low-speed digital combiner, a four-level pulse amplitude modulation module, an analog combiner module and a clock generation module; The low-speed digital combiner receives multiple parallel low-speed non-return-to-zero code data signals, combines them, generates 8 high-speed non-return-to-zero code data signals and transmits them to the four-level pulse amplitude modulation module; The four-level pulse amplitude modulation module receives the eight-channel high-speed non-return-to-zero code data signals, converts them into four-channel four-level pulse amplitude modulation signals, and transmits them to the analog combining module; The analog combining module receives the four-way four-level pulse amplitude modulation signals, combines them, and performs 2-tap feedforward equalization to generate one-way serial high-speed data signal for output; The clock generation module is connected to the low-speed digital combiner and the analog combiner module respectively, and the clock generation module is used to provide a clock signal to the low-speed digital combiner and the analog combiner module; The one-channel serial high-speed data signal output by the analog combining module is bandwidth-expanded by using inductive peaking technology before being output off-chip; The analog combiner module includes: a first 2:1 analog combiner, a second 2:1 analog combiner, a first return-to-zero code generating unit, a second return-to-zero code generating unit, and a return-to-zero code summing unit; The first 2:1 analog combiner receives any two four-level pulse amplitude modulation signals from the four four-level pulse amplitude modulation signals, and the second 2:1 analog combiner receives the remaining two four-level pulse amplitude modulation signals from the four four-level pulse amplitude modulation signals; The first 2:1 analog combiner combines the two received four-level pulse amplitude modulation signals to obtain a first four-level pulse amplitude modulation signal with a higher frequency and transmits the signal to the first return-to-zero code generating unit; The second 2:1 analog combiner combines the two received four-level pulse amplitude modulation signals to obtain a second four-level pulse amplitude modulation signal with a higher frequency and transmits the signal to the second return-to-zero code generating unit; The first return-to-zero code generating unit converts the first four-level pulse amplitude modulation signal with a higher frequency into a first return-to-zero code signal, and transmits the first return-to-zero code signal to the return-to-zero code summing unit; The second return-to-zero code generating unit converts the second four-level pulse amplitude modulation signal with a higher frequency into a second return-to-zero code signal, and transmits the second return-to-zero code signal to the return-to-zero code summing unit; The return-to-zero code summing unit performs staggered addition of the first return-to-zero code signal and the second return-to-zero code signal to obtain the one-channel serial high-speed data signal.

2. The four-level pulse amplitude modulation high-speed serial port transmitter circuit according to claim 1, characterized in that: The two four-level pulse amplitude modulation signals are two differential data signals; The first 2:1 analog combiner and the second 2:1 analog combiner have the same structure. The first 2:1 analog combiner includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor; The first end of the first MOS transistor and the first end of the second MOS transistor respectively receive one differential data signal of the two differential data signals, and the first end of the third MOS transistor and the first end of the fourth MOS transistor respectively receive the other differential data signal of the two four-level pulse amplitude modulation signals; The second end of the first MOS transistor is connected to the second end of the third MOS transistor, and outputs the first four-level pulse amplitude modulation signal with a higher frequency; The third end of the first MOS transistor and the third end of the second MOS transistor are connected, and both are connected to the second end of the fifth MOS transistor; The second end of the second MOS transistor is connected to the second end of the fourth MOS transistor, and outputs the first four-level pulse amplitude modulation signal with a higher frequency; The third end of the third MOS transistor is connected to the third end of the fourth MOS transistor, and both are connected to the second end of the sixth MOS transistor; The first end of the fifth MOS transistor and the first end of the sixth MOS transistor respectively receive the clock signal, where the clock signal is a differential clock signal; The third end of the fifth MOS transistor and the third end of the sixth MOS transistor are connected, and are both connected to the first current source and grounded through the first current source; Wherein, after the second end of the first MOS transistor and the second end of the third MOS transistor are connected, they are also connected to the first power supply through a set of resistors and inductors connected in series; After the second end of the second MOS transistor is connected to the second end of the fourth MOS transistor, the second end is further connected to a second power supply through a group of resistors and inductors connected in series.

3. The four-level pulse amplitude modulation high-speed serial port transmitter circuit according to claim 2, characterized in that: The first four-level pulse amplitude modulation signal with a higher frequency and the second four-level pulse amplitude modulation signal with a higher frequency are both differential input signals; The first return-to-zero code generating unit and the second return-to-zero code generating unit have the same structure. The first return-to-zero code generating unit includes: a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor; a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, and an eighteenth MOS transistor; The first end of the seventh MOS transistor, the first end of the eighth MOS transistor, the first end of the ninth MOS transistor, the first end of the tenth MOS transistor, the first end of the eleventh MOS transistor, the first end of the twelfth MOS transistor, the first end of the thirteenth MOS transistor, and the first end of the fourteenth MOS transistor all receive the differential input signal; The second end of the seventh MOS transistor, the second end of the tenth MOS transistor, the second end of the eleventh MOS transistor, and the second end of the fourteenth MOS transistor are all connected and output the first return-to-zero code signal; The second end of the eighth MOS transistor, the second end of the ninth MOS transistor, the second end of the twelfth MOS transistor, and the second end of the thirteenth MOS transistor are all connected and output the first return-to-zero code signal; The third end of the seventh MOS transistor is connected to the third end of the eighth MOS transistor, and both are connected to the second end of the fifteenth MOS transistor; The third end of the ninth MOS transistor is connected to the third end of the tenth MOS transistor, and both are connected to the second end of the sixteenth MOS transistor; The third end of the eleventh MOS transistor is connected to the third end of the twelfth MOS transistor, and both are connected to the second end of the seventeenth MOS transistor; The third end of the thirteenth MOS transistor is connected to the third end of the fourteenth MOS transistor, and both are connected to the second end of the eighteenth MOS transistor; The first end of the fifteenth MOS transistor and the first end of the sixteenth MOS transistor respectively receive the clock signal; The first end of the seventeenth MOS transistor and the first end of the eighteenth MOS transistor respectively receive a bias voltage; The third end of the fifteenth MOS transistor and the third end of the sixteenth MOS transistor are connected, and are both connected to the second current source and grounded through the second current source; The third end of the seventeenth MOS transistor and the third end of the eighteenth MOS transistor are connected, and are both connected to a third current source and grounded through the third current source; The second end of the seventh MOS transistor, the second end of the tenth MOS transistor, the second end of the eleventh MOS transistor, and the second end of the fourteenth MOS transistor are all connected and then connected to a third power supply through a group of resistors and inductors connected in series. The second end of the eighth MOS transistor, the second end of the ninth MOS transistor, the second end of the twelfth MOS transistor, and the second end of the thirteenth MOS transistor are all connected and then connected to a fourth power supply through a group of series-connected resistors and inductors.

4. The four-level pulse amplitude modulation high-speed serial port transmitter circuit according to claim 1, characterized in that: The low-speed digital combiner adopts serial port technology for processing, and realizes the function of synthesizing the multiple parallel low-speed non-return-to-zero code data signals into 8 high-speed non-return-to-zero code data signals by cascading multiple-stage combiners; The number of cascade stages of the multi-stage combiner cascade is determined by the number of the multi-channel parallel low-speed non-return-to-zero code data signals.

5. The four-level pulse amplitude modulation high-speed serial port transmitter circuit according to claim 1, characterized in that: The four-level pulse amplitude modulation module includes: two sets of differential amplifiers with adjustable tail current sources, wherein the magnitude of the differential pair tail current corresponding to the MSB is twice the magnitude of the differential pair tail current corresponding to the LSB; Two groups of CML structure differential amplifiers are connected to the same output, and the voltages generated by the two currents flowing through the load are the four-channel four-level pulse amplitude modulation signals obtained by conversion.

6. The four-level pulse amplitude modulation high-speed serial port transmitter circuit according to claim 1, characterized in that: The clock generation module includes: a driver, a frequency divider and a phase interpolator, wherein the frequency divider is used to generate a low-speed clock from a high-speed clock, and the phase interpolator is used to adjust the relative phase of the clocks between different cascaded combiners.

7. The four-level pulse amplitude modulation high-speed serial port transmitter circuit according to claim 5, characterized in that: The multi-channel parallel low-speed non-return-to-zero code data signals are 160-channel parallel low-speed non-return-to-zero code data signals generated by a pseudo-random binary sequence signal source.

8. A high-speed serial port transmitter, characterized in that: The high-speed serial port transmitter comprises the DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuit according to any one of claims 1-7.

9. An electronic device, characterized in that: The electronic device comprises the DAC-based four-level pulse amplitude modulation high-speed serial port transmitter circuit according to any one of claims 1-7.

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