Ultra-small image acquisition and processing system packaging structure and preparation method

Abstract

The present invention discloses a packaging structure and preparation method of an ultra-small image acquisition and processing system, including: optically coated glass, a protective film is provided on the first surface, and a dam around the second surface is connected to the first surface of a CMOS chip; the first surface of the CMOS chip is provided with a photosensitive and micro-lens area and a metal bonding pad, and a silicon through hole is etched on the second surface until it extends to the metal bonding pad on the first surface; a wafer redistribution layer covers the second surface of the CMOS chip and extends to the silicon through hole, and the outermost layer of the wafer redistribution layer is provided with a main controller, an image processor, an encoder, Flash, a power supply and a connection board; a plastic sealing layer plastic seals the second surface of the CMOS chip, and solder balls are provided on the outside of the plastic sealing layer to lead out the external electrical interface of the system. The structure and method of the present invention integrate wafer-level packaging and SIP integrated packaging process technology to realize a single-body packaging of the entire device, greatly reducing system complexity and power consumption, reducing the overall product size and signal path, and improving the image anti-interference ability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to an ultra-small image acquisition and processing system packaging structure and a preparation method thereof. Background Art

[0002] The image acquisition and processing system generally includes an image sensor, an image signal processor (ISP), an image encoder, and a main controller. The camera module only provides image acquisition, outputs digital or analog image information to the back-end ISP or codec chip for image optimization, encoding and compression, and the main control chip controls the final data transmission and storage. In the image acquisition and processing system, the conventional solution image acquisition, processing, encoding and compression, and system control are completed by different chips and different modules, and there are at least two chips or two modules. This invention provides a highly integrated system-on-chip or module solution at the packaging level.

[0003] The integration direction of traditional image processing systems is generally to integrate ISP and encoder into the main control chip to simplify the entire image acquisition and processing system. However, this solution often needs to consider the versatility of the main control SOC chip system, which makes the main control SOC chip system too large for some applications, with high power consumption and large package size. In addition, the image sensor is still packaged as an independent chip, which makes the entire system complicated and not conducive to its application in the field of microelectronics and wearable products. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention provides a packaging structure and a preparation method of an ultra-small image acquisition and processing system.

[0005] In order to solve the above technical problems, the present invention is solved by the following technical solutions:

[0006] An ultra-small image acquisition and processing system packaging structure, comprising:

[0007] Optical coated glass, wherein a protective film is provided on a first surface of the optical coated glass, and a cofferdam is formed around a second surface of the optical coated glass;

[0008] A CMOS chip, wherein a photosensitive and micro-lens area and a metal bonding pad are provided on a first surface of the CMOS chip, and a through-silicon via is etched on a second surface of the CMOS chip until it extends to the metal bonding pad on the first surface, wherein the cofferdam seamlessly connects the metal bonding pad and the peripheral edge area of ​​the CMOS chip through an adhesive film and covers the first surface of the CMOS chip to form a cavity, and the photosensitive and micro-lens area is located in the cavity;

[0009] A wafer redistribution layer, wherein the first layer of the wafer redistribution layer covers the second surface of the CMOS chip and extends to the through-silicon via region, and the outermost layer of the wafer redistribution layer is provided with an image processor and an encoder, a main controller, a power supply and a connection board;

[0010] A plastic sealing layer is used to seal the second surface of the CMOS chip. Solder balls are arranged on the outer side of the plastic sealing layer, and the positions of the solder balls and the connecting plate correspond to each other.

[0011] As an implementation method, the wafer redistribution layer includes a passivation layer and a metal routing layer bonded to each other, and the number of layers of the passivation layer is one more than the number of layers of the metal routing layer;

[0012] The first layer of the wafer redistribution layer is a passivation layer, and the outermost layer of the wafer redistribution layer is a passivation layer.

[0013] As an implementation method, the metal wiring layer is two layers, namely, a first metal wiring layer and a second metal wiring layer, and the passivation layer is three layers, namely, a first passivation layer, a second passivation layer and a third passivation layer;

[0014] The first passivation layer covers the second surface of the CMOS chip and extends to the silicon through via area, the first metal routing layer covers the first passivation layer and extends into the silicon through via so that the first surface and the second surface of the CMOS chip are electrically connected, and the second passivation layer, the second metal routing layer and the third passivation layer sequentially cover the first metal routing layer.

[0015] As an implementable embodiment, the metal wiring layer has three layers or more, and the passivation layer has four layers or more.

[0016] As an implementation method, the material of the protective film is metal, polymer or a mixture of metal and polymer.

[0017] As an implementable embodiment, the height of the connecting plate is respectively higher than the heights of the image processor and encoder, the main controller, the Flash, the power supply and other units.

[0018] As an implementable embodiment, the image processor and encoder, main controller, Flash, power supply and other units are connected through flip-chip tiling or wire bonding stacking design and through metal routing layers or metal bonding wires.

[0019] A method for preparing a packaging structure of an ultra-small image acquisition and processing system comprises the following steps:

[0020] Providing an optical coated glass, wherein a protective film is formed on a first surface of the optical coated glass, and a cofferdam is formed around a second surface of the optical coated glass;

[0021] A CMOS chip is provided, wherein a photosensitive and micro-lens area and a metal bonding pad are provided on a first surface of the CMOS chip, and a through-silicon via is etched on a second surface of the CMOS chip until it extends to the metal bonding pad on the first surface, wherein the cofferdam seamlessly connects the metal bonding pad and the peripheral edge area of ​​the CMOS chip through an adhesive film and covers the first surface of the CMOS chip to form a cavity, and the photosensitive and micro-lens area is located in the cavity;

[0022] Forming a wafer redistribution layer, wherein the first layer of the wafer redistribution layer covers the second surface of the CMOS chip and extends to the through silicon via region, and the outermost layer of the wafer redistribution layer is provided with an image processor and an encoder, a main controller, a Flash, a power supply and a connection board;

[0023] A plastic sealing layer is formed, wherein the plastic sealing layer seals the second surface of the CMOS chip, and solder balls are arranged on the outer side of the plastic sealing layer, and the positions of the solder balls and the connecting plate correspond to each other.

[0024] As an implementation method, the wafer redistribution layer includes a passivation layer and a metal routing layer bonded to each other, and the number of layers of the passivation layer is one more than the number of layers of the metal routing layer;

[0025] The first layer of the wafer redistribution layer is a passivation layer, and the outermost layer of the wafer redistribution layer is a passivation layer.

[0026] As an implementation method, the metal wiring layer is two layers, namely, a first metal wiring layer and a second metal wiring layer, and the passivation layer is three layers, namely, a first passivation layer, a second passivation layer and a third passivation layer;

[0027] The first passivation layer covers the second surface of the CMOS chip and extends to the silicon through via area, the first metal routing layer covers the first passivation layer and extends into the silicon through via so that the first surface and the second surface of the CMOS chip are electrically connected, and the second passivation layer, the second metal routing layer and the third passivation layer sequentially cover the first metal routing layer.

[0028] As an implementation method, the second surface of the CMOS chip is first passivated and patterned to form a first passivation layer;

[0029] Generating a first metal wiring layer on the first passivation layer;

[0030] Performing a second passivation and patterning on the first metal wiring layer to form a second passivation layer;

[0031] Generating a second metal wiring layer on the second passivation layer;

[0032] A third passivation and patterning are performed on the second metal wiring layer to form a third passivation layer.

[0033] As an implementable embodiment, the image processor and encoder, main controller, power supply and connection board are mounted on the outermost layer of the wafer redistribution layer or connected through a conductive structure.

[0034] As an implementable embodiment, the image processor and the encoder, main controller, power supply and other units are connected through a flip-chip tiled or wire-bonded stacking design and through metal routing layers or metal bonding wires.

[0035] As an implementable method, the following steps are also included:

[0036] The plastic sealing layer may be embedded in the plastic sealing film or conventionally plastic sealed and then ground to expose the connecting plate;

[0037] Solder balls are installed on the connection board, panel cutting and final testing are performed.

[0038] The present invention has significant technical effects due to the adoption of the above technical solution:

[0039] The present invention adopts a CMOS chip, an image processor, an encoder, and a control system packaging integration solution. The control system is used for system control and data transmission, so the system resource requirements are not high. The design adopts a low-power microprocessor to complete related functions, thereby reducing the burden on the entire system.

[0040] Through the packaging process, the CMOS chip, image processor (to be precise, image signal processor ISP), encoder (to be precise, image encoder), main controller, Flash, power supply, clock and other required extended function units are integrated into a packaging structure. The system formed by the entire packaging structure can realize a single-body design, reduce the overall product size and signal path, improve the image's anti-interference ability, greatly reduce the system's complexity and power consumption, and the system structure is compact. It can be widely used in application scenarios that have strict requirements on the size of image modules, such as medical capsule cameras, industrial micro cameras or wearable products. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0042] Figure 1 It is a schematic diagram of the overall structure of the packaging structure;

[0043] Figure 2is a schematic diagram of the overall structure of another embodiment of the packaging structure;

[0044] Figure 3-Figure 15 is a schematic diagram of the preparation method.

[0045] Description of the reference numerals in the accompanying drawings:

[0046] 1. CMOS chip; 2. Image processor and encoder; 3. Main controller; 4. Power supply; 5. Optically coated glass; 6. Cavity; 7. Cofferdam; 8. Adhesive film; 9. Metal bonding pad; 10. Plastic encapsulation layer; 11. Connecting plate; 12. Solder ball; 13. Through silicon via; 14. First passivation layer; 15. First metal routing layer; 16. Second passivation layer; 17. Second metal routing layer; 18. Third passivation layer; 19. Protective film; 20. Connecting wire; 21. Photosensitive and micro-lens area; 30. Wafer redistribution layer. DETAILED DESCRIPTION

[0047] The present invention is further described in detail below in conjunction with embodiments. The following embodiments are for explanation of the present invention but the present invention is not limited to the following embodiments.

[0048] In the existing technology, for wearable electronic products such as medical capsule mirrors, industrial micro cameras, AR / VR glasses, smart watches, police communications, mine safety modules, etc., due to strict requirements on volume and power consumption, it is necessary to design an ultra-small image acquisition and processing system packaging structure, which is not only compact but also can greatly improve the flexibility of the entire image acquisition and processing system and the convenience of structural design.

[0049] Example structure:

[0050] An ultra-small image acquisition and processing system packaging structure, such as Figure 1As shown, it comprises: an optical coated glass 5, a protective film 19 is provided on the first surface of the optical coated glass 5, and a cofferdam 7 is formed around the second surface of the optical coated glass 5; a CMOS chip 1, a photosensitive and micro-lens area 21 and a metal bonding pad 9 are provided on the first surface of the CMOS chip 1, and a through silicon via 13 is etched on the second surface of the CMOS chip 1 until it extends to the metal bonding pad 9, wherein the cofferdam 7 seamlessly connects the metal bonding pad 9 and the edge area around the CMOS chip 1 through an adhesive film 8 and the first surface of the CMOS chip 1 A surface is covered to form a cavity 6, and the photosensitive and micro-lens area 21 is located in the cavity 6; a wafer redistribution layer 30, the first layer of the wafer redistribution layer 30 covers the second surface of the CMOS chip 1 and extends to the silicon through-hole 13 area, and the outermost layer of the wafer redistribution layer 30 is provided with an image processor and encoder 2, a main controller 3, a power supply 4 and a connecting board 11; a plastic sealing layer 10, the plastic sealing layer 10 plastic seals the second surface of the CMOS chip 1, and a solder ball 12 is provided on the outside of the plastic sealing layer 10, and the position of the solder ball 12 corresponds to that of the connecting board 11. Of course, the solder ball can also be a pad or a bump, as long as it can be welded, and its shape is not limited.

[0051] The photosensitive and micro-lens area 21 is located on the first surface of the CMOS chip 1. In addition to the main controller 3, image processor and encoder 2, power supply 4, other necessary units such as Flash, clock, discrete devices and other units are also set on the second surface of the CMOS chip 1, which can be set as needed. The components are mainly packaged in WLP or FC to save the mounting area. The power supply 4, clock, discrete devices, resistor and capacitor devices and other units are packaged in small size chips. The main controller 3 controls and manages other functional chips and image sensors through the control bus (I2C bus / SIP bus / GPIO), and provides an external data interface to send out the optimized processed and encoded image information. The data bus, control bus, power supply 4, etc. realize the electrical signal interconnection between the first surface and the second surface of the CMOS chip 1 through silicon vias 13. Other signals and power supply 4 are interconnected through the metal wiring layer of the wafer redistribution layer 30. The number of metal wiring layers can be adjusted according to actual design requirements, such as 2 layers, 3 layers or other number layers.

[0052] After the image information is received by the photosensitive and micro-lens area 21, the CMOS chip 1 realizes photoelectric conversion and outputs the image data, and then the image processor and encoder 2 are processed by relevant algorithms, corrected and de-noised, and then encoded and compressed and output to the main controller 3. The main controller 3 can store the final image data locally, upload it to the host computer, or send it through a wireless transmitter according to application needs. The control system controls and manages the entire ultra-small image acquisition and processing system packaging structure through a bus such as an I2C bus, an SPI bus, or a GPIO line.

[0053] Embodiment 1:

[0054] This embodiment takes two layers of metal wiring layers as an example, an ultra-small image acquisition and processing system packaging structure, such as Figure 1 As shown, it includes: an optically coated glass 5, a protective film 19 is provided on the first surface of the optically coated glass 5, and a cofferdam 7 is formed around the second surface of the optically coated glass 5; a CMOS chip 1, a photosensitive and micro-lens area 21 and a metal bonding pad 9 are provided on the first surface of the CMOS chip 1, and a silicon through hole 13 is etched on the second surface of the CMOS chip 1 until it extends to the metal bonding pad 9, wherein the cofferdam 7 seamlessly connects the metal bonding pad 9 and the edge area around the CMOS chip 1 through an adhesive film 8 and covers the first surface of the CMOS chip 1 to form a cavity 6, and the photosensitive and micro-lens area 21 is located in the cavity 6; a wafer redistribution layer 30, a first layer of the wafer redistribution layer 30 covers the second surface of the CMOS chip 1 and extends to the silicon through hole 13 area, and the outermost layer of the wafer redistribution layer 30 is provided with an image processor and encoder 2, a main controller 3, a power supply 4 and a connecting board 11; a plastic sealing layer 10, the plastic sealing layer 10 plastic seals the second surface of the CMOS chip 1, and a solder ball 12 is provided on the outer side of the plastic sealing layer 10, and the positions of the solder ball 12 and the connecting board 11 correspond to each other.

[0055] When the metal wiring layer is two layers, namely the first metal wiring layer 15 and the second metal wiring layer 17, the passivation layer is three layers, namely the first passivation layer 14, the second passivation layer 16 and the third passivation layer 18; the first passivation layer 14 covers the second surface of the CMOS chip 1 and extends to the silicon through-via 13 area, the first metal wiring layer 15 covers the first passivation layer 14, and the second passivation layer 16, the second metal wiring layer 17 and the third passivation layer 18 sequentially cover the first metal wiring layer 15.

[0056] In order to make the image processor and encoder 2, main controller 3, power supply 4 and other units safer and more stable, the height of the connecting plate 11 is higher than the heights of the image processor and encoder 2, main controller 3, power supply 4 and other units.

[0057] The material of the first surface protective film 19 of the optical coated glass 5 is metal, polymer or a mixture of metal and polymer. Here, there is no requirement for the material of the metal or the polymer. The protective film is used to protect the optical coated glass during processing and transportation, and prevent dust and scratches.

[0058] Embodiment 2:

[0059] The difference between this embodiment and embodiment 1 is that, in order to reduce the plane size of the packaging structure of the ultra-small image acquisition and processing system, Figure 2As shown, the second surface packaging area of ​​the CMOS chip 1 is designed as a stacked packaging structure, and some functional chips (such as the main controller 3) using WB packaging can be stacked on the image processor and the encoder 2, and signal interconnection is achieved through the connecting wire 20, thereby further reducing the planar size of the entire packaging structure.

[0060] Exemplary methods:

[0061] A method for preparing a packaging structure of an ultra-small image acquisition and processing system comprises the following steps:

[0062] Providing an optical coated glass 5, a protective film 19 is formed on a first surface of the optical coated glass 5, and a cofferdam 7 is formed around a second surface of the optical coated glass 5;

[0063] A CMOS chip 1 is provided, wherein a photosensitive and micro-lens region 21 and a metal bonding pad 9 are provided on a first surface of the CMOS chip 1, and a through-silicon via 13 is etched on a second surface of the CMOS chip 1 until it extends to the metal bonding pad 9, wherein a cofferdam 7 seamlessly connects the metal bonding pad 9 and the peripheral edge region of the CMOS chip 1 through an adhesive film 8, and covers the first surface of the CMOS chip 1 to form a cavity 6, wherein the photosensitive and micro-lens region 21 is located in the cavity 6;

[0064] A wafer redistribution layer 30 is formed, wherein the first layer of the wafer redistribution layer 30 covers the second surface of the CMOS chip 1 and extends into the through silicon via 13, and the outermost layer of the wafer redistribution layer 30 is provided with an image processor and encoder 2, a main controller 3, a power supply 4 and a connection board 11;

[0065] A plastic encapsulation layer 10 is formed, and the plastic encapsulation layer 10 encapsulates the second surface of the CMOS chip 1. A solder ball 12 is arranged outside the plastic encapsulation layer 10, and the positions of the solder ball 12 and the connection board 11 correspond to each other. Of course, the solder ball can also be a pad or a bump, and its shape is not limited as long as it can achieve welding.

[0066] The photosensitive and micro-lens area 21 of the ultra-small image acquisition and processing system packaging structure produced by this preparation method is located on the first surface of the CMOS chip 1, and the main controller 3, image processor and encoder 2, power supply 4, clock, discrete devices and other units are located on the second surface of the CMOS chip 1. The main controller 3, image processor and encoder 2 and other chips with larger sizes are packaged in WLP or FC, and other chips are packaged in WB and arranged on the upper surface of the large-size chip to achieve 3D stacking and save mounting area. The power supply 4, clock, discrete devices and other units or resistors and capacitors are packaged in small-size chips. The main controller 3 controls and manages other functional chips and image sensors through the control bus (I2C bus / SIP bus / GPIO), and provides an external data interface to send out optimized processed and encoded image information. The data bus, control bus, power supply 4, etc. realize the electrical signal interconnection between the first surface and the second surface of the CMOS chip 1 through TSV (Through Silicon Via). Other signals and power supply 4 are interconnected through the metal wiring layer of the wafer redistribution layer 30. The number of metal line layers can be adjusted according to actual design requirements, such as 2 layers, 3 layers or other layers.

[0067] After the image information is received by the photosensitive and micro-lens area 21, the CMOS chip 1 realizes photoelectric conversion and outputs image data, and then after the image processor and encoder 2 are processed by relevant algorithms, correction and noise reduction, the image information is encoded and compressed and output to the main controller 3. The main controller 3 can store the final image data locally, upload it to the host computer, or send it through a wireless transmitter according to application needs. The control system controls and manages the entire ultra-small image acquisition and processing system packaging structure through a bus such as an I2C bus, an SPI bus, or a GPIO line.

[0068] Embodiment 3:

[0069] This embodiment takes two layers of metal wiring layers as an example, and a method for preparing a packaging structure of an ultra-small image acquisition and processing system includes the following steps:

[0070] like Figure 3 As shown, an optical coated glass 5 is provided, and a cofferdam 7 is formed around the second surface of the optical coated glass 5;

[0071] like Figure 4 As shown, a CMOS chip 1 is provided, a first surface of the CMOS chip 1 is provided with a photosensitive and micro-lens area 21 and a metal bonding pad 9, a through-silicon via 13 is etched on the second surface of the CMOS chip 1 until it extends to the metal bonding pad 9, wherein a cofferdam 7 connects the metal bonding pad 9 and the peripheral edge area of ​​the CMOS chip 1 through an adhesive film 8, and the first surface of the CMOS chip 1 is covered to form a cavity 6 which can be sealed by the adhesive film 8, and the photosensitive and micro-lens area 21 is located in the cavity 6;

[0072] like Figure 5 As shown, a protective film 19 is formed on the first surface of the optical coated glass 5;

[0073] like Figure 6-Figure 12 As shown, a through silicon via 13 region is formed on the second surface of the CMOS chip 1, and the through silicon via 13 sequentially penetrates the CMOS chip, the metal bonding pad 9 and extends to the inside of the cofferdam 7;

[0074] A wafer redistribution layer 30 is formed, and the wafer redistribution layer 30 has two metal routing layers, namely a first metal routing layer 15 and a second metal routing layer 17, and three passivation layers, namely a first passivation layer 14, a second passivation layer 16 and a third passivation layer 18; the first passivation layer 14 covers the second surface of the CMOS chip 1 and extends to a portion of the through silicon via 13 area, the first metal routing layer 15 covers above the first passivation layer 14 and extends into the through silicon via so that the first surface and the second surface of the CMOS chip 1 are electrically connected, and the second passivation layer 16, the second metal routing layer 17 and the third passivation layer 18 are sequentially covered on the first metal routing layer 15.

[0075] The specific process of forming the wafer redistribution layer 30 is as follows: the second surface of the CMOS chip 1 is first passivated and patterned to form a first passivation layer 14, and part of the first passivation layer 14 extends to part of the through silicon via 13 area;

[0076] A first metal wiring layer 15 is generated on the first passivation layer 14, and the first metal wiring layer 15 is electrically connected to the metal bonding pad 9 through the through silicon via 13;

[0077] Performing a second passivation and patterning on the first metal wiring layer 15 to form a second passivation layer 16;

[0078] Generating a second metal wiring layer 17 on the second passivation layer 16;

[0079] Performing a third passivation and patterning on the second metal wiring layer 17 to form a third passivation layer 18, with a portion of the second metal wiring layer 17 exposed;

[0080] like Fig.13 As shown, the image processor and encoder 2, the main controller 3, the power supply 4 and the connecting board 11 are mounted on the outermost layer of the wafer redistribution layer 30 (i.e., the third passivation layer 18 and the partially exposed second metal wiring layer 17), and the image processor and encoder 2, the main controller 3, the power supply 4 and the connecting board 11 are electrically connected to the CMOS chip 1 through the wafer redistribution layer 30;

[0081] like Fig.14 As shown, a plastic encapsulation layer 10 is formed, and the plastic encapsulation layer 10 encapsulates the second surface of the CMOS chip 1. Fig.15As shown, solder balls 12 are arranged on the outer side of the plastic packaging layer 10 and at corresponding positions of the connecting plate 11 , and the solder balls 12 are used to achieve external connection.

[0082] In addition, in one embodiment, the following steps are also included: the plastic encapsulation layer 10 is embedded in the plastic encapsulation through a film or conventionally encapsulated and then polished to expose the connecting board 11; solder balls 12 are installed on the connecting board 11, the panels are cut and finally tested (this step is not shown).

[0083] Embodiment 4:

[0084] The difference between this embodiment and embodiment 3 is that: in order to reduce the plane size of the packaging structure of the ultra-small image acquisition and processing system, such as Figure 2 The second surface area of ​​the CMOS chip 1 shown can be designed as a stacked package. Some functional chips (such as the main controller 3) using WB packaging can be stacked on the image processor and the encoder 2, and signal interconnection can be achieved through WB, thereby further reducing the size of the entire packaging module.

[0085] In addition, it should be noted that the shapes and names of the parts and components of the specific embodiments described in this specification may be different. Any equivalent or simple changes made based on the structure, features and principles described in the patent concept of the present invention are included in the protection scope of the patent of the present invention. The technicians in the technical field of the present invention can make various modifications or supplements to the specific embodiments described or replace them in a similar manner, as long as they do not deviate from the structure of the present invention or exceed the scope defined by the claims, they should all fall within the protection scope of the present invention.

Claims

1. An ultra-small image acquisition and processing system packaging structure, It is characterized in that include: Optical coated glass, wherein a protective film is provided on a first surface of the optical coated glass, and a cofferdam is formed around a second surface of the optical coated glass; A CMOS chip, wherein a photosensitive and micro-lens area and a metal bonding pad are provided on a first surface of the CMOS chip, a through-silicon via is etched on a second surface of the CMOS chip until it extends into the metal bonding pad on the first surface, the cofferdam seamlessly connects the metal bonding pad and the peripheral edge area of ​​the CMOS chip through an adhesive film and covers the first surface of the CMOS chip to form a cavity, and the photosensitive and micro-lens area is located in the cavity; A wafer redistribution layer, wherein the first layer of the wafer redistribution layer covers the second surface of the CMOS chip and extends to the through-silicon via region, and the outermost layer of the wafer redistribution layer is provided with an image processor and an encoder, a main controller, a Flash, a power supply and a connection board; A plastic sealing layer, wherein the plastic sealing layer seals the second surface of the CMOS chip, and solder balls are arranged on the outer side of the plastic sealing layer, and the positions of the solder balls and the connecting plate correspond to each other; Among them, the wafer redistribution layer includes a passivation layer and a metal routing layer bonded to each other, and the number of passivation layers is one more than the number of metal routing layers; the first layer of the wafer redistribution layer is the passivation layer, the outermost layer of the wafer redistribution layer is the passivation layer, and when the number of metal routing layers is more than one, one passivation layer is separated between two adjacent metal routing layers.

2. The ultra-small image acquisition and processing system packaging structure according to claim 1, It is characterized in that The metal wiring layer has two layers, namely, a first metal wiring layer and a second metal wiring layer, and the passivation layer has three layers, namely, a first passivation layer, a second passivation layer and a third passivation layer; The first passivation layer covers the second surface of the CMOS chip and extends to the silicon through via area, the first metal routing layer covers the first passivation layer and extends into the silicon through via so that the first surface and the second surface of the CMOS chip are electrically connected, and the second passivation layer, the second metal routing layer and the third passivation layer sequentially cover the first metal routing layer.

3. The ultra-small image acquisition and processing system packaging structure according to claim 1, It is characterized in that The metal wiring layer has three layers or more, and the passivation layer has four layers or more.

4. The ultra-small image acquisition and processing system packaging structure according to claim 1, It is characterized in that The material of the protective film is metal, polymer or a mixture of metal and polymer.

5. The ultra-small image acquisition and processing system packaging structure according to claim 1, It is characterized in that The height of the connecting plate is respectively higher than the heights of the image processor and the encoder, the main controller, the Flash, the power supply and other units.

6. The ultra-small image acquisition and processing system packaging structure according to claim 1, It is characterized in that The image processor and encoder, main controller, Flash, power supply and other units are connected through flip-chip tiling or wire bonding stacking design and through metal wiring layers or metal bonding wires.

7. A method for preparing a packaging structure of an ultra-small image acquisition and processing system, It is characterized in that The following steps are involved: Providing an optical coated glass, wherein a protective film is formed on a first surface of the optical coated glass, and a cofferdam is formed around a second surface of the optical coated glass; A CMOS chip is provided, wherein a photosensitive and micro-lens area and a metal bonding pad are provided on a first surface of the CMOS chip, and a through-silicon via is etched on a second surface of the CMOS chip until it extends to the metal bonding pad on the first surface, wherein the cofferdam seamlessly connects the metal bonding pad and the peripheral edge area of ​​the CMOS chip through an adhesive film and covers the first surface of the CMOS chip to form a cavity, wherein the photosensitive and micro-lens area is located in the cavity; a wafer redistribution layer is formed, wherein a first layer of the wafer redistribution layer covers the second surface of the CMOS chip and extends to the through-silicon via area, and an image processor and an encoder, a main controller, a Flash, a power supply and a connection board are provided on the outermost layer of the wafer redistribution layer; Forming a plastic sealing layer, wherein the plastic sealing layer seals the second surface of the CMOS chip, and solder balls are arranged on the outside of the plastic sealing layer, and the positions of the solder balls and the connecting plate correspond to each other; Among them, the wafer redistribution layer includes a passivation layer and a metal routing layer bonded to each other, and the number of passivation layers is one more than the number of metal routing layers; the first layer of the wafer redistribution layer is the passivation layer, the outermost layer of the wafer redistribution layer is the passivation layer, and when the number of metal routing layers is more than one, one passivation layer is separated between two adjacent metal routing layers.

8. The method for preparing the ultra-small image acquisition and processing system packaging structure according to claim 7, It is characterized in that The metal wiring layer has two layers, namely, a first metal wiring layer and a second metal wiring layer, and the passivation layer has three layers, namely, a first passivation layer, a second passivation layer and a third passivation layer; The first passivation layer covers the second surface of the CMOS chip and extends to a portion of the through-silicon via area, the first metal routing layer covers the first passivation layer and extends into the through-silicon via to electrically connect the first surface and the second surface of the CMOS chip, and the second passivation layer, the second metal routing layer and the third passivation layer sequentially cover the first metal routing layer.

9. The method for preparing the ultra-small image acquisition and processing system packaging structure according to claim 7, It is characterized in that The second surface of the CMOS chip is passivated and patterned for the first time to form a first passivation layer; Generating a first metal wiring layer on the first passivation layer; Performing a second passivation and patterning on the first metal wiring layer to form a second passivation layer; Generating a second metal wiring layer on the second passivation layer; A third passivation and patterning are performed on the second metal wiring layer to form a third passivation layer.

10. The method for preparing the ultra-small image acquisition and processing system packaging structure according to claim 7, It is characterized in that The image processor and encoder, main controller, Flash, power supply and connection board are mounted on the outermost layer of the wafer redistribution layer or connected through a conductive structure.

11. The method for preparing the ultra-small image acquisition and processing system packaging structure according to claim 7, It is characterized in that The image processor and encoder, main controller, Flash, power supply and other units are connected through flip-chip tiling or wire bonding stacking design and through metal wiring layers or metal bonding wires.

12. The method for preparing the ultra-small image acquisition and processing system packaging structure according to claim 7, It is characterized in that The following steps are also included: The plastic sealing layer may be embedded in the plastic sealing film or conventionally plastic sealed and then ground to expose the connecting plate; Solder balls are installed on the connection board, the panels are cut and finally tested.

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