Reducing current ripple due to mosfet switching delay in pwm-based drivers

Abstract

The subject matter of this specification can be embodied in, among other things, a method that includes receiving a first current output setpoint, identifying a first operating condition based on the first current output setpoint, providing a first pulse width modulation (PWM) signal having a first predetermined duty cycle based on the identified first operating condition, the first PWM signal being based on the first current output setpoint and provided for a predetermined time period, receiving a second current output setpoint, identifying a second operating condition different from the first operating condition based on the second current output setpoint, and providing a second PWM signal having a second predetermined duty cycle based on the identified second operating condition, the second PWM signal being based on the second current output setpoint and provided for a predetermined multiple of the predetermined time period.

Description

Technical Field

[0001] This manual relates to pulse width modulation (PWM) control systems. Background Technology

[0002] Pulse width modulation (PWM), or pulse duration modulation (PDM), is a method to reduce the average power delivered by an electrical signal. Typically, the electrical signal is chopped into a series of discrete pulses sent at a set frequency. PWM is particularly suitable for operating loads (such as motors) that are not easily affected by such discrete switching because they have inertia and react relatively slowly compared to the PWM frequency. The PWM switching frequency is set high enough that the resulting waveform, as perceived by the load, is relatively smooth.

[0003] The pulse width (e.g., duty cycle) relative to the period duration (e.g., wavelength) can vary. A 100% duty cycle effectively allows the electrical signal to remain "on" or "high" and effectively supplies 100% of the current of that signal to the load. A 0% duty cycle effectively keeps the electrical signal "off" or "low" and effectively supplies zero current to the load. A 50% duty cycle effectively supplies 50% of the current of that signal to the load, and so on.

[0004] The action of switching PWM pulses enables certain forms of high-speed solid-state switching devices. For current demands of hundreds of amperes, IGBTs are typically used. For currents up to tens of amperes, MOSFETs, which have lower losses and can handle higher frequencies, are typically used. When PWM-based amplifiers are used to drive brushless DC motors, the load requirements are usually large enough that the operating current is several amperes, and near-zero current regulation is not common. Summary of the Invention

[0005] This document typically describes a pulse width modulation (PWM) control system.

[0006] In a first aspect, a computer-implemented method for current control includes: receiving a first current output setpoint; identifying a first operating condition based on the first current output setpoint; providing a first pulse width modulation (PWM) signal having a first predetermined duty cycle based on the identified first operating condition, the first PWM signal being provided based on the first current output setpoint and for a predetermined time period; receiving a second current output setpoint; identifying a second operating condition different from the first operating condition based on the second current output setpoint; and providing a second PWM signal having a second predetermined duty cycle based on the identified second operating condition, the second PWM signal being provided based on the second current output setpoint and for a predetermined multiple of the predetermined time period.

[0007] In a second aspect, according to aspect 1, providing a first PWM signal includes: determining the start of a PWM cycle having a first duration based on a predetermined time period; providing an electrical signal; stopping the electrical signal based on determining that the electrical signal has been provided for a second duration based on a first predetermined duty cycle and that the second duration has passed; and determining the end of the PWM cycle based on determining that the first duration has passed.

[0008] In a third aspect, according to aspect 1 or 2, providing a second PWM signal includes: determining the start of a first PWM cycle having a first duration based on a predetermined time period; providing an electrical signal; stopping the electrical signal based on determining that a second duration based on a second predetermined duty cycle has elapsed; determining the end of the first PWM cycle based on determining that the first duration has elapsed; determining the start of a predetermined number of second PWM cycles having a first duration based on a predetermined time period, the predetermined number being based on a predetermined multiple; stopping the electrical signal during the second PWM cycle; and determining that the end of the predetermined number of second PWM cycles has occurred.

[0009] In the fourth aspect, according to aspect 3, the method further includes determining a predetermined multiple based on the second operating conditions.

[0010] In the fifth aspect, according to any one of aspects 1 to 4, providing the second PWM signal includes: determining the start of a PWM period having a second duration based on a predetermined time period and a predetermined multiple; providing an electrical signal; stopping the electrical signal based on determining that the second duration based on a second predetermined duty cycle has passed; and determining the end of the PWM period based on determining that the second duration has passed.

[0011] In a sixth aspect, according to any one of aspects 1 to 5, providing a second PWM signal includes: generating PWM pulses at a frequency based on a predetermined time period; transmitting electrical pulses based on the generated PWM pulses; and ignoring a predetermined number of PWM pulses based on a predetermined multiple.

[0012] In the seventh aspect, according to any one of aspects 1 to 6, identifying the first operating condition is based on: determining a target duty cycle based on a first current output setpoint; determining that the target duty cycle is equal to or longer than a predetermined threshold duty cycle; and providing the target duty cycle as a first predetermined duty cycle.

[0013] In the eighth aspect, according to any one of aspects 1 to 7, the second operating condition is identified as being based on: determining a target duty cycle based on a second current output setpoint; determining that the target duty cycle is shorter than a predetermined threshold duty cycle; and determining a second predetermined duty cycle based on the target duty cycle.

[0014] In the ninth aspect, according to any one of aspects 1 to 8, the second operating condition is identified based on at least one of the following: the minimum turn-on time of the circuit configured to transmit a PWM signal, and the minimum turn-off time of the circuit.

[0015] In a tenth aspect, the control system includes: an input configured to receive a current setpoint; a monitoring circuit configured to identify at least a first operating condition and a second operating condition based on the received current setpoint; a pulse generator configured to generate an electrical pulse width modulation (PWM) signal comprising a plurality of PWM pulses based on the received current setpoint; a pulse suppressor configured to modify a PWM signal by transmitting PWM pulses based on the first operating condition and by blocking selected PWM pulses in the PWM signal and transmitting unselected PWM pulses based on the second operating condition; and a transmitter configured to transmit the modified PWM signal to a load.

[0016] In the eleventh aspect, according to aspect 10, the first operating condition is identified based on a first current setpoint, and the second operating condition is identified based on a second current setpoint, and the pulse generator is further configured to generate a first PWM signal based on the first current setpoint and a second PWM signal based on the second current setpoint.

[0017] In the twelfth aspect, according to aspect 10 or 11, the first operating condition is identified based on a first current setpoint, and the second operating condition is identified based on a second current setpoint, and the monitoring circuit is further configured to identify the first operating condition based on the first current setpoint and the second operating condition based on the second current setpoint.

[0018] In the thirteenth aspect, according to any one of aspects 10 to 12, the monitoring circuit is configured to further identify one or both of a first operating condition and a second operating condition based on one or more operating inputs describing the load or the operation of the load, wherein the operation of the load is controlled based on a PWM signal.

[0019] In the fourteenth aspect, according to any one of aspects 10 to 13, the pulse suppressor is configured to modify the operation of the pulse generator so that the pulse generator suppresses the generation of a selected PWM pulse in the PWM signal.

[0020] In the fifteenth aspect, according to any one of aspects 10 to 14, the pulse suppressor is configured to modify the operation of the pulse generator so that the pulse generator modifies the frequency of the PWM signal.

[0021] In the sixteenth aspect, according to any one of aspects 10 to 15, the pulse suppressor is configured to block the selected PWM pulse generated by the pulse generator.

[0022] In the seventeenth aspect, according to any one of aspects 10 to 16, the selected PWM pulse is a predetermined number of sequential PWM pulses.

[0023] In the eighteenth aspect, according to aspect 17, a predetermined number of sequential PWM pulses are based on a second operating condition.

[0024] In a nineteenth aspect, a non-transient computer storage medium coded by a computer program includes instructions that, when executed by a data processing device, cause the data processing device to perform operations including: receiving a first current output setpoint; identifying a first operating condition based on the first current output setpoint; providing a first pulse width modulation (PWM) signal having a first predetermined duty cycle based on the identified first operating condition, the first PWM signal being provided based on the first current output setpoint and for a predetermined time period; receiving a second current output setpoint; identifying a second operating condition different from the first operating condition based on the second current output setpoint; and providing a second PWM signal having a second predetermined duty cycle based on the identified second operating condition, the second PWM signal being provided based on the second current output setpoint and for a predetermined multiple of the predetermined time period.

[0025] In the twentieth aspect, according to aspect 19, providing a first PWM signal includes: determining the start of a PWM cycle having a first duration based on a predetermined time period; providing an electrical signal; stopping the electrical signal based on determining that a second duration based on a first predetermined duty cycle has passed; and determining the end of the PWM cycle based on determining that the first duration has passed.

[0026] In the twenty-first aspect, according to aspect 19 or 20, providing the second PWM signal includes: determining the start of a first PWM cycle having a first duration based on a predetermined time period; providing an electrical signal; stopping the electrical signal based on determining that a second duration based on a second predetermined duty cycle has elapsed; determining the end of the first PWM cycle based on determining that the first duration has elapsed; determining the start of a predetermined number of second PWM cycles having a first duration based on a predetermined time period, the predetermined number being based on a predetermined multiple; stopping the electrical signal during the second PWM cycle; and determining that the end of the predetermined number of second PWM cycles has occurred.

[0027] In the twenty-second aspect, according to aspect 21, the operation further includes determining a predetermined multiple based on the second operating conditions.

[0028] In the twenty-third aspect, according to any one of aspects 19 to 22, providing a second PWM signal includes: determining the start of a PWM period having a second duration based on a predetermined time period and a predetermined multiple; providing an electrical signal; stopping the electrical signal based on determining that the second duration based on a second predetermined duty cycle has passed; and determining the end of the PWM period based on determining that the second duration has passed.

[0029] In the twenty-fourth aspect, according to any one of aspects 19 to 23, providing a second PWM signal includes: generating PWM pulses at a frequency based on a predetermined time period; transmitting electrical pulses based on the generated PWM pulses; and ignoring a predetermined number of PWM pulses based on a predetermined multiple.

[0030] In the twenty-fifth aspect, according to any one of aspects 19 to 24, identifying the first operating condition is based on: determining a target duty cycle based on a first current output setpoint; determining that the target duty cycle is equal to or longer than a predetermined threshold duty cycle; and providing the target duty cycle as a first predetermined duty cycle.

[0031] In the twenty-sixth aspect, according to any one of aspects 19 to 25, the second operating condition is identified as being based on: determining a target duty cycle based on a second current output setpoint; determining that the target duty cycle is shorter than a predetermined threshold duty cycle; and determining a second predetermined duty cycle based on the target duty cycle.

[0032] In the twenty-seventh aspect, according to any one of aspects 19 to 26, the second operating condition is identified based on at least one of the following: the minimum turn-on time of the circuit configured to transmit a PWM signal, and the minimum turn-off time of the circuit.

[0033] The system and techniques described herein can provide one or more of the following advantages. First, the system can provide PWM control at near-zero output. Second, the system can improve the stability of load control at near-zero output. Third, the system can reduce current ripple in the PWM output at near-zero output. Fourth, the system can reduce audible ringing and / or chatter in mechanical outputs driven by PWM signals at near-zero output.

[0034] Details of one or more embodiments are set forth in the accompanying drawings and description. Other features and advantages will become apparent from the specification, drawings, and claims. Attached Figure Description

[0035] Figure 1 This is a schematic diagram illustrating an example of a system for pulse width modulation (PWM) control according to some embodiments in this document.

[0036] Figure 2A This is a diagram of an example PWM waveform.

[0037] Figure 2B This is a magnified view of the example PWM cycle.

[0038] Figure 2C This is a diagram of a modified PWM waveform based on some of the embodiments in this document.

[0039] Figure 2D This is a diagram of a modified PWM waveform based on another example of some embodiments in this document.

[0040] Figure 3 This is a flowchart illustrating an example process for determining operating conditions that can provide a PWM or modified PWM signal.

[0041] Figure 4 This is a schematic diagram illustrating an example of another system for pulse width modulation (PWM) control, based on some embodiments described in this document.

[0042] Figure 5 This is a schematic diagram illustrating an example of another system used for pulse width modulation.

[0043] Figure 6 This is a flowchart of an example process for PWM control based on some embodiments of this document.

[0044] Figure 7 This is a flowchart of an example process for providing a PWM signal according to some embodiments in this document.

[0045] Figure 8 This is a flowchart of another example process for modifying a PWM signal according to some embodiments in this document.

[0046] Figure 9 This is a flowchart of another example process for modifying a PWM signal according to some embodiments in this document.

[0047] Figure 10 This is a schematic diagram of an example of a general-purpose computer system. Detailed Implementation

[0048] This document describes systems and techniques for pulse width modulation (PWM) or pulse duration modulation (PDM) control systems. Typically, the techniques described in this document overcome problems that arise as a byproduct of providing very short PWM pulses (e.g., near-zero output) to solid-state switches and / or amplification stages. These problems are typically overcome by identifying a condition that the PWM duty cycle width has fallen below a predetermined minimum threshold and responding by skipping or blocking the transmission of a predetermined number of pulses before transmitting the next PWM pulse (e.g., sending one PWM pulse every "X" PWM cycles when the PWM pulse width is determined to be less than "Y" milliseconds).

[0049] In some embodiments, these techniques can be used to control the amount of current supplied to a torque motor used to drive an electro-hydraulic servo valve (EHSV). These EHSVs are typically two-stage hydraulic control valves that can be used to drive linear or rotary hydraulic actuators on the control surfaces of mobile aircraft. However, in some other embodiments, these control techniques can also be used with other types of electric motors or solenoids.

[0050] This document typically describes systems and techniques for overcoming the limitations of PWM switching in MOSFETs and other solid-state devices at extremely low currents. Many existing applications use linear amplifiers that employ discrete analog electronics to drive current in EHSV torque motors. Even though linear amplifiers are less efficient than PWM-based amplifiers, the current requirements of EHSVs with low flow ratings are small enough that losses in the amplifier may not be a concern. However, for larger EHSVs or in directly driven EHSVs (where the torque motor directly drives the slide valve), the current requirements can be much greater, potentially prompting the use of PWM-based amplifiers. From an electronic design perspective, PWM-based amplifiers allow proportional-integral (PI) control to be offloaded to software and can leverage the characteristics of a microcontroller to control the output waveform. This can result in fewer parts and better integration, leading to reduced costs and increased reliability.

[0051] Solid-state devices vary in switching speed, and each configuration of a device can have a minimum turn-on time and a minimum turn-off time. The minimum turn-on time corresponds to the pulse width required to turn on the MOSFET from the off state, while the minimum turn-off time corresponds to the minimum time it takes for the MOSFET to completely turn off once the pulse width reaches zero (e.g., the voltage is removed from its gate). This turn-off time ultimately corresponds to the minimum duty ratio that can be used to command the MOSFET. These turn-on and turn-off times are relatively short (e.g., milliseconds), and while higher-quality devices can exhibit even shorter times, all known solid-state switches still exhibit this behavior to some extent.

[0052] In an ideal system, the PWM output is directly and smoothly proportional to the duty cycle (e.g., 100% duty cycle gives 100% current, 50% duty cycle gives 50% current, and 1% duty cycle gives 1% current). However, due to the switching limitations of real-world solid-state switches, practical PWM outputs may lose linearity and / or stability near the zero-current point (e.g., under conditions using sufficiently short duty cycles). When the duty cycle of the pulse used to drive the gate of a MOSFET becomes shorter than the MOSFET's minimum off-time, the MOSFET may produce an output pulse with (e.g., a relatively long) minimum off-time instead of an output pulse with (e.g., a relatively short) command PWM duty cycle. In some examples, this behavior may resemble plateauing or "bottoming out" of the output current when a series of duty cycles transition from longer than the minimum off-time (e.g., which could cause a proportional decrease in output current) to equal or shorter than the minimum off-time (e.g., at least a portion of which could produce the same output current based on the minimum off-time rather than the duty cycle).

[0053] When PWM-based amplifiers are used to drive brushless DC motors, the load requirements are typically large enough that the operating current is several amperes, and near-zero current regulation is uncommon. In such applications, the PWM duty cycle (e.g., the portion of the PWM cycle during which the signal is "on") is typically longer than the minimum off-time of the amplifier's switch. However, when PWM-based amplifiers are used to control EHSV servos, the implementation may require near-zero current regulation. In some applications, the PWM duty cycle may become shorter than the minimum off-time of the amplifier's switch.

[0054] Figure 1 This is a schematic diagram illustrating an example of a system 100 for pulse width modulation (PWM) control. System 100 includes a PWM controller 110 configured to receive a setpoint value 101 (e.g., a target output current, a percentage of the output current) and provide a corresponding output signal to an electrical load 102 (e.g., an EHSV, a motor).

[0055] PWM controller 110 includes switch 112. Switch 112 is a solid-state switching device (such as a MOSFET-backed H-bridge or IGBT) configured to act as a PWM signal transmitter to send a PWM signal to electrical load 102. Switch 112 has inherent minimum on-time and minimum off-time (e.g., based on the physics of its underlying solid-state structure). For example, once the control signal is turned off, switch 112 can remain on for at least a predetermined amount of time, even if the control signal is removed before that time has elapsed. In another example, once the controller signal is turned off, switch 112 can remain off unless an on signal is provided for at least a predetermined amount of time. This on-time is typically much smaller than the off-time (e.g., 0.025 microseconds compared to 2 microseconds).

[0056] In the example, the selected MOSFET may have finite turn-on and turn-off times, such as T on = 22 nanoseconds, and T off = 2 microseconds. For a PWM frequency of 10kHz, this means the "minimum" duty cycle command from the gate drive circuit is 0.022% to turn on the MOSFET. Due to the limited T... off Any duty cycle greater than 0.022% and less than 2% will result in an effective duty cycle of 2%. With this nonlinearity present, the proportional-integral (PI) controller can become unstable for current command values ​​in the range of -10mA to +10mA. Essentially, the PI controller doesn't "know" the dead zone and offset in the duty cycle command, so its integrator keeps accumulating until the PI output changes sign. This causes the current to reverse in an attempt to reduce the error. The cycle itself then repeats. In an example where the current loop is running at 10kHz, these oscillations can have frequencies ranging from 1kHz to 2kHz and can produce audible noise and vibration in a torque motor. The problem becomes more severe as the PWM voltage increases because the duty cycle decreases proportionally; for example, for equivalent current output, the duty cycle of a 28VDC supply is typically smaller than that of a 12VDC supply.

[0057] These and other performance parameters of switch 112 may be known (e.g., based on manufacturer specifications) or determined (e.g., measured) and are used as a set of predetermined switch parameters 103.

[0058] Switch 112 is configured to amplify the PWM drive signal by rapidly switching the current from power source 106 (e.g., current received at transistor source input) to electrical load 102 (e.g., electrically connected to transistor drain output) based on a PWM control signal (e.g., received at transistor gate input). The PWM drive signal can be a normal PWM signal 131 generated by normal PWM signal (e.g., pulse) generator module 130, or a modified PWM signal 141 generated by modified PWM signal (e.g., pulse) generator 140. Typically, a normal PWM signal is a PWM signal having a predetermined period or frequency where non-zero values ​​are represented by an electrical pulse during each period, while a modified PWM signal is a PWM signal having a predetermined period or frequency but not transmitting an electrical pulse for each period for some non-zero values. Figure 2A The description further discusses examples of normal PWM signals, and... Figure 2B and Figure 2C The description further discusses examples of modified PWM signals.

[0059] The determination of whether to present a normal PWM signal or a modified PWM signal to switch 112 is performed by monitoring module 120. In some implementations, monitoring module 120 may be a software algorithm executed by a processor, or it may be a function executed by dedicated electronic circuitry. Monitoring module 120 includes operating condition identification module 122 and threshold module 124.

[0060] Operating condition identification module 122 is configured to determine the duty cycle of the PWM signal to be generated (e.g., for amplification by switch 112) based on a setpoint value 101 received at input port 111. PWM controller 110 is configured to provide a high power level range (e.g., 0-10A, 0-100A) from switch 112 to electrical load 102 based on a low power (e.g., 0-5V, 0-10V, -10mA to +10mA) or digital signal provided to PWM controller 110 to represent setpoint 101.

[0061] The operating condition identification module 122 is also configured to receive feedback or other information about the electrical load 102 and use that information to determine the operating conditions. For example, an electric actuator without a mechanical load may respond differently to a selected PWM duty cycle than when the electric actuator load has a high inertia load, and the operating condition identification module 122 may determine the operating conditions or PWM duty cycle at least partially based on these conditions. In another example, two different mechanical loads may behave differently to a modified PWM signal (e.g., one load may audibly resonate or mechanically jitter in response to the same modified PWM signal, while the other load may not), and the operating condition identification module 122 may determine the operating conditions or PWM duty cycle at least partially based on these conditions.

[0062] In some implementations, the operating condition identification module 122 can be configured to convert the setpoint value 101 into a PWM signal with a predetermined period and a duty cycle based on the setpoint value 101. For example, the setpoint value 101 may represent "10%", and the operating condition identification module 122 can respond by determining that the corresponding duty cycle is 10% of the PWM period and by determining the duration of the PWM pulse corresponding to the 10% duty cycle. In such an example, the operating condition identification module 122 may determine that for a PWM frequency of 10 kHz, the PWM period or frame time will be 0.0001 seconds long, and determine that a 10% duty cycle will result in a PWM pulse with a duration of 0.00001 seconds over an interval of 0.0001 seconds. Such pulse control is achieved by switch 112 switching the amount of power from power source 106 to electrical load 102 (e.g., in this example, 10% of the power available from power source 106). Similarly, a 90% setpoint value can enable the operating condition identification module 122 to determine that a 90% duty cycle is appropriate, and can determine that a 90% duty cycle will result in a PWM signal that includes pulses with different durations (e.g., 0.0009 seconds for a PWM frequency of 1 kHz).

[0063] In some embodiments, the operating condition identification module 122 may be configured to measure the pulse duration of an existing PWM signal. For example, the operating condition identification module 122 may be configured downstream of the PWM signal generator (e.g., rather than upstream of the PWM signal generators 130 and 140 as shown in the example). In some embodiments, arranging the operating condition identification module 122 upstream of PWM signal generation may be useful for new controller designs, while arranging the operating condition identification module 122 downstream of PWM signal generation may be useful for enhancing or modifying existing controller designs.

[0064] Threshold module 124 is configured to compare the duration of a determined PWM pulse with predetermined switching parameters 103. Predetermined switching parameters 103 provide information describing the characteristics of switch 112, including a minimum on-time of switch 112. In some implementations, predetermined switching parameters 103 may be provided directly; for example, predetermined switching parameters 103 may include explicit values ​​describing the minimum on-time of switch 112. In some implementations, predetermined switching parameters 103 may be provided indirectly; for example, predetermined switching parameters 103 may include values ​​describing structure, type, brand, and model, or other information identifying switch 112, and the minimum on-time of switch 112 may be determined (e.g., looked up, calculated) based on this information.

[0065] The threshold module 124 compares the duration of the determined PWM pulse with the minimum off time of the switch 112 to determine whether the target PWM duty cycle results in a PWM pulse that is equal to or longer than the minimum off time of the switch 112, or whether the target PWM duty cycle results in a PWM pulse that is shorter than the minimum on time of the switch 112 (e.g., a PWM duty cycle that is too short for the switch 112 to be accurately followed).

[0066] If the threshold module determines that the PWM pulse duration is equal to or longer than the minimum off time of switch 112 (e.g., switch 112 can accurately follow the pulse), then the normal PWM signal generator 130 is engaged to generate a normal PWM signal 131 and provide the normal PWM signal 131 to the switch. However, if the threshold module determines that the PWM pulse duration is shorter than the minimum off time of switch 112 (e.g., switch 112 cannot accurately follow the pulse), then the modified PWM signal generator 140 is engaged to generate a modified PWM signal 141 and provide the modified PWM signal 141 to the switch.

[0067] Figure 2A Figure 200a shows an example PWM waveform 201a. In some implementations, PWM waveform 201a can be... Figure 1 Example of a normal PWM signal 131.

[0068] The PWM waveform 201a is a series of PWM cycles 205a. Each of the PWM cycles 205a has a predetermined PWM cycle time period 207a. At the beginning of the PWM cycle 205a, the PWM waveform 201a goes high (e.g., the signal power is turned on), and when the predetermined PWM cycle time period 207a has elapsed, the PWM waveform 201a goes low (e.g., the signal power is turned off) and remains low until the PWM cycle time period 207a has elapsed, then the process repeats. For example, a PWM signal with a frequency of 100Hz will have a cycle time period of 10ms (e.g., 1 / 100th of a second equals 10ms). Typically, the PWM signal is transmitted at a substantially fixed predetermined frequency.

[0069] For non-zero PWM values, each of the PWM cycles 205 includes a PWM pulse 210. Each of the PWM pulses 210 has a duty cycle, which is a fraction or percentage of the PWM cycle time period 207. The duty cycle determines the duration or time period of the PWM pulse, and in the example shown, the PWM pulse duration is represented as 215. For example, for a PWM signal with a 50% duty cycle, the length of the PWM pulse duration 215 will be 50% of the time length of the PWM cycle time period 207. In another example, for a PWM signal with a frequency of 100Hz and a 50% duty cycle, the PWM pulse will be 5ms long (e.g., 50% of a 10ms time period equals 5ms). To simplify the illustration for explanation, PWM waveform 201 represents a single value emitted within the duration shown for PWM waveform 201.

[0070] Figure 2B This is a diagram of an example PWM period 220. In some embodiments, PWM period 220 may be an enlarged view of one of the PWM periods 205. The PWM period has a PWM period time interval 222 and a PWM pulse 224. The PWM pulse has a PWM pulse duration 226. The threshold time interval 228 represents the switching amplifier (e.g., Figure 1 Example minimum on time (example switch).

[0071] In the example shown, the selected duty cycle of PWM period 220 results in a PWM pulse duration 226 shorter than the threshold time period 228. In some examples, unless further steps are taken, the pulse provided by the switching amplifier may have a duration close to the threshold time period 228, instead of the PWM pulse duration 226. As a result, without additional remedies, the actual output of the switching amplifier may become disproportionate to the command output. For example, a high current based on a high PWM duty cycle may decrease proportionally as the PWM duty cycle decreases until the PWM duty cycle duration is substantially equal to the threshold time period 228. As the PWM duty cycle continues to decrease, the amplified current output may remain at the level caused by the minimum off-time of the switching amplifier (as represented by the threshold time period 228). Under such conditions, and without additional remedies, the output of the switching amplifier will be higher than the command output level and will become increasingly erroneous as the command output level approaches zero.

[0072] The PWM pulse duration 226 is determined (e.g., by...). Figure 1 The example monitoring circuit provides a modified PWM signal to a switching amplifier (e.g., switch 112) when the time period is less than (or equal to or less than) a threshold 228, so as to controllably adjust the output of the switching amplifier.

[0073] Figure 2C Figure 240 shows an example of a modified PWM waveform 241. In some implementations, the modified PWM waveform 241 may be... Figure 1 Example of a modified PWM signal 141. Typically, the modified PWM waveform 241 can be used to controllably adjust a switching amplifier (e.g., by driving the PWM control signal to a level with a PWM duty cycle shorter than the minimum off-time of the switching amplifier). Figure 1 The output of example switch 112). Typically, this is achieved by transmitting a PWM pulse during the first PWM cycle, and then suppressing, blocking, skipping, or otherwise preventing the transmission of the PWM pulse for a predetermined number of subsequent PWM cycles before transmitting another PWM pulse.

[0074] In the example shown, the PWM waveform 241 includes a PWM period 245 having a PWM period duration 207 and a PWM pulse duration 242 defining the PWM pulse 243. At the start of the PWM period 245, the PWM waveform 241 goes high (e.g., signal power is turned on), and when the predetermined PWM period duration 207 has elapsed, the PWM waveform 241 goes low (e.g., signal power is turned off) and remains low until the PWM period duration 207 has elapsed. However, with... Figure 2AUnlike the normal PWM waveform 201, the modified PWM waveform 241 does not immediately repeat itself. Instead, the PWM waveform 241 remains low during skipped PWM cycles 246 and 247, each of which has a PWM cycle duration 207, before going high again for another PWM pulse duration equal to the PWM pulse duration 242.

[0075] In the example shown, PWM cycle 245 is followed by two skipped PWM cycles 246 and 247. In some implementations, an appropriate number of PWM cycles (e.g., 2, 3, 5, 10, 20, or more skipped cycles) may be skipped before another PWM pulse 243 is provided. In some implementations, the number of skipped PWM cycles may be determined dynamically, for example, based on the PWM duty cycle or based on a comparison of the PWM pulse duration 242 with the minimum off time.

[0076] For example, for situations where the PWM pulse duration is almost equal to the switching duration (e.g., Figure 1 For example, for a PWM duty cycle with a minimum off time of switch 112), zero skipped PWM cycles can be used, which will result in an amplified PWM signal with approximately the minimum off time at the switch output. In another example, for a PWM duty cycle that results in a PWM pulse duration of approximately half the minimum off time of the switch, one skipped PWM cycle can be used between each pulse PWM cycle, which will result in an amplified PWM signal with half a pulse per second at the switch output and will result in an amplified output of approximately half the output with zero skipped cycles. In yet another example, for a PWM duty cycle that results in a PWM pulse duration of approximately one-third the minimum off time of the switch, two skipped PWM cycles can be used, which will result in an amplified PWM signal with approximately one-third a pulse per second at the switch output and will result in an amplified output of approximately one-third the output with zero skipped cycles.

[0077] In another example, the PWM driver 110 can be equipped to account for variations in the DC resistance of the motor coils in the load 102, and / or for variations in the current command value (e.g., as the current command value decreases, the number of frame skips can increase). In a specific example, the voltage supply V... s The nominal DC resistance can be known and is fixed. For the maximum current lmax = V s / (DC resistance), assuming a duty cycle of 100%, then the voltage across the winding of the torque motor is V. s For a given current command l cmd The required duty cycle is estimated to be DR = lcmd / l max In an example where the DC resistance varies with temperature or from motor to motor, these variables can be measured or estimated first. The calculation of the number of sample time periods to skip n cycles can be as follows:

[0078] 1. MOSFET turn-on time T on _ min = 22 nanoseconds corresponds to a duty cycle DR on_min = 0.00022.

[0079] 2. MOSFET turn-off time T off_min = 22 microseconds corresponds to a duty cycle DR off_min = 0.02.

[0080] 3. PWM time period T pwm = 100 microseconds and is fixed.

[0081] 4. For a given duty cycle command for DR (= T on / T pwm ), where 0.00022 < DR ≤ 0.02, when DR is commanded to be zero, we must "skip" n - 1 frames.

[0082] To determine n, note that:

[0083] a. (T on + T off_min ) / (n * T pwm ) can be equal to T on / T pwm .

[0084] b. Therefore n = (T[[ID=五十一]] on + T off_min ) / T on

[0085] c. Divide the numerator and denominator by T[[ID=五十九]] pwm , we get:

[0086] n = (DR + DR off_min [[ID=六十五]] / DR[[ID=六十六]]

[0087] d. The result can be rounded to the nearest integer so that it can work with a frame counter.

[0088] Figure 2D is FIG. 260 of a modified PWM waveform 261. In some implementations, the modified PWM waveform 261 can be Figure 1 an example of a modified PWM signal 141. In some implementations, the modified PWM waveform 261 can be Figure 2CThe example is a modified PWM waveform 241, but generated using a different technique. Typically, while the modified PWM waveform 241 is generated by providing a PWM cycle with pulses, followed by one or more cycles in which the pulses are held low, blocked, or otherwise not provided, the modified waveform 261 is generated by dynamically changing the PWM cycle frequency.

[0089] As discussed earlier, when the PWM duty cycle is shortened to approximately equal to the switching frequency (e.g., Figure 1 When the minimum off time of the example switch 112) is equal to the PWM duration, it is impossible to make the amplified pulse of the switch output shorter. In the example shown, instead of implementing skipped PWM cycles to further reduce the switch output (e.g., as done in example waveform 241), the PWM frequency of PWM waveform 261 is reduced by a predetermined amount.

[0090] The PWM waveform 261 consists of a set of repeating PWM cycles 265. Each of the PWM cycles 265 has a PWM cycle time period 267, and for non-zero values, each PWM cycle 265 includes a PWM pulse 262 with a PWM pulse duration 272.

[0091] In the example shown, the PWM cycle time is approximately 267. Figure 2A and Figure 2C The example cycle time period 2073 is longer, while the PWM pulse duration is not extended (e.g., the PWM duty cycle is reduced to one-third to offset the extended PWM cycle time period 267). For example, if the PWM cycle time period 207 is 100ms and the duty cycle is 10%, then the PWM pulse duration 242 will be 10ms. Continuing this example, if the PWM cycle time period 267 is extended to 300ms, the PWM pulse duration 242 can be maintained at approximately 10ms. By dynamically reducing the PWM frequency, the PWM waveform 261 can be used to provide a switched, amplified output representing a PWM duty cycle shorter than the minimum off time of the switch, which would otherwise be allowed.

[0092] In the example shown, the PWM frequency has been reduced to approximately one-third, but in other examples, any appropriate reduction can be used. For example, by setting the PWM cycle time period 267 to twice the length of the example PWM cycle time period 207, the PWM frequency (and the resulting amplified output) can be reduced by approximately half (e.g., compared to the example PWM waveform 201). In other examples, any appropriate length of PWM cycle time period can be used, such as 1.25x, 2x, 2.5x, 3x, 5x, or 10x the duration of the PWM cycle time period of a normal (e.g., unmodified) PWM signal.

[0093] exist Figures 2A-2D In this document, PWM waveforms are shown and described as edge-aligned waveforms (e.g., where the leading edge of the pulse is aligned with the start of the PWM period). However, PWM signals (including those described in this document) are not limited to edge-aligned signals. For example, the systems and techniques described in this document can be adapted for use with center-aligned PWM waveforms (e.g., where the pulse appears symmetrically aligned with the center of the PWM period) or with any other suitable edges or offsets for timing and / or alignment of the PWM pulse and PWM period.

[0094] Figure 3 This is a flowchart illustrating an example process 300 for determining operating conditions that can provide a PWM or modified PWM signal. In some implementations, process 300 may be... Figure 1 Example PWM controller 110 is executed.

[0095] At point 310, the PWM duty cycle is determined based on the set of feedback information 330 and the setpoint 320. For example, it can be based on... Figure 1 The target output of the example switch 112 and the PWM duty cycle are selected based on information about the example electrical load 102 directly or indirectly driven by the output of switch 112.

[0096] At 340, the PWM pulse width is determined based on the established PWM duty cycle. The PWM signal repeats at predetermined or measurable time intervals, and the PWM duty cycle represents a fraction of that interval. The resulting portion is the PWM pulse duration. For example, a 10Hz PWM signal with a 50% duty cycle will have pulses 0.05s long and repeat once every 0.1s.

[0097] At 350, a determination is made based on the determined PWM pulse duration and a predetermined threshold 360. Threshold 360 is based on the minimum off time of the switch (e.g., solid-state device, transistor, IGBT, MOSFET) that will amplify the PWM signal. If the PWM pulse duration is approximately equal to or longer than the time period determined according to threshold 360 (e.g., the PWM pulse has a length that will not be affected by the minimum off time of the switch), then at 370, an unmodified (e.g., normal) PWM signal is provided to the switch (e.g., normal PWM signal generator 130 is used to provide normal PWM signal 131 to switch 112). If the PWM pulse duration is shorter than the time period determined according to threshold 360, then at 380, a modified PWM signal is provided to the switch (e.g., modified PWM signal generator 140 is used to provide modified PWM signal 141 to switch 112).

[0098] Figure 4 This is a schematic diagram illustrating an example of another system 400 for pulse width modulation (PWM) control. In some embodiments, system 400 may be... Figure 1 Modifications to the example system 100 or more specific configurations.

[0099] System 400 includes a PWM controller 410. In the illustrated example, a PWM signal generator 430 is configured to generate a normal PWM signal (e.g., a pulse per cycle) or a modified PWM signal (e.g., one pulse per selected number of cycles, or a reduced frequency signal) based on a setpoint value 101 and operating conditions determined by a monitoring module 120 based on the setpoint value 101. The selected type of PWM signal is provided to a switch 112 to control the power flow from a power source 106 to an electrical load 102.

[0100] Figure 5 This is a schematic diagram illustrating an example of another system 500 for pulse width modulation control. In some embodiments, system 500 may be... Figure 1 Modifications to the example system 100 or more specific configurations.

[0101] System 500 includes a PWM controller 510. In the illustrated example, a normal PWM signal generator 130 is configured to always generate an unmodified PWM signal (e.g., a normal PWM signal 131) based on a setpoint value 101. A monitoring module 120 is configured to determine operating conditions based on the setpoint. For example, the monitoring module 120 may be configured to determine whether the setpoint results in a PWM duty cycle that will have a PWM pulse duration equal to or longer than the minimum off time of switch 112, or a PWM duty cycle that will result in a PWM pulse duration shorter than the minimum off time of switch 112.

[0102] The pulse suppressor 540 is configured to selectively modify the unmodified PWM signal provided by the PWM signal generator 130, or allow the unmodified PWM signal to remain unmodified, based on operating conditions determined by the monitoring module 120. Under operating conditions where the frequency and duty cycle of the unmodified PWM signal are determined (e.g., by the monitoring module 120) to result in a PWM pulse equal to or longer than the minimum off time of switch 112, the pulse suppressor module 540 can remain inactive and allow the unmodified PWM signal (e.g., the normal PWM signal 131) to be transmitted to switch 112.

[0103] Under operating conditions where the frequency and duty cycle of the unmodified PWM signal are determined (e.g., by monitoring module 120) to result in PWM pulses shorter than the minimum off time of switch 112, pulse suppressor module 540 can be activated to modify the unmodified PWM signal and deliver the resulting modified PWM signal (e.g., modified PWM signal 141) to switch 112. For example, pulse suppressor module 540 can be configured to turn on and off synchronously with the duration of the PWM cycle to allow the selected PWM cycle to be delivered to switch 112 and suppress or otherwise prevent other cycles from being delivered.

[0104] In operation, the pulse suppressor module 540 can be configured to suppress or otherwise block the transmission of a selected number of subsequent PWM cycles for each PWM cycle it is configured to transmit. For example, the pulse suppressor module 540 can be configured to allow a PWM cycle and its PWM pulse to be transmitted to switch 112, and then block the next four PWM cycles before transmitting another PWM cycle and its PWM pulse, the transmission of which occurs before the suppression of another four skipped cycles. In other examples, the pulse suppressor module 540 can be configured to skip zero, one, two, three, four, ten, twenty, or any other suitable number of PWM cycles.

[0105] In the illustrated example, the pulse suppressor module 540 is configured to controllably propagate and block a low-level PWM pulse before it arrives at switch 112 for amplification. In some embodiments, the pulse suppressor module 540 may be configured to controllably propagate and block a high-level PWM signal. For example, the pulse suppressor module 540 may be arranged to controllably propagate and block the output of switch 112.

[0106] In the illustrated example, the pulse suppressor module 540 is included as part of the PWM controller 510. In some embodiments, the pulse suppressor module 540 and / or the monitoring module 120 may be external to the PWM controller 510. For example, an existing (e.g., normal) PWM signal generator may be modified or otherwise supplemented with the monitoring module 120 to detect operating conditions based on the setpoint value 101, and the pulse suppressor module 540 may be arranged between the switch 112 and the electrical load 102. In such an arrangement, the pulse suppressor module 540 may be configured to controllably propagate or block the amplified PWM signal as it travels from the PWM controller 510 to the electrical load 102.

[0107] Figure 6 This is a flowchart of an example process 600 for PWM control according to some embodiments in this document. In some implementations, process 600 may be... Figure 1 , Figure 4 and Figure 5 Example systems 100, 400, and / or 500 are executed.

[0108] At 610, the first current output setpoint is received. For example, example setpoint value 101 is received by PWM controller 110.

[0109] At 620, a determination is made. If no first operating condition is identified based on the first current output setpoint, the process continues at 640. If the first operating condition is identified based on the first current output setpoint, the process continues at 630.

[0110] In some implementations, identifying the first operating condition may be based on the following operations: determining a target duty cycle based on a first current output setpoint, determining that the target duty cycle is equal to or longer than a predetermined threshold duty cycle, and providing the target duty cycle as a first predetermined duty cycle. For example, monitoring module 120 may determine, based on switch parameter 103, whether setpoint value 101 will result in a PWM signal having a PWM duty cycle that results in a PWM pulse approximately equal to or longer than the minimum off time of switch 112.

[0111] At 630, a first pulse width modulation (PWM) signal with a first predetermined duty cycle is provided based on the identified first operating condition. The first PWM signal is based on a first current output setpoint and is provided for a predetermined time period. For example, when the PWM pulse duration is approximately equal to or longer than the minimum off time of switch 112, normal PWM signal generator 130 can be used to generate normal PWM signal 131.

[0112] In some implementations, providing the first PWM signal may include: determining the start of a PWM cycle having a first duration based on a predetermined time period; providing an electrical signal; stopping the electrical signal based on determining that the electrical signal has been provided for a second duration based on a first predetermined duty cycle and that the second duration has elapsed; and determining the end of the PWM cycle based on determining that the first duration has elapsed. For example, example PWM waveform 201 includes a repeating set of PWM cycles 205 having a PWM cycle time period 207. The start of cycle 205 can be determined, and an output signal can be turned on. The output signal remains on until the end of the PWM pulse duration 215 and is turned off for the remainder of the PWM cycle time period 207.

[0113] At position 640, the second current output setpoint is received. In some implementations, the second output setpoint can be the first output setpoint.

[0114] At 650, another determination is made. If no second operating condition different from the first operating condition is identified based on the second current output setpoint, the process continues at 610. If a second operating condition is identified based on the second current output setpoint, the process continues at 660.

[0115] In some implementations, identifying the second operating condition may be based on: determining a target duty cycle based on a second current output setpoint, determining that the target duty cycle is shorter than a predetermined threshold duty cycle, and determining a second predetermined duty cycle based on the target duty cycle. In some implementations, identifying the second operating condition may be based on at least one of the following: the minimum off-time of a circuit configured to transmit a PWM signal, and the minimum on-time of that circuit. For example, monitoring module 120 may determine, based on switch parameter 103, whether setpoint value 101 will result in a PWM signal with a PWM duty cycle that results in a PWM pulse shorter than the minimum off-time of switch 112.

[0116] At 660, a second PWM signal is provided based on the identified second operating condition. The second PWM signal has a second predetermined duty cycle, is based on a second current output setpoint, and is provided at a predetermined multiple of a predetermined time period. For example, when the PWM pulse duration is shorter than the minimum off time of switch 112, the modified PWM signal generator 140 can be used to generate a modified PWM signal 141.

[0117] In some implementations, providing a second PWM signal may include: generating PWM pulses at a frequency based on a predetermined time period, transmitting electrical pulses based on the generated PWM pulses, and ignoring a predetermined number of PWM pulses based on a predetermined multiple. For example, one of the example PWM pulses 243 may be generated during each PWM cycle 245, and no PWM pulses may be generated during PWM cycles 246 and 247. In some implementations, PWM pulses can be ignored by configuring the PWM signal generator not to generate pulses to be ignored or skipped. In some implementations, the PWM generator may generate pulses for each PWM cycle, but a filter (e.g., pulse suppressor module 540) may block or otherwise effectively prevent selected ignored or skipped pulses from reaching the amplification stage (e.g., switch 112).

[0118] In some implementations, providing a second PWM signal may include: determining the start of a PWM cycle having a second duration based on a predetermined time period and a predetermined multiple; providing an electrical signal; stopping the electrical signal based on determining that the electrical signal has been provided for a second duration based on a second predetermined duty cycle and that the second duration has elapsed; and determining the end of the PWM cycle based on determining that the second duration has elapsed. For example, it may be possible to provide... Figure 2D The modified PWM waveform 261, wherein the duration of the example PWM period time period 265 is a predetermined multiple (e.g., three times) of the example PWM period time period 207.

[0119] Figure 7 This is a flowchart of an example process 700 for providing a PWM signal according to some embodiments of this document. In some implementations, process 700 may be... Figure 1 , Figure 4 and Figure 5 Example systems 100, 400, and / or 500 execute, for example, to produce Figure 2C Example of a normal PWM waveform 241. In some implementations, process 700 can be used as... Figure 6 At least a portion of step 630 of example process 600 is performed.

[0120] At point 710, the start of a first PWM cycle having a first duration based on a predetermined time period is determined. For example, the start of a PWM cycle 245 having a PWM cycle time period 207 can be determined or detected.

[0121] At 720, an electrical signal is provided. For example, the output of the modified PWM signal generator 140 can be turned on or set high to start the PWM pulse 210.

[0122] At 730, a determination is made based on whether the second duration has elapsed. For example, the determination can be based on whether the PWM pulse duration 207 has elapsed. If the second duration has not yet elapsed, process 700 continues at 720. If the second duration has elapsed, process 700 continues at 740.

[0123] At 740, based on the determination that the second duration has elapsed, the electrical signal stops. For example, the output of the modified PWM signal generator 130 can be turned off or set low when the PWM pulse duration 215 has elapsed to end the PWM pulse 210.

[0124] At 750, another determination is made based on whether the first duration has elapsed. For example, if the PWM cycle time period 207 has not yet elapsed, the PWM signal remains low, and the process continues at 740. If the PWM cycle time period 207 has elapsed, the process 700 continues at 710.

[0125] Figure 8 This is a flowchart of an example process 800 for modifying a PWM signal. In some implementations, process 800 can be... Figure 1 , Figure 4 and Figure 5 Example systems 100, 400, and / or 500 execute, for example, to produce Figure 2C Example modified PWM waveform 241. In some implementations, process 700 can be used as... Figure 6 At least a portion of step 660 of example process 600 is performed.

[0126] At point 810, the start of a first PWM cycle with a first duration based on a predetermined time period is determined. For example, it can be identified as follows: Figure 2A Example PWM period 205 or Figure 2C The example PWM cycle is 245 at the beginning.

[0127] At 820, a determination is made. If the PWM signal will be generated in an unmodified (e.g., normal) mode, process 800 continues at 830. If the PWM signal will be generated in a modified mode, process 800 continues at 840.

[0128] An electrical signal is provided at 830. For example, it can be started. Figures 2A-2D Examples of PWM pulses 210, 224, and 243 (e.g., signal power can be turned on).

[0129] At 850, a decision is made. If the duty cycle of the PWM signal has not yet expired, the process continues at 830. For example, if the durations of example PWM pulses 215, 226, and 242 have not yet expired, their corresponding PWM pulses 210, 224, and 243 remain on. If the duty cycle of the PWM signal has expired, the process continues at 860.

[0130] At 860, the electrical signal is stopped based on the determination that a second duration has elapsed. The second duration is based on a first predetermined duty cycle or a second predetermined duty cycle (e.g., any duty cycle recently determined according to setpoint value 101). For example, example PWM pulses 210, 224, and 243 can be turned off when the corresponding PWM pulse durations 215, 226, and 242 of example PWM pulses 210, 224, and 243 have expired.

[0131] At 870, another determination is made based on the PWM cycle duration. If the PWM cycle duration has not yet expired, process 800 continues at 860, and the PWM signal level remains low. If the PWM cycle duration has expired, process 800 continues at 810. For example, example PWM waveforms 201 and 241 can remain low or off for the remainder of their respective PWM cycle time periods 207.

[0132] If process 800 operates in the modified mode, the determination at 870 may include determining the end of the first PWM cycle based on the determination that a first duration has elapsed. For example, if the modified PWM waveform is to include four skipped cycles for each pulse (e.g., non-skipped) cycle, the end of the pulse cycle may be identified as the end of the first PWM cycle.

[0133] When it is determined at 820 that process 800 is operating in the modified PWM mode, the process continues at 840. At 840, another determination is made regarding the number of PWM cycles to be skipped, ignored, blocked, or otherwise not provided with corresponding PWM pulses. For example, by determining that a PWM pulse was sent in the previous cycle and resetting the skipped cycle counter, a predetermined number of second PWM cycles with a first duration based on a predetermined time period, the predetermined number being based on a predetermined multiple, is determined to begin. If no predetermined number of cycles have occurred, the process continues at 860, where the PWM signal output is set or held low and remains low until the cycle is complete. The process of holding the PWM output low continues until it is determined at step 840 that a predetermined number of skipped cycles have been performed. If a predetermined number of skipped cycles have occurred, the process continues at 830, where the next PWM pulse begins.

[0134] In some implementations, process 800 may also include determining a predetermined multiple based on a second operating condition. For example, setpoint value 101 may be analyzed to determine whether zero, one, two, three, four, seven, thirteen, or any other appropriate number of periods without corresponding PWM pulses are provided after the provided PWM pulses.

[0135] Figure 9 This is a flowchart of an example process 900 for modifying a PWM signal. In some implementations, process 900 can be... Figure 1 , Figure 4 and Figure 5 Example systems 100, 400, and / or 500 execute, for example, to produce Figure 2D Example of a modified PWM waveform 261.

[0136] At position 910, the start of the PWM cycle is determined. For example, it can be identified... Figure 2A Example PWM period 205 or Figure 2D The example PWM cycle is 265 at the beginning.

[0137] At 920, a decision is made. If a modified PWM output is not required (e.g., the PWM pulse duration is long enough to allow switch 122 to accurately replicate), the process continues at 930. If a modified PWM output is required (e.g., the PWM pulse duration is too short for switch 122 to accurately replicate), the process continues at 960.

[0138] At 930, process 900 begins operating in "normal" PWM mode. At 940, a normal (e.g., unmodified) PWM duty cycle is determined for the output signal, and at 950, (e.g., to...) Figure 1 Example switch 112) provides a normal PWM signal.

[0139] At 960, process 900 begins operating in a "modified" PWM mode. At 970, the modified PWM duty cycle is determined. For example, the example PWM cycle time period 207 can be extended to an example PWM cycle time period 267. In some examples, the example PWM duty cycle can be modified to provide an example PWM pulse duration 272 (e.g., to proportionally compensate for the extended PWM cycle). In some implementations, step 970 can effectively reduce the frequency of the PWM signal by a predetermined amount (e.g., based on setpoint value 101, switching parameters 103, and / or feedback from electrical load 102). At 980, the modified signal is provided (e.g., to switch 112).

[0140] Figure 10This is a schematic diagram of an example of a general-purpose computer system 1000. According to one implementation, system 1000 can be used in conjunction with the operations described in example procedure 300. For example, system 1000 can be included in any one or all of PWM controller 110, PWM controller 410, and PWM controller 510.

[0141] System 1000 includes a processor 1010, a memory 1020, a storage device 1030, and an input / output device 1040. Each of components 1010, 1020, 1030, and 1040 is interconnected using a system bus 1050. Processor 1010 is capable of processing instructions for execution within system 1000. In one implementation, processor 1010 is a single-threaded processor. In another implementation, processor 1010 is a multi-threaded processor. Processor 1010 is capable of processing instructions stored in memory 1020 or on storage device 1030 to display graphical information of a user interface on input / output device 1040.

[0142] Memory 1020 stores information within system 1000. In one implementation, memory 1020 is a computer-readable medium. In one implementation, memory 1020 is a volatile memory cell. In another implementation, memory 1020 is a non-volatile memory cell.

[0143] Storage device 1030 provides large-capacity storage for system 1000. In one implementation, storage device 1030 is a computer-readable medium. In various implementations, storage device 1030 may be a non-volatile memory cell, a floppy disk device, a hard disk device, an optical disk device, or a magnetic tape device.

[0144] Input / output device 1040 provides input / output operations for system 1000. In one implementation, input / output device 1040 includes a keyboard and / or a pointing device. In another implementation, input / output device 1040 includes a display unit for displaying a graphical user interface.

[0145] The described features can be implemented in digital electronic circuits, or in computer hardware, firmware, software, or a combination thereof. The apparatus can be implemented in a computer program product tangibly embodied in an information carrier, for example, in a machine-readable storage device for execution by a programmable processor; and method steps can be executed by a programmable processor executing an instruction program to perform the described functions by manipulating input data and generating output. The described features can advantageously be implemented in one or more computer programs executable on a programmable system including at least one programmable processor coupled to receive and transmit data and instructions from and to a data storage system, at least one input device, and at least one output device. A computer program is a set of instructions that can be used directly or indirectly in a computer to perform an activity or produce a result. A computer program can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0146] Suitable processors for executing instructions include, for example, both general-purpose microprocessors and special-purpose microprocessors, as well as a single processor or one or more processors in any kind of computer. Generally, the processor receives instructions and data from read-only memory or random access memory, or both. The basic components of a computer are a processor for executing instructions and one or more memories for storing instructions and data. Generally, a computer will also include one or more mass storage devices for storing data files, or operatively coupled to and in communication with such mass storage devices; such devices include: disks, such as internal hard disks and removable disks; magneto-optical disks; and optical disks. Storage devices suitable for tangibly representing computer program instructions and data include all forms of non-volatile memory, which, as examples, include: semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and memory may be supplemented or integrated with ASICs (Application-Specific Integrated Circuits).

[0147] To provide interaction with the user, these features can be implemented on a computer with a display device for displaying information to the user (such as a CRT (cathode ray tube) or LCD (liquid crystal display) monitor), and a keyboard and pointing device (such as a mouse or trackball) through which the user can provide input to the computer.

[0148] These features can be implemented in computer systems that include backend components (such as data servers), or in computer systems that include middleware components (such as application servers or internet servers), or in computer systems that include frontend components (such as client computers with graphical user interfaces or internet browsers), or in any combination thereof. The components of the system can be connected via digital data communication of any form or medium (such as communication networks). Examples of communication networks include, for example, LANs, WANs, and computers and networks that form the Internet.

[0149] A computing system may include clients and servers. Clients and servers are typically geographically separated and usually interact via a network (such as the network described). The client-server relationship arises from computer programs running on their respective computers that have a client-server relationship with each other.

[0150] Although several embodiments have been described in detail above, other modifications are possible. Furthermore, the logical flow depicted in the accompanying drawings does not require a specific order or sequence to achieve the desired result. Additionally, other steps may be provided, or steps may be eliminated from the described flow, and other components may be added to or removed from the described system. Accordingly, other implementations are also within the scope of the appended claims.

Claims

1. A computer-implemented method for current control, comprising: receiving a first current output setpoint; identifying a first operating condition based on the first current output setpoint; providing a first pulse width modulated (PWM) signal having a first predetermined duty cycle based on the first current output setpoint and provided for a predetermined time period based on the identified first operating condition; receiving a second current output setpoint; identifying a second operating condition different from the first operating condition based on the second current output setpoint, wherein identifying the second operating condition is based on a minimum off time of a switch configured to transmit the PWM signal to a load; and providing a second PWM signal having a second predetermined duty cycle based on the second current output setpoint and provided for a predetermined multiple of the predetermined time period based on the identified second operating condition. providing the first PWM signal comprises:

2. The computer-implemented method of claim 1, wherein, determining a start of a PWM period having a first duration based on the predetermined time period; providing an electrical signal; stopping the electrical signal based on a determination that the electrical signal has been provided a second duration based on the first predetermined duty cycle and the second duration has elapsed; and determining an end of the PWM period based on a determination that the first duration has elapsed. providing the second PWM signal comprises:

3. The computer-implemented method of claim 1, wherein, determining a start of a first PWM period having a first duration based on the predetermined time period; providing an electrical signal; stopping the electrical signal based on a determination that a second duration based on the second predetermined duty cycle has elapsed; determining an end of the first PWM period based on a determination that the first duration has elapsed; determining a start of a predetermined number of second PWM periods having the first duration based on the predetermined time period, the predetermined number based on the predetermined multiple; stopping the electrical signal during the second PWM periods; and determining that the end of the predetermined number of second PWM periods has occurred.

4. The computer-implemented method of claim 3, further comprising determining the predetermined multiple based on the second operating condition. providing the second PWM signal comprises:

5. The computer-implemented method of any one of claims 1 to 4, wherein, determining a start of a PWM period having a second duration based on the predetermined time period and the predetermined multiple; providing an electrical signal; stopping the electrical signal based on a determination that a second duration based on the second predetermined duty cycle has elapsed; and determining an end of the PWM period based on a determination that the second duration has elapsed. providing the second PWM signal comprises:

6. The computer-implemented method of any one of claims 1 to 4, wherein, generating PWM pulses at a frequency based on the predetermined time period; transmitting electrical pulses based on the generated PWM pulses; and ignoring a predetermined number of PWM pulses based on the predetermined multiple. identifying the first operating condition is based on:

7. The computer-implemented method of any one of claims 1 to 4, wherein, determining a target duty cycle based on the first current output setpoint; determining that the target duty cycle is equal to or longer than a predetermined threshold duty cycle; and providing the target duty cycle as the first predetermined duty cycle. identifying the second operating condition is based on: determining a target duty cycle based on the second current output setpoint; 8. The computer-implemented method of any one of claims 1 to 4, wherein, determining that the target duty cycle is shorter than a predetermined threshold duty cycle; and providing the target duty cycle as the second predetermined duty cycle. determining a target duty cycle based on the second current output setpoint; determining that the target duty cycle is shorter than a predetermined threshold duty cycle; and determining the second predetermined duty cycle based on the target duty cycle.

9. A control system, the control system comprising: an input configured to receive a current setpoint; a monitoring circuit configured to identify at least a first operating condition and a second operating condition based on the received current setpoint; a pulse generator configured to generate a pulse width modulated (PWM) signal comprising a plurality of PWM pulses based on the received current setpoint; a pulse suppressor configured to modify the PWM signal by passing the PWM pulses based on the first operating condition and by preventing selected PWM pulses in the PWM signal and passing unselected PWM pulses based on the second operating condition; and a transmitter configured to transmit the modified PWM signal to a load; wherein the monitoring circuit is configured to identify the second operating condition based on a minimum off time of the transmitter.

10. The control system of claim 9, wherein, the first operating condition is identified based on a first current setpoint and the second operating condition is identified based on a second current setpoint, and the pulse generator is further configured to generate a first PWM signal based on the first current setpoint and a second PWM signal based on the second current setpoint.

11. The control system of claim 9, wherein, the first operating condition is identified based on a first current setpoint and the second operating condition is identified based on a second current setpoint, and the monitoring circuit is further configured to identify a first operating condition based on the first current setpoint and a second operating condition based on the second current setpoint.

12. The control system of any one of claims 9 to 11, wherein, the monitoring circuit is configured to identify one or both of the first operating condition and the second operating condition further based on one or more operating inputs descriptive of the load or operation of the load, wherein operation of the load is controlled based on the PWM signal.

13. The control system of any one of claims 9 to 11, wherein, the pulse suppressor is configured to modify operation of the pulse generator such that the pulse generator suppresses generation of the selected PWM pulses of the PWM signal.

14. The control system of any one of claims 9 to 11, wherein, the pulse suppressor is configured to modify operation of the pulse generator such that the pulse generator modifies a frequency of the PWM signal.

15. The control system of any one of claims 9 to 11, wherein, the pulse suppressor is configured to prevent the selected PWM pulses generated by the pulse generator.

16. The control system of any one of claims 9 to 11, wherein, the selected PWM pulses are a predetermined number of sequential PWM pulses.

17. The control system of claim 16, wherein, the predetermined number of sequential PWM pulses is based on the second operating condition.

18. A non-transitory computer storage medium encoded with a computer program, the computer program comprising instructions that when executed by a data processing apparatus cause the data processing apparatus to perform operations comprising: receiving a first current output setpoint; identifying a first operating condition based on the first current output setpoint; providing a first pulse width modulation (PWM) signal having a first predetermined duty cycle based on the identified first operating condition, the first PWM signal being based on the first current output setpoint and provided for a predetermined time period; receiving a second current output setpoint; identifying a second operating condition different from the first operating condition based on the second current output setpoint, wherein identifying the second operating condition is based on a minimum off time of a switch configured to transmit the PWM signal to a load; and providing a second PWM signal having a second predetermined duty cycle based on the identified second operating condition, the second PWM signal being based on the second current output setpoint and provided for a predetermined multiple of the predetermined time period.

19. The non-transitory computer storage medium of claim 18, wherein, providing the first PWM signal includes: determining a start of a PWM period having a first duration based on the predetermined time period; providing an electrical signal; stopping the electrical signal based on a determination that a second duration based on the first predetermined duty cycle has elapsed; and determining an end of the PWM period based on a determination that the first duration has elapsed.

20. The non-transitory computer storage medium of claim 18, wherein, providing the second PWM signal includes: determining a start of a first PWM period having a first duration based on the predetermined time period; providing an electrical signal; stopping the electrical signal based on a determination that a second duration based on the second predetermined duty cycle has elapsed; determining an end of the first PWM period based on a determination that the first duration has elapsed; determining a start of a predetermined number of second PWM periods having the first duration based on the predetermined time period, the predetermined number being based on the predetermined multiple; stopping the electrical signal during the second PWM periods; and determining that the end of the predetermined number of second PWM periods has occurred.

21. The non-transitory computer storage medium of claim 20, the operations further comprising determining the predetermined multiple based on the second operating condition.

22. The non-transitory computer storage medium of any one of claims 18 to 21, wherein, providing the second PWM signal includes: determining a start of a PWM period having a second duration based on the predetermined time period and the predetermined multiple; providing an electrical signal; stopping the electrical signal based on a determination that a second duration based on the second predetermined duty cycle has elapsed; and determining an end of the PWM period based on a determination that the second duration has elapsed.

23. The non-transitory computer storage medium of any one of claims 18 to 21, wherein, providing the second PWM signal includes: generating PWM pulses at a frequency based on the predetermined time period; transmitting electrical pulses based on the generated PWM pulses; and ignoring a predetermined number of PWM pulses based on the predetermined multiple.

24. The non-transitory computer storage medium of any one of claims 18 to 21, wherein, identifying the first operating condition is based on: determining a target duty cycle based on the first current output setpoint; determining that the target duty cycle is equal to or longer than a predetermined threshold duty cycle; and providing the target duty cycle as the first predetermined duty cycle. identifying the second operating condition is based on:

25. The non-transitory computer storage medium of any one of claims 18 to 21, wherein, determining a target duty cycle based on the second current output setpoint; determining that the target duty cycle is shorter than a predetermined threshold duty cycle; and determining the second predetermined duty cycle based on the target duty cycle. ​ ​ 26. The non-transitory computer storage medium of claim 19 or 20, wherein, providing the second PWM signal includes: determining a start of a first PWM period having a first duration based on the predetermined time period; providing an electrical signal; stopping the electrical signal based on a determination that a second duration based on the second predetermined duty cycle has elapsed; determining an end of the first PWM period based on a determination that the first duration has elapsed; determining a start of a predetermined number of second PWM periods having the first duration based on the predetermined time period, the predetermined number based on the predetermined multiple; stopping the electrical signal during the second PWM periods; and determining that the end of the predetermined number of second PWM periods has occurred.

27. The non-transitory computer storage medium of claim 26, the operations further comprising determining the predetermined multiple based on the second operating condition.

28. The computer-implemented method of claim 2, wherein, providing the second PWM signal includes: determining a start of a first PWM period having a first duration based on the predetermined time period; providing an electrical signal; stopping the electrical signal based on a determination that a second duration based on the second predetermined duty cycle has elapsed; determining an end of the first PWM period based on a determination that the first duration has elapsed; determining a start of a predetermined number of second PWM periods having the first duration based on the predetermined time period, the predetermined number based on the predetermined multiple; stopping the electrical signal during the second PWM periods; and determining that the end of the predetermined number of second PWM periods has occurred.

29. The computer-implemented method of claim 28, further comprising determining the predetermined multiple based on the second operating condition.

30. The computer-implemented method of claim 5, wherein, providing the second PWM signal includes: generating PWM pulses at a frequency based on the predetermined time period; emitting electrical pulses based on the generated PWM pulses; and ignoring a predetermined number of PWM pulses based on the predetermined multiple.

31. The computer-implemented method of claim 5, wherein, identifying the first operating condition is based on: determining a target duty cycle based on the first current output setpoint; determining that the target duty cycle is equal to or longer than a predetermined threshold duty cycle; and providing the target duty cycle as the first predetermined duty cycle.

32. The computer-implemented method of claim 6, wherein, identifying the first operating condition is based on: determining a target duty cycle based on the first current output setpoint; determining that the target duty cycle is equal to or longer than a predetermined threshold duty cycle; and providing the target duty cycle as the first predetermined duty cycle.

33. The control system of claim 10, wherein, the first operating condition is identified based on a first current setpoint and the second operating condition is identified based on a second current setpoint, and the monitoring circuit is further configured to identify a first operating condition based on the first current setpoint and a second operating condition based on the second current setpoint.

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