Switching power supply secondary side synchronous rectification controller and switching power supply

Abstract

The embodiment of the present application discloses a switching power supply secondary-side synchronous rectification controller and a switching power supply, wherein the synchronous rectification controller includes: a demagnetization detection circuit, a standby judgment circuit, an AND gate circuit, and a drive circuit; wherein the input end of the demagnetization detection circuit is connected to one end of the synchronous rectification MOS Q2 of the switching power supply, an output end of the demagnetization detection circuit is connected to an input end of the AND gate circuit, another output end of the demagnetization detection circuit is connected to the input end of the standby judgment circuit, the output end of the standby judgment circuit is connected to another input end of the AND gate circuit, the output end of the AND gate circuit is connected to the input end of the drive circuit, and the output end of the drive circuit is connected to the gate of the MOS Q2. The technical solution of the present application has the advantage of improving system efficiency.

Description

Technical Field

[0001] The present application relates to the technical field of switching power supplies, and in particular to a switching power supply secondary-side synchronous rectification controller and a switching power supply. Background Art

[0002] As the charging power of mobile terminals continues to grow, energy efficiency is gaining increasing attention, and countries and regions are continuously improving their energy efficiency standards. The use of synchronous rectifier controllers, replacing traditional Schottky diode rectification, has greatly improved the charging efficiency of adapters and chargers, leading to their increasing widespread adoption. However, while existing synchronous rectifier controller technologies do improve charging efficiency when the power supply system is heavily loaded, they overlook the fact that the synchronous rectifier controller's own power consumption when the power supply is unloaded or lightly loaded reduces system efficiency and increases system standby power consumption, wasting significant energy and increasing energy consumption. Summary of the Invention

[0003] Therefore, in order to solve the problem of high energy consumption in the prior art, the present application proposes a synchronous rectification controller for the secondary side of a switching power supply.

[0004] This application solves the above problems through the following technical means:

[0005] The present application provides a secondary-side synchronous rectification controller for a switching power supply, the synchronous rectification controller comprising: a demagnetization detection circuit, a standby determination circuit, an AND gate circuit, and a drive circuit; wherein an input end of the demagnetization detection circuit is connected to one end of a synchronous rectification MOS Q2 of the switching power supply, an output end of the demagnetization detection circuit is connected to an input end of the AND gate circuit, another output end of the demagnetization detection circuit is connected to an input end of the standby determination circuit, an output end of the standby determination circuit is connected to another input end of the AND gate circuit, an output end of the AND gate circuit is connected to an input end of the drive circuit, and an output end of the drive circuit is connected to a gate end of the MOS Q2;

[0006] The demagnetization detection circuit is used to detect the voltage difference VDET between the drain and source of the MOS Q2, and output a DEMAG signal through two output terminals when the VDET is lower than a set threshold;

[0007] The standby judgment circuit is used to integrate the DEMAG signal and compare it with the set threshold to obtain a comparison result, and determine the output signal V according to the comparison result. G-EN whether it is effective;

[0008] The AND gate circuit is used to generate a voltage according to the DEMAG signal and V G-EN Output V gate Signal;

[0009] The driving circuit is used togate The signal determines whether to output the VG signal to the gate of the MOS Q2 to drive the MOS Q2.

[0010] Optionally, the demagnetization detection circuit includes: a first comparator, an inverter INV, a resistor, and a reference voltage V DET-ref ;in,

[0011] The positive input terminal of the first comparator is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to VDET, and the negative input terminal of the first comparator is connected to the reference voltage V DET-ref The two ends of the second resistor R2 are respectively connected to the non-inverting input terminal and the output terminal of the first comparator, and the output terminal of the first comparator outputs the DEMAG signal through the inverter INV.

[0012] Optionally, the standby judgment circuit includes: a current source, a MOS tube, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D trigger, and an inverter; wherein,

[0013] The drain of the first MOS tube is connected to the current source I charge The gate of the first MOS transistor is connected to the DEMAG signal, the source of the first MOS transistor is connected to the drain of the second MOS transistor and one end of the capacitor C1, the gate of the second MOS transistor is connected to the clock signal CLK, and the source of the second MOS transistor and the other end of the capacitor C1 are grounded;

[0014] The non-inverting input terminals of the second comparator and the third comparator are both connected to the source of the first MOS tube, and the inverting input terminal of the second comparator is connected to the voltage V TH , the enable terminal of the second comparator is connected to The inverting input terminal of the third comparator is connected to the voltage V TL , the enable terminal of the third comparator is connected to V G-EN ;

[0015] The two input ends of the OR gate circuit are connected to the output end of the second comparator and the output end of the third comparator respectively. The output end of the OR gate circuit is connected to the input end of the buffer circuit BUF. The output end of the buffer circuit BUF is connected to the signal input end of the D flip-flop. The clock port of the D flip-flop is connected to the clock signal CLK. The output end of the D flip-flop outputs V G-EN , V G-EN The signal is output through the inverter Signal.

[0016] Optionally, the standby judgment circuit uses V C1 With V TH 、V TL The size relationship can be used to determine whether the switching power supply is in a heavy load or light load state in the current cycle.

[0017] Optionally, the standby judgment circuit includes: a resistor, an operational amplifier, a MOS tube, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D trigger, and an inverter; wherein,

[0018] One end of a fifth resistor R5 is connected to the DEMAG signal, and the other end is connected to the non-inverting input of the operational amplifier. The inverting input of the operational amplifier is connected to the source of the first MOS transistor, and the drain of the first MOS transistor is connected to the output of the operational amplifier. The positive power supply of the operational amplifier is connected to the voltage source VCC, and the negative power supply is grounded. Two ends of a sixth resistor R6 are respectively connected to the inverting input of the operational amplifier and the reference ground. Two ends of a first capacitor C1 are respectively connected to the output and inverting input of the operational amplifier.

[0019] One end of the second capacitor C2 is connected to the non-inverting input terminal of the operational amplifier, the other end of the second capacitor C2 is grounded, the drain of the second MOS transistor is connected to the non-inverting input terminal of the operational amplifier, the source of the second MOS transistor is grounded, and the gate of the second MOS transistor and the gate of the first MOS transistor are both connected to the clock signal CLK;

[0020] The non-inverting input terminals of the second and third comparators are connected to the output terminal V C1 , the inverting input of the second comparator is connected to the voltage V TH , the enable terminal of the second comparator is connected to The inverting input terminal of the third comparator is connected to the voltage V TL , the enable terminal of the third comparator is connected to V G-EN ;

[0021] The two input ends of the OR gate circuit are connected to the output end of the second comparator and the output end of the third comparator respectively. The output end of the OR gate circuit is connected to the input end of the buffer circuit BUF. The output end of the buffer circuit BUF is connected to the signal input end of the D flip-flop. The clock port of the D flip-flop is connected to the clock signal CLK. The output end of the D flip-flop outputs V G-EN , V G-EN The signal is obtained through the inverter Signal.

[0022] Optionally, the standby judgment circuit uses V C1 With V TH 、V TL The size relationship can be used to determine whether the switching power supply is in a heavy load or light load state in the current cycle.

[0023] Optionally, the standby judgment circuit includes: a resistor, an operational amplifier, a MOS tube, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D trigger, and an inverter; wherein,

[0024] One end of the fifth resistor R5 is connected to the DEMAG signal, and the other end is connected to the inverting input terminal of the operational amplifier. The non-inverting input terminal of the operational amplifier is grounded, the positive power supply terminal is connected to the voltage source VCC, and the negative power supply terminal is connected to the voltage source -VCC. The two ends of the first capacitor C1 are respectively connected to the output terminal and the inverting input terminal of the operational amplifier;

[0025] The drain of the first MOS transistor is connected to the inverting input terminal of the operational amplifier, the source of the first MOS transistor is connected to the output terminal of the operational amplifier, and the gate of the first MOS transistor is connected to the clock signal CLK;

[0026] The inverting input terminals of the second and third comparators are both connected to the output terminal V C1 , the non-inverting input of the second comparator is connected to the voltage -V TH , the enable terminal of the second comparator is connected to The non-inverting input of the third comparator is connected to the voltage -V TL , the enable terminal of the third comparator is connected to V G-EN ;

[0027] The two input ends of the OR gate circuit are connected to the output end of the second comparator and the output end of the third comparator respectively. The output end of the OR gate circuit is connected to the input end of the buffer circuit BUF. The output end of the buffer circuit BUF is connected to the signal input end of the D flip-flop. The clock port of the D flip-flop is connected to the clock signal CLK. The output end of the D flip-flop outputs V G-EN , V G-EN The signal is obtained through the inverter Signal.

[0028] Optionally, the standby judgment circuit uses V C1 with -V TH 、-V TL The size relationship can be used to determine whether the switching power supply is in a heavy load or light load state in the current cycle.

[0029] The present application also provides a switching power supply, which includes: the above-mentioned switching power supply secondary-side synchronous rectification controller.

[0030] Optionally, the switching power supply is: a flyback converter topology circuit, a forward converter topology circuit, an LLC converter topology circuit, a half-bridge converter topology circuit, a full-bridge converter topology circuit or a push-pull converter topology circuit.

[0031] The synchronous rectification controller and its standby mode control circuit proposed in this application generate a demagnetization signal DEMAG by detecting the voltage drop across the synchronous rectification MOS, and detects a fixed time T CLK Internal DEMAG effective time t on The length of the output V G_EN, determine whether to switch between normal working mode and standby mode. When the synchronous rectifier controller of the present application switches from normal working mode to standby mode when it enters light load or no load from heavy load, it can reduce the power consumption of the synchronous rectifier controller and achieve the purpose of improving system efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0033] Figure 1 This is a schematic block diagram of a secondary-side synchronous rectification controller for a switching power supply provided by this application;

[0034] Figure 2 This is a schematic diagram of the synchronous rectification controller and its standby mode control principle provided by this application;

[0035] Figure 3 This is a schematic diagram of the key waveforms when the synchronous rectification controller of the present application switches from a heavy load to a light load or no load and switches from a normal working mode to a standby mode;

[0036] Figure 4 This is a schematic diagram of the key waveforms of the synchronous rectification controller of the present application switching from standby mode to normal working mode when it enters heavy load from light load or no load;

[0037] Figure 5 is a control flow chart of the synchronous rectification controller proposed in this application;

[0038] Figure 6 This is another control principle diagram of the synchronous rectification controller and its standby mode proposed in this application;

[0039] Figure 7 This is another control principle diagram of the synchronous rectification controller and its standby mode proposed in this application. DETAILED DESCRIPTION

[0040] To make the above-mentioned purposes, features, and advantages of this application more clearly understood, the technical solutions of this application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0041] See Figure 1 , Figure 1This is a schematic block diagram of the secondary-side synchronous rectification controller of the switching power supply of the present application, wherein the switching power supply can be any one of the topology circuits such as the flyback converter topology circuit, the forward converter topology circuit, the LLC converter topology circuit, the half-bridge converter topology circuit, the full-bridge converter topology circuit, and the push-pull converter topology circuit, see Figure 1 The synchronous rectification controller includes: a demagnetization detection circuit, a standby determination circuit, an AND gate, and a drive circuit. The input of the demagnetization detection circuit is connected to one end of the synchronous rectification MOS Q2 of the switching power supply, an output of the demagnetization detection circuit is connected to an input of the AND gate circuit, another output of the demagnetization detection circuit is connected to the input of the standby determination circuit, an output of the standby determination circuit is connected to another input of the AND gate circuit, an output of the AND gate circuit is connected to the input of the drive circuit, and an output of the drive circuit is connected to the gate of the MOS Q2.

[0042] The demagnetization detection circuit is used to detect the voltage difference VDET between the drain and source of the MOS Q2, and output a DEMAG signal through two output terminals when the VDET is lower than a set threshold.

[0043] The standby judgment circuit is used to integrate the DEMAG signal and compare it with the set threshold to obtain a comparison result, and determine the output channel V according to the comparison result. G-EN Is it valid?

[0044] The AND gate circuit is used to generate a voltage according to the DEMAG signal and V G-EN Output V gate Signal.

[0045] The driving circuit is used to gate The signal determines whether to output the VG signal to the gate of the MOS Q2 to drive the MOS Q2.

[0046] The synchronous rectifier controller proposed in this application has two working modes: normal working mode and standby mode. The demagnetization detection circuit samples the Vds across the synchronous rectifier MOS Q2 through the VDET pin, and gives a DEMAG signal when Vds is lower than the set threshold. The standby judgment circuit compares the integrated DEMAG signal with the set threshold to determine whether the current power supply system is lightly loaded or unloaded, thereby determining whether the synchronous rectifier controller enters the standby mode and giving a signal to enable the drive output signal V G_EN . V G_EN The driver circuit strengthens the driving capability based on the Vgate signal and outputs the VG signal to drive the synchronous rectifier MOS Q2.

[0047] Figure 2This is the first synchronous rectifier controller and its standby mode control principle diagram proposed in this application. Figure 1 Further detailed description of the synchronous rectification controller is given in FIG. Figure 2 The demagnetization detection circuit principle and the standby judgment circuit principle are given in detail. Specifically, the demagnetization detection circuit includes: a first comparator, an inverter INV, a resistor and a reference voltage V DET-ref The positive input terminal of the first comparator is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to VDET, and the negative input terminal of the first comparator is connected to the reference voltage V DET-ref The two ends of the second resistor R2 are respectively connected to the non-inverting input terminal and the output terminal of the first comparator, and the output terminal of the first comparator outputs the DEMAG signal through the inverter INV.

[0048] The standby judgment circuit includes: a current source, a MOS tube, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D trigger, and an inverter; wherein the drain of the first MOS tube is connected to the current source I charge The gate of the first MOS tube is connected to the DEMAG signal, the source of the first MOS tube is connected to the drain of the second MOS tube and one end of the capacitor C1, the gate of the second MOS tube is connected to the clock signal CLK, and the source of the second MOS tube and the other end of the capacitor C1 are grounded; the non-inverting input terminals of the second comparator and the third comparator are connected to the source of the first MOS tube, and the inverting input terminal of the second comparator is connected to the voltage V TH , the enable terminal of the second comparator is connected to The inverting input terminal of the third comparator is connected to the voltage V TL , the enable terminal of the third comparator is connected to V G-EN ;

[0049] The two input ends of the OR gate circuit are connected to the output end of the second comparator and the output end of the third comparator respectively. The output end of the OR gate circuit is connected to the input end of the buffer circuit BUF. The output end of the buffer circuit BUF is connected to the signal input end of the D flip-flop. The clock port of the D flip-flop is connected to the clock signal CLK. The output end of the D flip-flop outputs V G-EN , V G-EN The signal is output through the inverter Signal.

[0050] like Figure 2 The demagnetization detection circuit shown contains R1, R2, comparator 1 and reference voltage V DET_ref When the sampling VDET voltage drops rapidly and falls below (For example, when it is set to -85mV), the comparator 1 outputs a low level, and after passing through the inverter INV, it outputs a DEMAG high level, indicating that the demagnetization begins. When the sampled VDET voltage gradually rises and is higher than When the voltage is set to about -5mV, the comparator 1 outputs a high level, and after passing through the inverter INV, it outputs a DEMAG low level, indicating that the demagnetization is detected to be completed.

[0051] Figure 2 The principle of the standby judgment circuit is also given. During the demagnetization process, that is, when DEMAG is high, the DEMAG signal drives MOS Q1 to turn on, and the current source I charge Charge capacitor C1, V C1 The rising level is: where t ON is the time duration of DEMAG being high. When DEMAG is low, that is, not in the demagnetization time, MOS Q1 is turned off, and V C1 Each VDET pulse will repeat the above process to achieve V C1 The voltage rises and accumulates during each DEMAG high period. CLK V inside C1 Voltage and set threshold V TL / V TH The relationship between the size of T can be used to determine the heavy load or light load state of the switching power supply in the current cycle, and then control the synchronous rectifier to enter the normal working mode or standby mode. CLK and V TL / V TH Both can be set, which makes it convenient to set different standby mode trigger thresholds in different applications.

[0052] There are four situations in the standby judgment circuit: 1. Entering the standby mode from the normal working mode, that is, V G_EN From the high level of the current cycle to the low level of the next CLK cycle; 2. Maintain normal working mode, that is, maintain the current V G_EN 3. Restore from standby mode to normal working mode, that is, V G_EN From the current cycle low level to the next CLK cycle high level; 4. Keep in standby mode, that is, keep the current V G_EN is low level.

[0053] The first and second cases mentioned above both occur when the current V G_EN When it is high, the synchronous rectifier controller is in normal working mode, and the comparator 3 enables the signal V G_EN High, output valid level, comparator 2 enable signal is low, the output is always low. When the next rising edge of CLK comes, if V C1 >V TL, then the output of comparator 3 is high level, after the OR gate and BUF delay, the VD signal is high level, and the D flip-flop outputs V G_EN Keep it at high level, that is, the second case of the standby judgment circuit: the synchronous rectification controller maintains normal working mode. When the next rising edge of CLK comes, if V C1 ≤V TL , then the output of comparator 3 is low level, and comparator 2 is low level due to the enable signal is low, the output is always low, after the OR gate and BUF delay, the VD signal is low, and the D flip-flop outputs V G_EN The high level turns into the low level, which is the first situation of the standby judgment circuit: the synchronous rectification controller enters the standby mode from the normal working mode.

[0054] The above cases 3 and 4 both occur when the current V G_EN When the synchronous rectifier controller is in standby mode, the comparator 3 enables the signal V G_EN is low, the output is always low, and the comparator 2 enables the signal When the next rising edge of CLK comes, if V C1 >V TH , then the output of comparator 2 is high level, after the OR gate and BUF delay, the VD signal is high level, and the D flip-flop outputs V G_EN From low level to high level, it is the third situation of the standby judgment circuit: the synchronous rectification controller recovers from standby mode to normal working mode. If the next rising edge of CLK comes, V C1 ≤V TH , then the output of comparator 2 is low level, and comparator 3 is low level due to the enable signal V G_EN is low, the output is always low, after the OR gate and BUF delay, the VD signal is low, and the D flip-flop outputs V G_EN Maintaining a low level indicates the fourth situation of the standby judgment circuit: the synchronous rectification controller maintains the standby mode.

[0055] Standby judgment circuit output signal V G_EN The demagnetization signal DEMAG is input into the AND gate together, and the AND gate outputs V gate To the drive circuit. The drive circuit strengthens the driving capability and outputs a V gate The synchronous signal VG is given to the gate of the synchronous rectifier MOS Q2 to control the switching of the synchronous rectifier MOS. The above is the basic principle of the synchronous rectifier controller and its standby mode control implemented in this application.

[0056] Figure 3This is a key waveform diagram of the synchronous rectifier controller of this application switching from normal working mode to standby mode when it enters light load or no load from heavy load. At the beginning of time, t = 0, CLK sends a pulse signal. When the pulse signal is high, MOS Q2 is turned on to discharge the capacitor C1. V C1 Discharge quickly to zero, such as Figure 3 Medium V C1 As shown in the waveform. After the CLK pulse, whenever VDET drops rapidly and satisfies "VDET<V DET_ref_L ", the demagnetization signal DEMAG becomes high, and V G_EN Through the AND gate output V gate At the same time, the demagnetization signal DEMAG is high and drives MOS Q1 to turn on, charging the capacitor C1. C1 The rising level is: where t ON is the duration of DEMAG being high. When DEMAG is low, that is, not in the demagnetization time, MOS Q1 is turned off and VC1 remains unchanged. Each VDET pulse will repeat the above process, thus achieving V C1 The voltage rises and accumulates during each DEMAG high level period. Until the next rising edge of CLK arrives, V C1 The cumulative rise does not exceed V TL , the D flip-flop outputs V G_EN It changes from high level to low level and remains at low level before the next CLK comes, so that the synchronous rectification controller switches from normal working mode to standby mode.

[0057] Figure 4 This is a key waveform diagram of the synchronous rectifier controller of this application switching from standby mode to normal working mode when it enters heavy load from light load or no load. At the beginning of time, t = 0, CLK sends a pulse signal. When the pulse signal is high, MOS Q2 is turned on to discharge the capacitor C1. V C1 Discharge quickly to zero, as shown in the figure V C1 As shown in the waveform. After the CLK pulse, whenever VDET drops rapidly and satisfies "VDET<V DET_ref_L ", the demagnetization signal DEMAG becomes high, driving MOS Q1 to turn on and charge the capacitor C1, V C1 The rising level is: where t ON When DEMAG is low, that is, not in the demagnetization time, MOS Q1 is turned off, and V C1 Each VDET pulse will repeat the above process to achieve V C1The voltage rises and accumulates during each DEMAG high level period. Until the next rising edge of CLK arrives, V C1 Accumulate and rise to meet V C1 >V TH , the D flip-flop outputs V G_EN It changes from low level to high level and remains high level before the next CLK comes, so that the synchronous rectification controller switches from standby mode to normal working mode.

[0058] Figure 5 This is the control flow chart of the synchronous rectifier controller proposed in this application. The specific implementation circuit and implementation principle of the flow chart follow Figure 1 Synchronous Rectification Controller Block Diagram and Figure 2 The proposed synchronous rectification controller and its standby mode control principle. The detailed control process steps are as follows:

[0059] Step 1: Start;

[0060] Step 2: Power on and reset, initialize the sampling module, initialize the logic circuits of each part, and default VG to low level;

[0061] Step 3: Enter normal working mode, CLK generates pulses, V C1 Clear, V G_EN Enable, VG outputs normally;

[0062] Step 4: VDET detects the demagnetization time and charges C1 during the demagnetization time;

[0063] Step 5: T CLK When the timing ends and the next CLK pulse rises, V C1 Is it less than V TL If yes, go to step 6; if no, go to step 3;

[0064] Step 6: Enter standby mode, CLK pulses out, V C1 Clear, V G_EN If not enabled, VG has no output;

[0065] Step 7: VDET detects the demagnetization time and charges C1 during the demagnetization time;

[0066] Step 8: T CLK When the timing ends and the next CLK pulse rises, V C1 Is it greater than V TH If yes, go to step 3; if no, go to step 6.

[0067] Figure 6 This is another control principle diagram of the synchronous rectification controller and its standby mode proposed in this application, the demagnetization detection circuit and Figure 2The first proposed synchronous rectification controller and its standby mode control principle Figure 1 Same, the difference is Figure 2 The standby judgment circuit adopts DEMAG control I charge Charge capacitor C1 to achieve That is V C1 and t on A linear function relationship that is directly proportional to Figure 6 The standby determination circuit shown includes: a resistor, an operational amplifier, a MOS transistor, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein, one end of the fifth resistor R5 is connected to the DEMAG signal, and the other end is connected to the non-inverting input of the operational amplifier; the inverting input of the operational amplifier is connected to the source of the first MOS transistor, the drain of the first MOS transistor is connected to the output of the operational amplifier, the positive power supply of the operational amplifier is connected to the voltage source VCC, and the negative power supply is grounded; the two ends of the sixth resistor R6 are respectively connected to the inverting input of the operational amplifier and the reference ground; the two ends of the first capacitor C1 are respectively connected to the output and inverting input of the operational amplifier; one end of the second capacitor C2 is connected to the non-inverting input of the operational amplifier, the other end of the second capacitor C2 is grounded, the drain of the second MOS transistor is connected to the non-inverting input of the operational amplifier, the source of the second MOS transistor is grounded, and the gates of the second MOS transistor and the first MOS transistor are both connected to the clock signal CLK; the non-inverting inputs of the second comparator and the third comparator are both connected to the output of the operational amplifier V C1 , the inverting input of the second comparator is connected to the voltage V TH , the enable terminal of the second comparator is connected to The inverting input terminal of the third comparator is connected to the voltage V TL , the enable terminal of the third comparator is connected to V G-EN The two input ends of the OR gate circuit are connected to the output end of the second comparator and the output end of the third comparator respectively, the output end of the OR gate circuit is connected to the input end of the buffer circuit BUF, the output end of the buffer circuit BUF is connected to the signal input end of the D flip-flop, the clock port of the D flip-flop is connected to the clock signal CLK, and the output end of the D flip-flop outputs V G-EN , V G-EN The signal is obtained through the inverter Signal.

[0068] like Figure 6 As shown, Figure 6 The standby judgment circuit is replaced by a positive phase integration circuit composed of an operational amplifier, R5, C2, Q2, R6, C1, and Q1, and R5*C2=R6*C1, then we have Also realize V C1 and t on A linear function relationship that is proportional to V DEMAGIt is the voltage value when DEMAG is high level. When the second synchronous rectifier controller and its standby mode control principle diagram proposed in this application can realize the first synchronous rectifier controller and its standby mode control principle diagram Figure 1 Same functions, key waveform reference Figure 3 and Figure 4 .

[0069] Figure 7 This is another control principle diagram of the synchronous rectification controller and its standby mode proposed in this application, the demagnetization detection circuit and Figure 2 、 Figure 6 Proposed synchronous rectification controller and its standby mode control principle Figure 1 Exactly the same, such as Figure 7 The standby determination circuit shown includes: a resistor, an operational amplifier, a MOS transistor, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein, one end of the fifth resistor R5 is connected to the DEMAG signal, and the other end is connected to the inverting input of the operational amplifier; the non-inverting input of the operational amplifier is grounded, the positive power supply end is connected to the voltage source VCC, and the negative power supply end is connected to the voltage source -VCC; the two ends of the first capacitor C1 are respectively connected to the output and inverting input of the operational amplifier; the drain of the first MOS transistor is connected to the inverting input of the operational amplifier, the source of the first MOS transistor is connected to the output of the operational amplifier, and the gate of the first MOS transistor is connected to the clock signal CLK; the inverting inputs of the second and third comparators are both connected to the output of the operational amplifier V C1 , the non-inverting input of the second comparator is connected to the voltage -V TH , the enable terminal of the second comparator is connected to The non-inverting input of the third comparator is connected to the voltage -V TL , the enable terminal of the third comparator is connected to V G-EN The two input ends of the OR gate circuit are connected to the output end of the second comparator and the output end of the third comparator respectively, the output end of the OR gate circuit is connected to the input end of the buffer circuit BUF, the output end of the buffer circuit BUF is connected to the signal input end of the D flip-flop, the clock port of the D flip-flop is connected to the clock signal CLK, and the output end of the D flip-flop outputs V G-EN , V G-EN The signal is obtained through the inverter Signal.

[0070] See Figure 7 , the difference is Figure 2 The standby judgment circuit adopts DEMAG control I charge Charge capacitor C1 to achieve That is V C1 and t on A linear function relationship that is directly proportional; Figure 7Here, we replace it with a positive phase integrator circuit consisting of an operational amplifier, R5, C2, Q2, R6, C1, and Q1, and take R5*C2=R6*C1, then we have Also realize V C1 and t on A linear function relationship that is proportional to V DEMAG is the voltage value when DEMAG is high. Figure 7 Here, an inverting integration circuit consisting of an operational amplifier, R5, C1, and Q1 is used. Implement V C1 and t on A negatively correlated linear function relationship, where V DEMAG = is the voltage value when DEMAG is high. Since the output of VC1 of the inverting integrator is negative, the input conditions of comparator 2 and comparator 3 need to be adjusted accordingly: the input reference value is V TL / V TH Change to (-V TL ) / (-V TH ), and set the input reference value to the comparator positive input, V C1 The other parts of the standby judgment circuit are Figure 2 、 Figure 6 Stay consistent and achieve the same functionality.

[0071] In summary, the synchronous rectification controller and its standby mode control circuit proposed in this application generate a demagnetization signal DEMAG by detecting the voltage drop across the synchronous rectification MOS, and detects the fixed time T CLK Internal DEMAG effective time t on The length of the output V G_EN , determine whether to switch between normal working mode and standby mode. When the synchronous rectifier controller of the present application switches from normal working mode to standby mode when it enters light load or no load from heavy load, it can reduce the power consumption of the synchronous rectifier controller and achieve the purpose of improving system efficiency.

[0072] This application provides three representative synchronous rectifier controllers and their standby mode control circuits. These are preferred implementation examples only and are not intended to limit this application. Those skilled in the art will appreciate that various modifications and variations based on this application are possible. Any modifications, replacements, or improvements made within the design principles and spirit of this application are within the scope of this application.

Claims

1. A switching power supply secondary side synchronous rectification controller, characterized in that: The synchronous rectification controller includes: a demagnetization detection circuit, a standby judgment circuit, an AND gate circuit, and a drive circuit; wherein the input end of the demagnetization detection circuit is connected to one end of the synchronous rectification MOS Q2 of the switching power supply, an output end of the demagnetization detection circuit is connected to an input end of the AND gate circuit, another output end of the demagnetization detection circuit is connected to the input end of the standby judgment circuit, the output end of the standby judgment circuit is connected to the other input end of the AND gate circuit, the output end of the AND gate circuit is connected to the input end of the drive circuit, and the output end of the drive circuit is connected to the gate of the MOS Q2; The demagnetization detection circuit is used to detect the voltage difference VDET between the drain and source of the MOS Q2, and output a DEMAG signal through two output terminals when the VDET is lower than a set threshold; The standby judgment circuit is used to integrate the DEMAG signal and compare it with the set threshold to obtain a comparison result, and determine the output signal V according to the comparison result. G-EN whether it is effective; The AND gate circuit is used to generate a voltage according to the DEMAG signal and V G-EN Output V gate Signal; The driving circuit is used to gate The signal determines whether to output a VG signal to the gate of the MOS Q2 to drive the MOS Q2; The standby judgment circuit includes: a resistor, an operational amplifier, a MOS tube, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D trigger, and an inverter; wherein, One end of a fifth resistor R5 is connected to the DEMAG signal, and the other end is connected to the non-inverting input of the operational amplifier. The inverting input of the operational amplifier is connected to the source of the first MOS transistor, and the drain of the first MOS transistor is connected to the output of the operational amplifier. The positive power supply terminal of the operational amplifier is connected to the voltage source VCC, and the negative power supply terminal is grounded. Two ends of a sixth resistor R6 are respectively connected to the inverting input of the operational amplifier and the reference ground. Two ends of a first capacitor C1 are respectively connected to the output and inverting input of the operational amplifier. One end of the second capacitor C2 is connected to the non-inverting input terminal of the operational amplifier, the other end of the second capacitor C2 is grounded, the drain of the second MOS transistor is connected to the non-inverting input terminal of the operational amplifier, the source of the second MOS transistor is grounded, and the gate of the second MOS transistor and the gate of the first MOS transistor are both connected to the clock signal CLK; The non-inverting input terminals of the second and third comparators are connected to the output terminal V C1 , the inverting input terminal of the second comparator is connected to the voltage V TH , the enable terminal of the second comparator is connected The inverting input terminal of the third comparator is connected to the voltage V TL , the enable terminal of the third comparator is connected to V G-EN ; The two input ends of the OR gate circuit are connected to the output end of the second comparator and the output end of the third comparator respectively, the output end of the OR gate circuit is connected to the input end of the buffer circuit BUF, the output end of the buffer circuit BUF is connected to the signal input end of the D flip-flop, the clock port of the D flip-flop is connected to the clock signal CLK, and the output end of the D flip-flop outputs V G-EN , V G-EN The signal is obtained through the inverter Signal.

2. The switching power supply secondary side synchronous rectification controller according to claim 1, characterized in that: The demagnetization detection circuit includes: a first comparator, an inverter INV, a resistor and a reference voltage V DET-ref ;in, The positive input terminal of the first comparator is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the VDET, and the negative input terminal of the first comparator is connected to the reference voltage V DET-ref The two ends of the second resistor R2 are respectively connected to the non-inverting input terminal and the output terminal of the first comparator, and the output terminal of the first comparator outputs the DEMAG signal through the inverter INV.

3. The switching power supply secondary-side synchronous rectification controller according to claim 1, characterized in that: The standby judgment circuit is connected to the V C1 With V TH 、V TL The size relationship can be used to determine whether the switching power supply is in a heavy load or light load state in the current cycle.

4. A switching power supply, characterized in that: The switching power supply comprises: a switching power supply secondary-side synchronous rectification controller according to any one of claims 1 to 3.

5. The switching power supply according to claim 4, characterized in that: The switching power supply is a flyback converter topology circuit, a forward converter topology circuit, an LLC converter topology circuit, a half-bridge converter topology circuit, a full-bridge converter topology circuit or a push-pull converter topology circuit.

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