Silicon Carbide MOSFET Device with Lateral P+ Region

Abstract

The present invention discloses a silicon carbide MOSFET device, which includes a silicon carbide substrate of a first doping type, a first silicon carbide layer of the first doping type located on the silicon carbide substrate, a second silicon carbide layer of the second doping type embedded in the top portion of the first silicon carbide layer, a third silicon carbide layer of the first doping type embedded in the top portion of the second silicon carbide layer, a gate oxide layer overlapping the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer, and a fourth silicon carbide layer at least partially overlapping the second silicon carbide layer in a direction perpendicular to the silicon carbide substrate. In some embodiments, a P+ region arranged laterally with an N+ region allows sufficient P+ area to achieve good body diode performance and protection of the gate oxide, but does not occupy a significant area of ​​the MOSFET unit.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and in particular to silicon carbide MOSFET. Background Art

[0002] Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) have been widely used in green energy applications such as electric vehicles, solar energy, wind energy, and traction control. All of these applications are in harsh environments, requiring SiC MOSFETs to be extremely rugged and reliable. However, one of the well-known weaknesses of SiC MOSFETs is the gate oxide that is exposed to high electric fields during high temperature reverse bias of the device. Specific reliability tests, such as high temperature gate bias (HTGB) test and high temperature reverse bias (HTRB) test, have been designed to age the devices to ensure that the MOSFET operates for a long time (e.g., 1,000 hours) at temperature (e.g., 175C) and voltage bias (e.g., 1,200V). Many SiC MOSFETs fail these reliability tests, especially HTRB, and the weak point is always the gate oxide above the JFET region of the MOSFET.

[0003] In conventional technology, attempts have been made to increase the robustness of SiC MOSFETs in high temperature and / or high voltage bias environments. The basic working principle of MOSFET is that, whether it is SiC-MOSFET or Si-MOSFET; whether it is a planar structure or a trench structure, it has an intrinsic body diode formed by the P+ and N drift epitaxial layers. The characteristics of the body diode affect the quality of the overall MOSFET device. The forward characteristics and reverse recovery characteristics of the body diode play an important role in the application of power MOSFETs, such as power supplies, DC-DC converters, low voltage motor controllers, and many other applications. Therefore, the conventional method of enhancing the robustness of SiC MOSFETs is to increase the width of the P+ region as much as possible, and / or reduce the spacing between two adjacent P+ regions. The SiC MOSFET obtained in this way can allow sufficient P+ region to achieve good body diode performance and protection of the gate oxide. However, this comes at a cost: either increase the MOSFET cell spacing and consume a large area of ​​the MOSFET cell, or increase the JFET resistance and reduce the MOSFET performance. Summary of the invention

[0004] In view of the above background, an object of the present invention is to address the above drawbacks and propose an alternative SiC MOSFET to better protect the gate oxide in these devices.

[0005] The above objects are achieved by the feature combinations of the independent claims in the present application. The dependent claims in the present application disclose further advantageous embodiments of the invention.

[0006] Those skilled in the art will derive other objects of the present invention from the following description. Therefore, the above object statement is not exhaustive, but is only used to illustrate some of the many objects of the present invention.

[0007] Therefore, the present invention provides a silicon carbide MOSFET device in one aspect, which includes: a silicon carbide substrate of a first doping type, a first silicon carbide layer of a first doping type on the silicon carbide substrate, a second silicon carbide layer of a second doping type embedded in the top of the first silicon carbide layer, a third silicon carbide layer of a first doping type embedded in the top of the second silicon carbide layer, a fourth silicon carbide layer at least partially overlapping the second silicon carbide layer in a direction perpendicular to the silicon carbide substrate, a gate oxide layer overlapping the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer, and a polysilicon layer in contact with the gate oxide layer as a gate material of the silicon carbide MOSFET. The first silicon carbide layer formed by an epitaxial process has a lower doping amount than the silicon carbide substrate and defines a drift region. The third silicon carbide layer formed by an ion implantation process has a higher doping amount than the first silicon carbide layer. The third silicon carbide layer includes a plurality of third portions extending substantially along the first direction. The second silicon carbide layer formed by an ion implantation process includes a plurality of second portions extending substantially along the first direction. The fourth silicon carbide layer formed by the ion implantation process has a higher doping amount than the second silicon carbide layer. The fourth silicon carbide layer includes a plurality of fourth portions extending substantially along a second direction perpendicular to the first direction. Both the first and second directions are parallel to the silicon carbide substrate.

[0008] In some embodiments, the first doping type is N and the second doping type is P. The third silicon carbide layer is an N+ layer, and the third portions of the third silicon carbide layer are spaced apart from each other along the second direction. The fourth silicon carbide layer is a P+ layer, and the fourth portions are P+ portions spaced apart from each other along the first direction.

[0009] In some embodiments, the second silicon carbide layer includes a plurality of P-well regions spaced apart from each other along the second direction.

[0010] In some embodiments, a depth of the fourth silicon carbide layer is equal to or less than a depth of the second silicon carbide layer.

[0011] In some embodiments, a pitch between fourth portions of the fourth silicon carbide layer is equal to or smaller than a pitch between P-well regions of the second silicon carbide layer.

[0012] In some embodiments, a depth of the fourth silicon carbide layer is greater than a depth of the second silicon carbide layer.

[0013] In some embodiments, a pitch between fourth portions of the fourth silicon carbide layer is greater than a pitch between P-well regions of the second silicon carbide layer.

[0014] In some embodiments, the multiple P-wells are doped using multiple, sequential ion implantations at progressively lower energies and lower doses.

[0015] In some embodiments, the third silicon carbide layer includes two N+ regions as third portions, which are respectively disposed on opposite sides of the gate oxide layer.

[0016] In some embodiments, the second silicon carbide layer includes a P-base. The device also includes a plurality of trenches.

[0017] In some embodiments, a depth of the fourth silicon carbide layer is greater than a depth of the plurality of trenches.

[0018] In some embodiments, the third silicon carbide layer includes a P+ region sandwiched between two N+ regions on each of two opposing sides of the gate oxide layer.

[0019] In some embodiments, the third silicon carbide layer includes two N+ regions as a third portion, which are respectively disposed on opposite sides of the gate oxide layer.

[0020] In some embodiments, the gate oxide layer includes a plurality of oxidized portions, each of the oxidized portions being formed in one of the plurality of trenches along a sidewall direction.

[0021] In some embodiments, the P+ portion is doped using multiple sequential ion implantations with a bimodal profile.

[0022] In some embodiments, a width of the fourth silicon carbide layer along the first direction is a minimum width that can be achieved by a device manufacturing process.

[0023] In some embodiments, viewed from a direction perpendicular to the silicon carbide substrate, the fourth portion is in a strip shape, a bamboo joint shape, an I-beam shape, or a dumbbell shape.

[0024] In another aspect of the present invention, a method for producing a silicon carbide MOSFET device is provided, which comprises the following steps: providing a first silicon carbide layer of a first doping type on a silicon carbide substrate, the first silicon carbide layer comprising a first epitaxial layer and a second epitaxial layer; providing a second silicon carbide layer of a second doping type embedded in a top portion of the first silicon carbide layer; providing a third silicon carbide layer of a first doping type embedded in a top portion of the first silicon carbide layer; providing a fourth silicon carbide layer at least partially overlapping the second silicon carbide layer in a direction perpendicular to the silicon carbide substrate; providing a gate oxide layer overlapping the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer; and providing a polysilicon layer in contact with the gate oxide layer as a gate material of the silicon carbide MOSFET. The fourth silicon carbide layer comprises a plurality of fourth portions extending substantially along a second direction perpendicular to the first direction. The first direction and the second direction are parallel to the silicon carbide substrate, respectively. The doping amount of the first silicon carbide layer is lower than the doping amount of the silicon carbide substrate, and the doping amount of the third silicon carbide layer is higher than the doping amount of the first silicon carbide layer. The third silicon carbide layer comprises a plurality of third portions extending substantially along the first direction.

[0025] In some embodiments, the first doping type is N and the second doping type is P. The third silicon carbide layer is an N+ layer, and the third portions of the third silicon carbide layer are spaced apart from each other along the second direction. The fourth silicon carbide layer is a P+ layer, and the fourth portions are P+ portions spaced apart from each other along the first direction.

[0026] In some embodiments, the method further comprises the step of doping the P+ portion using multiple consecutive ion implantations with a bimodal distribution.

[0027] In some embodiments, the method further comprises the steps of implanting a first series of dopants in the first epitaxial layer and implanting a second series of dopants in a second epitaxial layer deposited on the first epitaxial layer.

[0028] Thus, embodiments of the present invention achieve a SiC MOSFET structure with increased MOSFET device robustness, but without occupying a relatively small area of ​​the MOSFET cell used. For example, for a vertical planar MOSFET, the P+ region arranged laterally relative to the N+ region in some embodiments allows sufficient P+ area to protect the gate oxide, but is not placed in a manner that crowds out a significant area of ​​the MOSFET cell. At the same time, the MOSFET device meets channel mobility and threshold voltage targets by carefully selecting the P-well distribution that is critical to the MOSFET channel and junction gate field effect transistor (JFET) effect. On the other hand, some embodiments provide a trench SiC MOSFET in which the same concept of a P+ region perpendicular to the N+ region is applied. The P+ region acts as a shielding layer, allowing protection of the gate oxide near the bottom portion of the trench. The P+ region is directly connected to the source contact, so the performance of the body diode can be greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and further features of the present invention will become apparent from the following description of preferred embodiments, which are provided by way of example only in conjunction with the accompanying drawings, in which:

[0030] Figure 1 An active cell layout of a vertical planar MOSFET device according to a first embodiment of the present invention is shown.

[0031] Figure 2a-2d They are Figure 1 A cross-sectional view of the MOSFET device along lines AA, BB, CC, and DD.

[0032] Figure 3 Shows Figure 1 Definition of certain dimensions in MOSFET devices.

[0033] Figure 4a Shows Figure 1 Doping junction distribution of the P-well in the MOSFET device.

[0034] Figure 4b Shows Figure 1 Doping junction distribution of the P+ region in the MOSFET device.

[0035] Figure 5a A cross section of a vertical planar MOSFET device according to a second embodiment of the present invention is shown.

[0036] Figure 5b Shows the corresponding Figure 5a Doping junction distribution of the P+ region in the MOSFET device.

[0037] Figure 6a-6c Shows the Figure 1 Various modifications to the geometry of the P+ region in the MOSFET device of -5.

[0038] Figure 7 Shows the manufacturing Figure 1 or Figure 5a Flowchart of the main steps in making a MOSFET device.

[0039] Figure 8 An active cell layout of a trench MOSFET device according to a third embodiment of the present invention is shown.

[0040] Figures 9a-9d They are Figure 8 A cross-sectional view of the MOSFET device along lines AA, BB, CC, and DD.

[0041] Fig.10 Shows Figure 8 Doping junction distribution of the P+ region in the MOSFET device.

[0042] Figures 11a-11c Shows the Figure 8 Various modifications to the geometry of the P+ region in MOSFET devices.

[0043] Fig.12 Shows the manufacturing Figure 8 Flowchart of the main steps in making a MOSFET device.

[0044] Fig.13 An active cell layout of a trench MOSFET device according to a fourth embodiment of the present invention is shown.

[0045] Figures 14a-14d They are Fig.13 A cross-sectional view of the MOSFET device along lines AA, BB, CC, and DD.

[0046] Figures 15a-15c Shows the Fig.13 Various modifications to the P+ region geometry in MOSFET devices in FIG.

[0047] Fig.16 Shows the manufacturing Fig.13 Flowchart of the main steps in making a MOSFET device.

[0048] Fig.17 FIG. 5 shows the doping junction distribution of the P+ region in a MOSFET device according to a fifth embodiment of the present invention.

[0049] Fig.18 Shown according to Fig.17 Flowchart of the main steps in manufacturing MOSFET devices with doping junction distribution in FIG.

[0050] In the drawings, like numerals refer to like parts throughout the several embodiments described herein. DETAILED DESCRIPTION

[0051] In the following claims and the foregoing description of the invention, unless the context requires otherwise due to the express language or necessary implication, the word "comprise" or variations such as "including", "having" and the like are used in an inclusive sense to refer to the presence of stated features but not to exclude the presence or addition of further features in various embodiments of the invention.

[0052] As used herein and in the claims, unless otherwise stated, "coupled" or "connected" means electrically coupled or connected, either directly or indirectly, via one or more electrical devices.

[0053] Terms such as "horizontal," "vertical," "upward," "downward," "above," "below," and similar terms used herein are intended to describe the invention in its normal orientation of use and are not intended to limit the invention to any particular orientation.

[0054] When describing the silicon carbide structure of any MOSFET device, the terms "region" and "portion" are used interchangeably, since a region of a MOSFET device that is made of a specific material different from its surroundings can also be said to be a portion made of the specific material.

[0055] First look Figure 1-2d The first embodiment of the present invention is a vertical planar MOSFET device, which Figure 1 The MOSFET device is shown in an active cell layout (i.e., a fully functional MOSFET can be formed by expanding the active cell to the required size and then surrounded by edge terminations). The MOSFET device is configured with a source, gate, and drain that form a vertical silicon pillar (e.g. Figure 2a-2d Specifically, the silicon carbide substrate 30 is configured as Figure 1 The underlying structure and epitaxy of the MOSFET device in . As will be appreciated by those skilled in the art, the silicon carbide substrate 30 is made of a SiC wafer, and in this embodiment the silicon carbide substrate 30 is of N+ type as the first doping type. A metal layer (not shown) is also configured on the bottom side of the silicon carbide substrate 30 as an ohmic contact, which serves as a drain contact for the MOSFET device. On top of the silicon carbide substrate 30, there is an N-type first silicon carbide layer 28, and the first silicon carbide layer 28 serves as an N-drift layer. The first silicon carbide layer 28 has a lower doping amount than the silicon carbide substrate 30, and such relatively lower and higher doping amounts are specified using N- and N+, respectively. As described in Figure 2a and 2c As can be seen in FIG. 1 , in some portions of the MOSFET device, the first silicon carbide layer 28 extends all the way up to the top surface 19 of the SiC structure of the MOSFET device.

[0056] Near the top surface 19, there are a plurality of P-well portions 20, which are configured to together form a second silicon carbide layer of the MOSFET device. The second silicon carbide layer has a second doping type P compared to the first doping type N of the first silicon carbide layer 28 and the silicon carbide substrate 30. The P-well portion 20 in this embodiment is embedded in the top of the first silicon carbide layer 28. Figure 2a As shown, there are two P-well portions 20, which are perpendicular to the silicon carbide substrate 30 and relative to Figure 1The plurality of P-well portions 20 are thus spaced apart from one another in a direction perpendicular to the imaginary plane 18. Each P-well portion 20 is further symmetrical around an N+ portion 24 and surrounds the N+ portion 24, which is also embedded in the top of the first silicon carbide layer (and the top portion of the entire SiC structure). Figure 1 and Figure 2a As shown, there are two N+ portions 24, each having a stripe shape, and the N+ portions 24 together form the third silicon carbide layer of the MOSFET device. The N+ portion 24 has a higher doping amount than the first silicon carbide layer 28, while they are both the same N doping type.

[0057] Both the N+ portion 24 and the P-well portion 20 extend parallel to both the silicon carbide substrate 30 and the virtual plane 18. The two N+ portions 24 are also symmetrical about the virtual plane 18. Figure 2a As best shown in FIG. 1 , the N+ portion 24, the P-well portion 20, and the first silicon carbide layer 28 (in terms of their highest portions) all have top surfaces that are flush with the top surface 19 of the SiC structure of the MOSFET device. In this way, it can be said that the N+ portion 24 and the P-well portion 20 are embedded in the top of the first silicon carbide layer 28 (and the top of the SiC structure). The portion of the first silicon carbide layer 28 between the two P-well portions 20 closest to the virtual plane 18 constitutes a junction FET (JFET) region.

[0058] Above the top surface 19 of the SiC structure of the MOSFET device is a stack of a gate oxide layer, which is a dielectric layer; and a polysilicon layer, which is a conductive layer for forming a gate. The gate oxide layer (not shown) is directly below the polysilicon layer and overlaps the first silicon carbide layer 28, the second silicon carbide layer, and the third silicon carbide layer. The gate terminal is located on top of the source and drain terminals (terminals not shown), and a conductive path connecting the source and drain when the MOSFET device is turned on. Figure 1-2b As shown, there are three gate portions forming the gate terminal, including two partial gate portions 22b and one full gate portion 22a. The center of the full gate portion 22a intersects with the virtual plane 18 and is placed on top of the JFET region and partially covers the N+ portion 24 and two adjacent P-well portions 20. The partial gate portion 22b and the full gate portion 22a are part of the polysilicon layer. The two partial gate portions 22b are part of the gate, and when they extend along the normal direction of the virtual plane 18, they will form a complete gate portion 22a. In fact, it should be noted that Figure 1-2d The layout shown is only a portion of the wafer (but the portion is larger than a cell). Figure 1-2dThe structure of more than one unit cell is shown to indicate how the units are integrated on a single wafer. A person skilled in the art will understand how to obtain the same as described above by extending a portion of the unit cell at each edge (eg, a portion of the gate portion 22b is a portion of the portion of the unit cell). Figure 1-2d The same (repeated) structure of the cells shown in . Figure 1 As can be seen in FIG. 1 , all three gate portions 22 a , 22 b extend in a direction extending parallel to the virtual plane 18 .

[0059] Figure 1 The region (portion) extending parallel to the virtual plane 18 in the SiC structure of the MOSFET device has been described above, but there are other portions extending in a direction perpendicular to the virtual plane 18 and parallel to the silicon carbide substrate 30. In particular, as Figure 1 and Figure 2b As can be seen in FIG. 1 , there are two P+ portions 32, which serve as both body diode contacts and P+ sinkers, and the P+ portions 32 extend perpendicularly to the N+ portions 24 and the P-well portion 20. Figure 2b As shown, the junction depth of the P+ portion 32 is slightly less than the junction depth of the P-well portion 20, although in other embodiments they may be equal or deeper. Figure 1 As best shown, the P+ portion 32 is along Figure 2a-2d In the vertical direction of FIG. 1 , the P+ portions 32 overlap with the P-well portion 20, the N+ portion 24 and a portion of the first silicon carbide layer 28 (as an N-drift layer). The plurality of P+ portions 32 together form a fourth silicon carbide layer of the MOSFET device.

[0060] It should be noted that in Figure 1-2d In the figure, the metal terminals of the MOSFET device are not shown. As understood by those skilled in the art, the metal terminals are formed by conductive materials deposited on the gate portions 22a and 22b, the lower side of the silicon carbide substrate 30, and the source region 26 formed by the N+ portion 24 to form a gate terminal, a drain terminal, and a source terminal, respectively. Examples of such conductive materials include titanium (Ti), nickel (Ni), titanium nitride (TiN), titanium aluminum (TiAl), platinum (Pt), aluminum (Al), etc.

[0061] Now refer to Figure 3 explain Figure 1 The two P+ portions 32 described above extend in a direction perpendicular to the gate portion 22a, the P-well portion 20, and the N+ portion 24. Each P+ portion 32 has a Figure 3The width W shown, and the spacing S between the two P+ portions 32. The width W of each P+ portion 32 should be the minimum size that the MOSFET device manufacturing process can allow, which is limited by the photolithography resolution and etching process to open a window for P+ doping by ion implantation. In this embodiment, the width W is 1 μm. The spacing S between the two P+ portions 32 depends on two parameters, namely, the junction depth D1 of the P+ portion 32 (see Figure 2b ) and P-well spacing J (see Figure 3 In order to obtain the best performance of the MOSFET device, the depletion region 34 of the JFET region is parallel to the MOSFET channel caused by the P-well portion 20 (see Figure 2a and 2c ) should also be perpendicular to the MOSFET channel caused by the P+ portion 32. In this embodiment, since the junction depth D1 of the P+ portion 32 is equal to or less than the junction depth P of the P-well portion 20 (see Figure 2a ), the spacing S between the two P+ parts 32 should be equal to or less than the P-well spacing J. Figure 1-3 In a specific implementation of the MOSFET device, the junction depth P of the P-well portion 20 is 1.5 μm, and the P-well spacing J is 1.8 μm. The junction depth D corresponding to the P+ portion 32 is 1.2 μm, and the spacing S between the two P+ portions 32 is 1.45 μm.

[0062] exist Figure 1-3 In another specific embodiment of the MOSFET device, the silicon carbide substrate 30 is an N+ doped 4H-SiC, 3C-SiC or 6H-SiC semiconductor layer with a thickness of about 350 μm and a resistivity of 0.02 Ω·cm to 0.03 Ω·cm. The first silicon carbide layer 28 is an N-epitaxial layer with a thickness ranging from 4 μm to 35 μm and a doping concentration ranging from 1e15 cm -3 to 3e16cm -3 The P-well portion 20 contains aluminum dopants, and the junction depth is in the range of 1 μm to 1.75 μm. The surface doping concentration of the P-well portion 20 is 1e17 cm -3 To 5e18cm -3 The peak doping level is in the range of 1e18 cm -3 To 5e18cm -3 The P+ portion 32 contains aluminum dopants with a doping concentration of 5e19cm -3 to 2e20cm -3 The peak doping amount near the top surface is 2e20cm -3 The peak doping level near the bottom of the P+ portion 32 is 8e19cm -3The N+ portion 24 contains nitrogen or phosphorus dopants, with a junction depth in the range of 0.2 μm to 0.5 μm and a doping concentration of 1e20 cm -3 to 1.5e20cm -3 The gate portions 22a and 22b are silicon dioxide stacks with a thickness in the range of 20nm to 70nm and a thickness in the range of 400nm to 800nm ​​below the gate polysilicon with an in-situ doping amount.

[0063] Next, we will refer to Figure 4a-4b describe Figure 1-3 The doping amount distribution of the P-well portion 20 and the P+ portion 32 in the MOSFET device in FIG. The distribution of the P-well portion 20 is critical to the MOSFET channel and JFET effect of the MOSFET device. Figure 2a The doping concentration of the P-well portion 20 (near the top surface 19 in the P-well portion 20) forms the MOSFET channel and determines parameters such as threshold voltage and channel mobility. The junction depth P of the P-well portion 20 and the doping concentration at the bottom of the P-well portion 20 determine the efficiency of the body diode and the depletion of the JFET region. In this embodiment, the P-well portion 20 is designed to be slightly retrograde to achieve MOSFET and JFET performance targets. To this end, dopants (such as aluminum ions) are implanted into the first silicon carbide layer 28 using a patterned hard mask. The implantation is a series of typically 3 to 6 steps, using different doses and energies to achieve the desired distribution. Figure 4a In the specific implementation shown, the P-well doping consists of five consecutive ion implantations, namely PW1, PW2, PW3, PW4 and PW5. As shown, PW1 corresponds to the ion implantation with the highest energy and highest dose, thus resulting in a retrograde doping profile. PW2, PW3 and PW4 are ion implantations with gradually decreasing energy and dose, so that each junction profile overlaps smoothly. PW5 is an ion implantation in which the energy and dose are adjusted to meet the channel mobility and threshold voltage targets.

[0064] Go to Figure 4b As previously mentioned in Figure 1-3 As mentioned in the embodiment of FIG. 1 , the junction depth D1 of the P+ portion 32 is designed to be less than or equal to the junction depth P of the P-well portion 20. The smaller junction depth allows the use of the same or thinner hard mask thickness as the P-well implant. It is critical to maintain good control of the critical dimensions (width and spacing) of the P+ portion 32. Figure 4b As shown, the doping amount of the P+ portion 32 shows a bimodal distribution. Figure 2aThe P+ portion 32 near the top surface 19 is highly doped to form an ohmic contact. The doping concentration at the bottom of the P+ portion 32 is also highly doped to improve the efficiency of the body diode. Dopants (such as aluminum ions) are implanted into the first silicon carbide layer 28 using a patterned hard mask. The implantation is a series of steps, typically 3 to 6, using different doses and energies to achieve the desired profile. Figure 4b In the specific embodiment shown, the P+ region doping amount consists of 5 ion implantations, namely PP1, PP2, PP3, PP4 and PP5. As shown in the figure, PP1 corresponds to the ion implantation with the highest energy, so it results in the deepest projection range. PP2 and PP3 are ion implantations with gradually decreasing energy and dose, so that each junction distribution overlaps smoothly. To achieve ohmic contact, PP4 and PP5 are ion implantations with higher doses when the implantation energy is lower.

[0065] refer to Figure 5a-5b , now describe the second embodiment of the present invention, which is similar to Figure 1-4b The device in the figure is SiC MOSFET. Figure 5a Most of the characteristics of MOSFET devices are similar to Figure 1-4b The features of the silicon carbide diode array in are similar, so for the sake of brevity, they will not be described here. Figure 5a-5b and Figure 1-4b In particular, the difference between the MOSFET devices in Figure 1-4b The embodiment in the embodiment is different in that the junction depth D1 of the P+ portion is designed to be less than or equal to the junction depth P of the P-well portion. Figure 5a-5b In the embodiment of the present invention, the junction depth D2 of the P+ portion 132 extends to pass through the junction depth P of the P-well portion 120. In other words, the junction depth D2 of the P+ portion 132 is greater than the junction depth of the P-well portion 120. At the same time, in the present embodiment, the spacing S between the P+ portions 132 of the fourth silicon carbide layer is greater than the spacing J of the P-well portion 120 of the second silicon carbide layer (the definitions of S, J, and W are the same as above). This further improves the performance of the body diode and allows a larger P+ portion spacing to width ratio to achieve a higher channel density in the MOSFET cell. Figure 5a-5b In a specific implementation of the MOSFET device, the junction depth P of the P-well portion 320 is 1.5 μm, and the P-well pitch J is 1.8 μm. The junction depth D2 corresponding to the P+ portion 132 is 1.8 μm, and the pitch S between the two P+ portions 132 is 2.16 μm.

[0066] Similar to the P+ portion 32, Figure 5b The doping amount of the P+ portion 132 shown in FIG. 1 also shows a bimodal distribution. Figure 5aThe P+ portion 132 near the top surface 119 is highly doped to form an ohmic contact. The doping concentration at the bottom of the P+ portion 132 is also highly doped to improve the efficiency of the body diode. Dopants (e.g., aluminum ions) are implanted into the first silicon carbide layer 128 using a patterned hard mask. The implantation is a series of steps, typically 3 to 6, using different doses and energies to achieve the desired profile. Figure 5b In the specific implementation shown, the P+ region doping is composed of 5 ion implantations, namely PQ1, PQ2, PQ3, PQ4 and PQ5. As shown in the figure, PQ1 corresponds to the ion implantation with the highest energy, so it results in the deepest projection range. PQ2 and PQ3 are ion implantations with gradually decreasing energy and dose, so that each junction distribution overlaps smoothly. In order to achieve ohmic contact, PQ4 and PQ5 are ion implantations, and the dose will be higher when the implantation energy is lower.

[0067] Next, Figure 6a-6c A variation of the active cell layout of the above embodiment is shown, where the geometry of the P+ portion is changed. For simplicity, the gate portion is not shown. The geometry of the P+ portion can be changed to balance parameters such as body diode performance, MOSFET channel density, etc. to protect the gate oxide from electric fields. Figure 1-5b The embodiment in uses a strip-shaped P+ portion, but it is not the only possible geometry that can be used. Figure 6a In the embodiment, the P+ portion 232 has an I-shape in a top view. Figure 6b In FIG. 1 , the P+ portion 332 has a dumbbell shape in a top view. Figure 6c , the P+ portions 432 each have a bamboo-node shape.

[0068] Figure 7 Shows how to produce Figure 1-5b. Note that the exemplary method described in this embodiment is not intended to be limiting, as other methods and / or different orders of steps may be used to produce the same MOSFET device. The method begins at step 140, in which a raw silicon carbide epitaxial wafer that has been cleaned using an RCA cleaning procedure is prepared. The wafer has an N+ type silicon carbide substrate and an N-type first silicon carbide layer on top of it. It should be noted that the entire wafer will be processed into multiple MOSFET devices before the wafer is cut into individual chips of MOSFET devices. As previously described, the first silicon carbide layer is an epitaxial N-drift layer that is less doped than the silicon carbide substrate. Then, in step 142, a first hard mask (e.g., a dielectric mask such as SiO2) is applied to the first silicon carbide layer. The hard mask process can be accomplished, for example, by plasma enhanced chemical vapor deposition (PECVD) using tetraethyl orthosilicate (TEOS) on the wafer, particularly on the top side of the first silicon carbide layer, thereby forming an oxide layer on the wafer surface. The oxide hard mask layer is then patterned (not shown) by conventional lithography such as optical, ion and electron beam lithography and oxide etching processes to expose portions of the first silicon carbide layer that are to be formed as P+ portions. Figure 4b or Figure 5b A series of P+ ion implantations are performed from the top surface of the first silicon carbide layer in the manner shown to form the P+ portion. In step 146, the first hard mask is removed and then a second hard mask is deposited on the first silicon carbide layer using the same process as the first hard mask. The thickness of the second hard mask can be the same as or different from the first hard mask, but the second hard mask must be thick enough to absorb ions at the masked locations. In step 148, the second hard mask is patterned to expose the portion of the first silicon carbide layer that will be formed as the P-well portion. In step 150, as shown in FIG. Figure 4aA series of P-ion implantations are performed as shown to make a P-well portion in the first silicon carbide layer. In step 152, a sidewall oxide is deposited on the second hard mask and the first silicon carbide layer, and then etched back to form a sidewall oxide portion and expose the N+ portion. In step 154, N+ ion implantation is performed on the top surface of the first silicon carbide layer to form an N+ portion to be used as a source region. N+ ion implantation can counter-dope the P-well portion, but cannot counter-dope the P+ portion. Next, in step 156, the second hard mask is removed and a carbon capping layer is deposited on the top surface of the SiC structure. This carbon capping layer is necessary to minimize the surface roughness caused by the high temperature annealing process. In step 158, the carbon capping layer is prepared, and the entire SiC structure is then subjected to thermal annealing and activation. In step 160, after the top surface of the SiC structure is completely cleaned, a gate oxide is deposited, followed by a post-oxidation anneal. In step 162, doped polysilicon is deposited on top of the gate oxide portion to form a MOSFET gate. In step 164, an interlayer dielectric (ILD) is deposited on top of the entire MOSFET device. The ILD is then patterned on the top surface of a portion of the first silicon carbide layer by photolithography and etching processes, leaving contacts for the ohmic metal later. In step 166, a layer of ohmic metal is deposited on the entire MOSFET device, the ohmic metal is filled in the aforementioned contacts, and then an annealing process is performed. This forms the ohmic contact of the MOSFET device. In step 168, a barrier metal layer is formed on top of the ohmic metal, and in step 170, a layer of power metal is deposited and patterned on top of the barrier metal layer. In step 172, a passivation layer is deposited and patterned on top of the power metal. In step 174, the back side of the silicon carbide substrate is grounded to a desired thickness. Finally, in step 176, a back metal layer is deposited on the back side of the silicon carbide substrate to form a drain contact for the MOSFET device. At this point, the manufacture of the MOSFET device is complete.

[0069] Figure 8-9d FIG. 4 shows a trench SiC MOSFET device according to another embodiment of the present invention. Figure 1-5b Similar to the MOSFET device in Figure 8-9d For the MOSFET device in FIG. 1 , the same concept of the P+ portion placed vertically with the N+ portion is applied, but Figure 8-9d The P+ section is used in trench MOSFET devices. The P+ section acts as a shield to allow protection of the gate oxide near the bottom of the trench. The P+ section is directly connected to the source contact and can therefore greatly improve the performance of the body diode.

[0070] Specifically, the trench MOSFET device arranges the source, channel and drain, which vertically form a silicon pillar (such as Figures 9a-9dIn particular, the silicon carbide substrate 530 is configured as Figure 9a The underlying structure and epitaxy of the MOSFET device in the embodiment. In this embodiment, the silicon carbide substrate 530 is of N+ type as the first doping type. A metal layer (not shown) is also formed on the bottom side of the silicon carbide substrate 530 as an ohmic contact to serve as a drain contact of the MOSFET device. On the top of the silicon carbide substrate 530, there is an N-type first silicon carbide layer 528, and the first silicon carbide layer 528 serves as an N-drift layer. The first silicon carbide layer 528 has a lower doping amount than the silicon carbide substrate 530 and such relatively low doping amount and relatively high doping amount are specified using N- and N+, respectively. Figure 1-5b Unlike the embodiment in FIG. 5 , the first silicon carbide layer 528 does not extend all the way up to the top surface 519 of the SiC structure of the MOSFET device.

[0071] Two P-base portions 521 are arranged on top of the first silicon carbide layer 528, which together form a second silicon carbide layer. Both P-base portions 521 have a strip shape and contain P-type dopants. The two P-base portions 521 are symmetrical with respect to a central virtual plane 518 perpendicular to the silicon carbide substrate 530. A trench gate formed by a gate polysilicon portion 522a encapsulated (except for the top surface) by a trench gate oxide 535 and a trench bottom oxide 538 is arranged between the two P-base portions 521. It should be noted that the trench gate oxide 535 and the trench bottom oxide 538 are made of the same material, but the manufacturing process and steps are different (described in detail later). They also refer to oxides of different thicknesses at different surfaces of the encapsulated gate polysilicon portion 522a. In addition, on the side of each P-base portion 521 away from the virtual plane 518, there is a partial trench gate structure. Each partial trench gate on the side includes a gate polysilicon portion 522b encapsulated by a trench gate oxide 535 and a trench bottom oxide 538. Figure 9a In the embodiment, when the partial trench gate extends in a direction perpendicular to the central virtual plane 518, a full trench gate will be formed.

[0072] Two N+ portions 524 separated by a first P+ portion 536 (which are P+ source junctions) are arranged on top of each P-base portion 521, and all of these N+ portions have a strip shape. The two N+ portions 524 are of equal width and are arranged on opposite sides of the trench gate oxide 535. The N+ portion 524 forms a third silicon carbide layer. The N+ portion 524, the first P+ portion 536 and the trench are all parallel to each other and extend in a direction parallel to the virtual plane 518 and the silicon carbide substrate 530. In addition, there are two second P+ portions 532 extending in a direction transverse to the N+ portion 524, the first P+ portion 536 and the trench, and the second P+ portion 532 forms a fourth silicon carbide layer. Figure 9a As best shown, the N+ portion 524, the first P+ portion 536, and the trench all have top surfaces that are flush with the top surface 519 of the SiC structure of the MOSFET device. It can be said that the N+ portion 524, the first P+ portion 536, and the trench are all embedded on top of the first silicon carbide layer 528.

[0073] In the trench of the MOSFET device, the thickness of the trench bottom oxide 538 can be the same as the thickness of the trench gate oxide 535, but can also be thicker than the thickness of the trench gate oxide 535 to provide more protection. If there is a thicker oxide at the bottom of the trench, the second P+ portion 532 (see Fig.9c The depth D3 of the second P+ portion 532 may be shallower or deeper than the total depth of the trench T (see Figure 9a ). If there is no thicker oxide at the bottom of the trench, the second P+ portion 532 needs to be deeper than the trench to provide effective shielding. Figure 8-9d In the illustrated embodiment, the thickness of the trench bottom oxide 538 is 150 nm, while the thickness of the trench gate oxide 535 is 50 nm.

[0074] Figure 9a and 9c The depletion region 534 of the trench MOSFET device is shown respectively. Figure 9a In FIG. 5 , a cross section of a MOSFET device is shown along a direction perpendicular to the trench, and it can be seen that the depletion region 534 has a flat shape, delimited by two parallel dashed lines, indicating that the trench gate oxide 535 is protected. Fig.9c FIG. 4 shows a cross section of the MOSFET device along a direction parallel to the trench, where it can be seen that the depletion region 534 has an uneven shape, which is defined by the bottom end of the second P+ region 532 .

[0075] Figure 8 The width W of the second P+ portion 532 shown in FIG. 5 has similar design constraints as those mentioned in the previous embodiments, and specifically W should be the minimum dimension that the manufacturing process of the trench MOSFET device can produce. Figure 8-9d In the illustrated embodiment, as described above, the junction depth D3 of the second P+ portion 532 is greater than the trench depth T to ensure that the trench gate oxide 535 is protected by the overlap of the depletion layer from the edge of the P-base portion 521 to the bottom of the trench. The level of protection depends on several factors, namely the doping concentration of the first silicon carbide layer 528, the trench spacing J between the trenches (see Figure 8 ) and the difference between D3 and T (D3-T). In this embodiment, the N-drift doping concentration of the first silicon carbide layer 528 is 1.0e16 / cm 3 , the trench junction depth T is 1.5 μm, the trench pitch J is 1.6 μm, the junction depth D3 of the second P+ portion 532 is 1.8 μm, and the pitch S of the second P+ portion 532 is 1.8 μm.

[0076] exist Figure 8-9d In another specific implementation of the MOSFET device, the silicon carbide substrate 530 is an N+ doped 4H-SiC, 3C-SiC or 6H-SiC semiconductor layer with a thickness of about 350 μm and a resistivity of 0.02 Ω·cm to 0.03 Ω·cm. The first silicon carbide layer 528 is an N-epitaxial layer with a thickness ranging from 4 μm to 35 μm and a doping concentration ranging from 1e15 cm -3 to 3e16cm -3 The P-base portion 521 contains aluminum dopants with a junction depth in the range of 0.6 μm to 1.2 μm and a doping concentration of 1e17 cm -3 To 5e18cm -3 The second P+ portion 532 includes an aluminum dopant with a doping concentration of 5e19cm -3 to 2e20cm -3 The peak doping amount near the top surface is 2e20cm -3 The peak doping level near the bottom of the second P+ portion 532 is 8e19cm -3 The N+ portion 524 contains nitrogen or phosphorus dopants, with a junction depth in the range of 0.2 μm to 0.5 μm and a doping concentration of 1e20 cm -3 to 1.5e20cm -3 The first P+ portion 536 includes an aluminum dopant with a doping concentration in the range of 5e19cm -3 to 2e20cm -3, the junction depth ranges from 0.2 μm to 0.5 μm. The width of each trench is in the range of 0.5 μm to 1.2 μm, and the depth T is in the range of 1.0 μm to 1.8 μm, preferably 1.5 μm. The trench gate oxide 535 is silicon dioxide with a thickness in the range of 20 nm to 70 nm. The trench bottom oxide 538 is silicon dioxide with a thickness in the range of 100 nm to 400 nm. Finally, the conductive material applied on the gate polysilicon portions 522a and 522b is polysilicon with in-situ doping to fill the trenches.

[0077] It should be noted that in Figure 8-9d In the figure, the metal terminals of the MOSFET device are not shown, but as understood by those skilled in the art, the metal terminals are formed by conductive materials deposited on the gate polysilicon portions 522a and 522b, the lower side of the silicon carbide substrate 530, and above the source region 626 formed by the N+ portion 524 and the first P+ portion 536 to form a gate terminal, a drain terminal, and a source terminal, respectively.

[0078] Steering Fig.10 , which shows the doping profile of the second P+ portion 532. The junction depth D3 of the second P+ portion 532 is designed to be greater than the trench depth T. This is to ensure that the hard mask is thick enough to block ion implantation in non-P+ regions. This requires the lithography and etching processes to provide a high enough resolution to obtain the required geometry. The doping of the second P+ portion 532 shows a bimodal distribution. The surface (i.e., Figure 9a The second P+ portion 532 near the top surface 519 is highly doped to form an ohmic contact. The doping concentration at the bottom of the second P+ portion 532 is also highly doped to improve the efficiency of the body diode. Dopants (e.g., aluminum ions) are implanted into the first silicon carbide layer 528 using a patterned hard mask. The implantation is a series of steps, typically 3 to 6, using different doses and energies to achieve the desired profile. Fig.10 In the specific implementation shown, the P+ region doping consists of five consecutive ion implantations, namely PR1, PR2, PR3, PR4 and PR5. As shown in the figure, PP1 corresponds to the highest energy ion implantation, so it results in the deepest projection range. PR2 and PR3 are ion implantations with gradually decreasing energy and dose, so that each junction distribution overlaps smoothly. In order to achieve ohmic contact, PR4 and PR5 are ion implantations, and the dose increases when the implant energy decreases.

[0079] Next, Figures 11a-11c Shown above Figure 8-9dA variation of the embodiment in which the geometry of the second P+ portion is changed. The geometry of the second P+ portion 532 can be changed to balance parameters such as body diode performance, MOSFET channel density, and protection of the trench gate oxide 535 from electric fields. Figure 8-9d The embodiment in FIG. 5 uses a stripe-shaped second P+ portion 532, but it is not the only possible geometry that can be used. Fig.11a In the embodiment, the second P+ portion 632 has an I-shape in a top view. Fig.11b In FIG. 1 , the second P+ portion 732 has a dumbbell shape in a top view. Fig.11c In the figure, the second P+ portions 832 all have a bamboo-joint shape.

[0080] Fig.12 Shows how to produce Figure 8-9d An exemplary method for a trench MOSFET device in is provided. Note that the exemplary method described in this embodiment is not intended to be limiting, as other methods and / or different orders of steps may be used to produce the same MOSFET device. The method begins at step 540, in which a raw silicon carbide epitaxial wafer that has been cleaned using an RCA cleaning procedure is prepared. The wafer has an N+ type silicon carbide substrate and an N-type first silicon carbide layer on top of it. As previously described, the first silicon carbide layer is an epitaxial N-drift layer that is less doped than the silicon carbide substrate. Then, in step 542, a first hard mask (e.g., a dielectric mask such as SiO2) is applied to the first silicon carbide layer. The hard mask process can be accomplished, for example, by plasma enhanced chemical vapor deposition (PECVD) using tetraethyl orthosilicate (TEOS) on the wafer, particularly on the top side of the first silicon carbide layer, thereby forming a layer of oxide on the wafer surface. The oxide hard mask layer is then patterned (not shown) by conventional photolithography such as optical, ion and electron beam lithography and oxide etching processes to expose portions of the first silicon carbide layer that will be formed as the second P+ portion. Fig.10A series of P+ ion implantations are performed from the top surface of the first silicon carbide layer in the manner shown to form a second P+ portion. In step 546, the first hard mask is removed and then a second hard mask is deposited on the first silicon carbide layer using the same process as the first hard mask. The thickness of the second hard mask can be the same or different from the first hard mask, but the second hard mask must be thick enough to absorb ions at the mask position. In step 548, the second hard mask is patterned to expose the portion of the first silicon carbide layer that will be formed as the P-base portion. In step 550, a series of P- ion implantations are performed to make a P-base layer in the first silicon carbide layer. In step 552, the second hard mask is removed and a third hard mask is deposited on the first silicon carbide layer using the same process as the first hard mask. The thickness of the third hard mask can be the same or different from the previous hard mask, but the third hard mask must be thick enough to absorb ions at the masking site. In step 554, the third hard mask is patterned to expose the portion of the first silicon carbide layer that will be formed as the N+ portion. In step 556, N+ source ion implantation is performed on the top surface of the first silicon carbide layer to form an N+ layer that will be used as a source region together with the first P+ portion. The N+ ion implantation can counter-dope the P-base portion, but cannot counter-dope the second P+ portion. Next, in step 558, the third hard mask is removed and the next fourth hard mask is deposited on the first silicon carbide layer using the same process as the first hard mask. The thickness of the fourth hard mask can be the same or different from the previous hard mask, but the fourth hard mask must be thick enough to absorb ions at the mask position. In step 560, the fourth hard mask is patterned to expose the portion of the first silicon carbide layer that will be formed as the first P+ portion. In step 562, P+ source ion implantation is performed on the top surface of the first silicon carbide layer to form the first P+ portion that will be used as a source region together with the N+ portion. The first P+ portion must not overlap with the N+ portion, but may choose to overlap or not overlap with the second P+ portion. In step 564, the fourth hard mask is removed and a carbon capping layer is deposited on the top surface of the SiC structure. In step 566, after the carbon capping layer is prepared, the entire SiC structure then undergoes thermal annealing and activation. In step 568, a fifth hard mask is deposited on the first silicon carbide layer using the same process as the first hard mask. The thickness of the fifth hard mask can be the same or different than the previous hard mask, but the fifth hard mask must be thick enough to maintain good sidewall distribution during trench etching. The hard mask is then patterned to expose portions of the first silicon carbide layer that will be formed into trenches. Next, in step 570, the trenches are etched to their target depths. Note that, as Figures 9a-9dAs shown, the trench will invade the N+ layer and the P-base layer, thereby forming a separated N+ part and a P-base part. In step 572, a vesicular oxide is immediately deposited and removed to remove the trench etching defects and smooth the surface of the trench sidewall. Then the bottom oxide is deposited into the trench. The bottom oxidation process can be completed by high-density plasma chemical vapor deposition (HDPCVD), for example. This process results in a thicker oxide at the bottom of the trench and a thinner oxide at the trench sidewall. In step 574, the oxide is etched back to remove the sidewalls and retain the oxide only at the bottom of the trench, and in step 576, a gate oxide is grown at the trench sidewall, followed by post-oxidation annealing. In step 578, doped polysilicon is deposited to cover the trench bottom oxide and the trench gate oxide portion to form a MOSFET gate. In step 580, an ILD is deposited on top of the entire MOSFET. The ILD is then patterned on the top surface of the portion of the first silicon carbide layer by photolithography and etching processes, leaving a contact for the ohmic metal later. In step 582, a layer of ohmic metal is deposited on the entire MOSFET device, the ohmic metal is filled in the aforementioned contact, and then an annealing process is performed. This forms the ohmic contact of the MOSFET device. In step 584, a barrier metal layer is formed on the top of the ohmic metal, and in step 586, a layer of power metal is deposited and patterned on the top of the barrier metal layer. In step 588, a passivation layer is deposited and patterned on the top of the power metal. In step 590, the back side of the silicon carbide substrate is grounded to the desired thickness. Finally, in step 592, a back metal layer is deposited on the back side of the silicon carbide substrate to form the drain contact of the MOSFET device. At this point, the manufacture of the MOSFET device is complete.

[0081] refer to Figure 13-14d Now, another embodiment of the present invention is described, which is similar to Figure 8-9d The embodiment in is also a trench SiC MOSFET device. Figure 13-14d Most of the characteristics of the MOSFET device in Figure 8-9d The features of the silicon carbide diode array in are similar, so for the sake of brevity, they are not described here. Figure 13-14d and Figure 8-9d In particular, the difference between the MOSFET devices in Figure 8-9d The difference between the embodiment in which the first P+ portion is arranged parallel to the N+ portion is that Figure 13-14d The first P+ portion (ie, the P+ source junction) is removed from the MOSFET device in FIG. 9. In contrast, the N+ portion 924 extends completely between adjacent trenches. Fig.13 The trench pitch J shown is 1.6 μm. Figure 13-14d All other structural, dimensional and design constraints of the MOSFET device are the same as Figure 8-9dThe MOSFET devices in are the same.

[0082] Next, Figures 15a-15c Shown above Figure 13-14d A variation of the embodiment in which the geometry of the second P+ portion 932 is changed. The geometry of the second P+ portion 932 can be changed to balance parameters such as body diode performance, MOSFET channel density, and protection of the gate oxide from electric fields. Figure 13-14d The embodiment in FIG. 1 uses a stripe-shaped second P+ portion 932, but it is not the only possible geometry that can be used. Fig.15a In the embodiment, the second P+ portion 1032 has an I-shape in a top view. Fig.15b In the embodiment, the second P+ portion 1132 has a dumbbell shape in a top view. Fig.15c In the embodiment, the second P+ portions 1232 all have a bamboo-joint shape.

[0083] Fig.16 Shows how to produce Figure 13-14d An exemplary method for a trench MOSFET device in is provided. Note that the exemplary method described in this embodiment is not intended to be limiting, as other methods and / or different orders of steps may be used to produce the same MOSFET device. The method begins at step 940, in which a raw silicon carbide epitaxial wafer that has been cleaned using an RCA cleaning procedure is prepared. The wafer has an N+ type silicon carbide substrate and an N-type first silicon carbide layer on top thereof. As previously described, the first silicon carbide layer is an epitaxial N-drift layer with a lesser doping amount than the silicon carbide substrate. Then, in step 942, a first hard mask (e.g., a dielectric mask such as SiO2) is applied to the first silicon carbide layer. For example, the hard mask process can be accomplished by using tetraethyl orthosilicate (TEOS) on the wafer, particularly on the top side of the first silicon carbide layer, by plasma enhanced chemical vapor deposition (PECVD), thereby forming a layer of oxide on the surface of the wafer. The oxide hard mask layer is then patterned (not shown) by conventional lithography such as optical, ion and electron beam lithography and oxide etching processes to expose portions of the first silicon carbide layer that will be formed as the second P+ portion. Fig.10A series of P+ region ion implantations are performed from the top surface of the first silicon carbide layer in the manner shown to form a second P+ portion. In step 946, the first hard mask is removed, and then a second hard mask is deposited on the first silicon carbide layer using the same process as the first hard mask. The thickness of the second hard mask can be the same or different from the first hard mask, but the second hard mask must be thick enough to absorb ions at the mask position. In step 948, the second hard mask is patterned to expose the portion of the first silicon carbide layer that will be formed as the P-base portion. In step 950, a series of P-base ion implantations are performed to form a P-base layer in the first silicon carbide layer. In step 952, the second hard mask is removed, and the next third hard mask is deposited on the first silicon carbide layer using the same process as the first hard mask. The thickness of the third hard mask can be the same or different from the previous hard mask, but the third hard mask must be thick enough to absorb ions at the masking site. In step 954, the third hard mask is patterned to expose portions of the first silicon carbide layer that are to be formed as N+ portions. In step 956, N+ source ion implantation is performed on the top surface of the first silicon carbide layer to form an N+ layer that is to be used as a source region. The N+ ion implantation can counter-dope the P-base portion, but cannot counter-dope the second P+ portion. Next, in step 958, the third hard mask is removed and a carbon capping layer is deposited on the top surface of the SiC structure. In step 960, after the carbon capping layer is prepared, the entire SiC structure is then thermally annealed and activated. In step 962, a fourth hard mask is deposited on the first silicon carbide layer using the same process as the first hard mask. The thickness of the fourth hard mask can be the same or different than the previous hard mask, but the fourth hard mask must be thick enough to maintain good sidewall distribution during trench etching. The hard mask is then patterned to expose portions of the first silicon carbide layer that are to be formed into trenches. Next, in step 964, the trenches are etched to their target depths. Note that, as Figures 14a-14dAs shown, the trench will invade the N+ layer and the P-base layer, thereby forming a separated N+ part and a P-base part. In step 966, a vesicular oxide is immediately deposited and etched to remove the trench etching defects and smooth the surface of the trench sidewall. Then the bottom oxide is deposited into the trench. The bottom oxidation process can be completed by high-density plasma chemical vapor deposition (HDPCVD), for example. This process results in a thicker oxide at the bottom of the trench and a thinner oxide at the trench sidewall. In step 968, the oxide is etched back to remove the sidewalls and retain the oxide only at the bottom of the trench, and in step 970, a gate oxide is grown at the trench sidewall, followed by post-oxidation annealing. In step 972, doped polysilicon is deposited to cover the trench bottom oxide and the trench gate oxide portion to form a MOSFET gate. In step 974, an ILD is deposited on top of the entire MOSFET device. Then the ILD is patterned on the top surface of the portion of the first silicon carbide layer by photolithography and etching processes, leaving a contact for the ohmic metal later. In step 976, a layer of ohmic metal is deposited on the entire MOSFET device, the ohmic metal is filled in the aforementioned contact, and then an annealing process is performed. This forms the ohmic contact of the MOSFET device. In step 978, a barrier metal layer is formed on the top of the ohmic metal, and in step 980, a layer of power metal is deposited and patterned on the top of the barrier metal layer. In step 982, a passivation layer is deposited and patterned on the top of the power metal. In step 984, the back side of the silicon carbide substrate is grounded to the desired thickness. Finally, in step 986, a back metal layer is deposited on the back side of the silicon carbide substrate to form the drain contact of the MOSFET device. At this point, the manufacture of the MOSFET device is complete.

[0084] Go to Fig.17 , which illustrates an alternative method for forming a deeper P+ section in a MOSFET device. For SiC structures that require a deep P+ region junction depth, such as Figure 5a , 8 , 9a-9d and 13-14d, an alternative approach can use two separate implant processes to produce a bimodal distribution of P+ region doping. This approach does not require high energy implants nor thick blocking hard masks, which allows the design of pattern geometries to be smaller and more area efficient. Fig.17According to the curve graph in, in order to perform the alternative method, a first series of dopants are typically implanted into the first epitaxial layer using 1 to 3 steps (e.g., aluminum ions) using a patterned hard mask. In this embodiment, the first P+ region doping includes two ion implantations, namely PT1 and PT2. The second epitaxial layer is then deposited on top of the first epitaxial layer. The thickness of the second epitaxial layer ranges from 0.5um to 3um, and the doping concentration is the same as the first epitaxial layer, but it can also be lower or higher than the first epitaxial layer. In order to form a complete doping distribution, a second series of dopants are typically implanted into the second epitaxial layer using a patterned hard mask, typically 2 to 4 steps (e.g., aluminum ions). In this embodiment, the second P+ region doping includes three ion implantations, namely PU1, PU2, and PU3. The second series of dopants must be added to the first series of dopants to provide connection. The patterned hard mask for doping the second P+ region can be the same, smaller, or larger than the patterned hard mask for doping the first P+ region.

[0085] Fig.18 Shows how Fig.17 The method described in Figure 13-14d . Note that the exemplary method described in this embodiment is not intended to be limiting, as the same MOSFET device can be produced using other methods and / or different sequences of steps. The method begins at step 1340, in which a raw silicon carbide epitaxial wafer that has been cleaned using an RCA cleaning procedure is prepared. The wafer has an N+ type silicon carbide substrate and an N-type first epitaxial layer on top of it. Then, in step 1342, a first hard mask (e.g., a dielectric mask such as SiO2) is applied to the first epitaxial layer. For example, the hard mask process can be accomplished by plasma enhanced chemical vapor deposition (PECVD) using tetraethyl orthosilicate (TEOS) on the wafer, particularly on the top side of the first epitaxial layer, to form a layer of oxide on the surface of the wafer. The oxide hard mask layer is then patterned (not shown) by conventional lithography such as optical, ion and electron beam lithography and oxide etching processes to expose the portion of the first epitaxial layer that is to be formed as the lower P+ portion. In step 1344, the first epitaxial layer is formed as shown in FIG. Fig.17 In the manner shown, a series of first P+ region ion implantations are performed from the top surface of the first silicon carbide layer to form a lower P+ portion. In step 1346, the first hard mask is removed, and then in step 1348, a second epitaxial layer is deposited on top of the first epitaxial layer. In step 1350, a second hard mask is deposited on the second epitaxial layer using the same process as the first hard mask. The thickness of the second hard mask can be the same or different than the first hard mask, but the second hard mask must be thick enough to absorb ions at the mask position. The hard mask is then patterned to expose a portion of the second epitaxial layer that will be formed as the upper P+ portion. In step 1352, the second epitaxial layer is patterned as shown. Fig.17A series of second P+ region ion implantations are performed from the top surface of the second epitaxial layer in the manner shown to form the upper P+ portion. In step 1354, the second hard mask is removed and a third hard mask is deposited on the second epitaxial layer using the same process as the first hard mask. The thickness of the third hard mask can be the same or different from the previous hard mask, but the third hard mask must be thick enough to absorb ions at the masked site. In step 1356, the third hard mask is patterned to expose the portion of the second epitaxial layer that will be formed as the P-base portion. In step 1358, a series of P-base ion implantations are performed to form a P-base layer in the second epitaxial layer. In step 1360, the third hard mask is removed and a fourth hard mask is deposited on the second epitaxial layer using the same process as the first hard mask. The thickness of the fourth hard mask can be the same or different from the previous hard mask, but the fourth hard mask must be thick enough to absorb ions at the masked position. In step 1362, the fourth hard mask is patterned to expose the portion of the second epitaxial layer that forms the N+ portion. In step 1364, N+ source ion implantation is performed on the top surface of the second epitaxial layer to form an N+ layer to be used as a source region. The N+ ion implantation can counter-dope the P-base portion, but cannot counter-dope the P+ portion. Next, in step 1366, the fourth hard mask is removed and a carbon capping layer is deposited on the top surface of the SiC structure. In step 1368, the carbon capping layer is prepared, and the entire SiC structure is then subjected to thermal annealing and activation. In step 1370, a fifth hard mask is deposited on the second epitaxial layer using the same process as the first hard mask. The thickness of the fifth hard mask can be the same or different from the previous hard mask, but the fifth hard mask must be thick enough to maintain a good sidewall profile during trench etching. The hard mask is then patterned to expose the portion of the second epitaxial layer that will be formed into the trench. Next, in step 1372, the trenches are etched to their target depths. In step 1374, vesicular oxide is immediately deposited and removed to remove trench etching defects and smooth the surface of the trench sidewalls. Then bottom oxide is deposited into the trench. The bottom oxidation process can be completed by high density plasma chemical vapor deposition (HDPCVD), for example. The process results in thicker oxide at the bottom of the trench and thinner oxide at the trench sidewalls. In step 1376, the oxide is etched back to remove the sidewalls and retain oxide only at the bottom of the trench, and in step 1378, gate oxidation is grown at the trench sidewalls, followed by post-oxidation annealing. In step 1380, doped polysilicon is deposited to cover the trench bottom oxide and trench gate oxide portions to form a MOSFET gate. In step 1382, ILD is deposited on top of the entire MOSFET device. Then ILD is patterned on the top surface of the portion of the first silicon carbide layer by photolithography and etching processes, leaving contacts for ohmic metal later.In step 1384, a layer of ohmic metal is deposited on the entire MOSFET device, the ohmic metal is filled in the contacts mentioned above, and then an annealing process is performed. This forms the ohmic contact of the MOSFET device. In step 1386, a barrier metal layer is formed on the top of the ohmic metal, and in step 1388, a layer of power metal is deposited and patterned on the top of the barrier metal layer. In step 1390, a passivation layer is deposited and patterned on the top of the power metal. In step 1392, the back side of the silicon carbide substrate is grounded to the desired thickness. Finally, in step 1394, a back metal layer is deposited on the back side of the silicon carbide substrate to form the drain contact of the MOSFET device. At this point, the manufacture of the MOSFET device is complete.

[0086] The exemplary embodiments of the present invention are thus fully described. Although the description relates to specific embodiments, it will be clear to those skilled in the art that the present invention can be practiced by changes in these specific details. Therefore, the present invention should not be interpreted as being limited to the embodiments set forth herein.

[0087] Although the present invention is described and illustrated in detail in the accompanying drawings and the foregoing description, it is considered to be illustrative rather than restrictive in nature, and it should be understood that only exemplary embodiments are shown and described and the scope of the present invention is not limited in any way. It is understood that any feature described herein can be used with any embodiment. The illustrative embodiments do not exclude each other or exclude other embodiments not listed herein. Therefore, the present invention also provides an embodiment including one or more combinations of the above-mentioned illustrative embodiments. Without departing from the spirit and scope of the present invention, the present invention can be modified and changed, therefore, only the restrictions shown in the appended claims should be applied.

Claims

1. A silicon carbide MOSFET device, comprising: a) a silicon carbide substrate of a first doping type; b) a first silicon carbide layer of a first doping type located on the silicon carbide substrate, the first silicon carbide layer having a lower doping amount than the silicon carbide substrate and defining a drift region; c) a second silicon carbide layer of a second doping type embedded on top of the first silicon carbide layer; the second silicon carbide layer comprises a plurality of second portions extending substantially along the first direction; d) a third silicon carbide layer of the first doping type embedded in the top of the second silicon carbide layer; the third silicon carbide layer has a higher doping amount than the first silicon carbide layer; the third silicon carbide layer includes a plurality of third portions extending substantially along the first direction; as well as e) a gate oxide layer overlapping the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer, and the gate oxide layer is in contact with the polysilicon layer; The silicon carbide MOSFET device further includes a fourth silicon carbide layer at least partially overlapping the second silicon carbide layer along a direction perpendicular to the silicon carbide substrate; the fourth silicon carbide layer has a higher doping amount than the second silicon carbide layer and includes a plurality of fourth portions; the fourth portion extends substantially along a second direction perpendicular to the first direction; the first direction and the second direction are both parallel to the silicon carbide substrate; The first doping type is N and the second doping type is P; the third silicon carbide layer is an N+ layer, and the third portions of the third silicon carbide layer are spaced apart from each other along the second direction; the fourth silicon carbide layer is a P+ layer, and the fourth portions are P+ portions spaced apart from each other along the first direction; The second silicon carbide layer includes a plurality of P-well regions spaced apart from each other along the second direction.

2. The silicon carbide MOSFET device according to claim 1, wherein: The depth of the fourth silicon carbide layer is equal to or smaller than the depth of the second silicon carbide layer.

3. The silicon carbide MOSFET device according to claim 2, wherein: A pitch between the fourth portions of the fourth silicon carbide layer is equal to or smaller than a pitch between the P-well regions of the second silicon carbide layer.

4. The silicon carbide MOSFET device according to claim 1, wherein: The depth of the fourth silicon carbide layer is greater than the depth of the second silicon carbide layer.

5. The silicon carbide MOSFET device according to claim 4, wherein: A pitch between the fourth portions of the fourth silicon carbide layer is greater than a pitch between the P-well regions of the second silicon carbide layer.

6. The silicon carbide MOSFET device according to claim 1, wherein: The plurality of P-well regions are doped using a plurality of consecutive ion implantations with gradually decreasing energy and decreasing dose.

7. The silicon carbide MOSFET device according to claim 1, wherein: The second silicon carbide layer includes a P-base; the silicon carbide MOSFET device also includes a plurality of trenches, the trenches are embedded in the top of the first silicon carbide layer, and the trenches have a top surface flush with a top surface of the fourth silicon carbide layer.

8. The silicon carbide MOSFET device according to claim 7, wherein: The fourth silicon carbide layer has a depth greater than a depth of the plurality of trenches.

9. The silicon carbide MOSFET device according to claim 7, wherein: The third silicon carbide layer includes a P+ region sandwiched between two N+ regions on each of two opposing sides of the gate oxide layer. 10 . The silicon carbide MOSFET device of claim 7 , wherein the third silicon carbide layer includes two N+ regions on each of two opposite sides of the gate oxide layer and has no P+ region.

11. The silicon carbide MOSFET device according to claim 7, wherein: The gate oxide layer includes a plurality of oxidized portions, each of which is formed in one of the plurality of trenches along a sidewall direction.

12. The silicon carbide MOSFET device according to claim 1, wherein: The width of the fourth silicon carbide layer along the first direction is the minimum width that can be achieved by the manufacturing process of the silicon carbide MOSFET device. 13 . The silicon carbide MOSFET device according to claim 1 , wherein the fourth portion is in a strip shape, a bamboo-joint shape, an I-shape, or a dumbbell shape when viewed from a direction perpendicular to the silicon carbide substrate. 14 . The silicon carbide MOSFET device according to claim 1 , wherein the third silicon carbide layer comprises two N+ regions as third portions, which are respectively disposed on opposite sides of the gate oxide layer.

15. The silicon carbide MOSFET device of claim 1, wherein the P+ portion is doped using multiple consecutive ion implantations with a bimodal distribution.

16. A silicon carbide MOSFET device, comprising: a) a silicon carbide substrate of a first doping type; b) a first silicon carbide layer of a first doping type located on the silicon carbide substrate, the first silicon carbide layer having a lower doping amount than the silicon carbide substrate and defining a drift region; c) a second silicon carbide layer of a second doping type embedded on top of the first silicon carbide layer; the second silicon carbide layer comprises a plurality of second portions extending substantially along the first direction; d) a third silicon carbide layer of the first doping type embedded in the top of the second silicon carbide layer; the third silicon carbide layer has a higher doping amount than the first silicon carbide layer; the third silicon carbide layer includes a plurality of third portions extending substantially along the first direction; as well as e) a gate oxide layer overlapping the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer, and the gate oxide layer is in contact with the polysilicon layer; The silicon carbide MOSFET device further includes a fourth silicon carbide layer at least partially overlapping the second silicon carbide layer along a direction perpendicular to the silicon carbide substrate; the fourth silicon carbide layer has a higher doping amount than the second silicon carbide layer and includes a plurality of fourth portions; the fourth portion extends substantially along a second direction perpendicular to the first direction; the first direction and the second direction are both parallel to the silicon carbide substrate; The first doping type is N and the second doping type is P; the third silicon carbide layer is an N+ layer, and the third portions of the third silicon carbide layer are spaced apart from each other along the second direction; the fourth silicon carbide layer is a P+ layer, and the fourth portions are P+ portions spaced apart from each other along the first direction; The third silicon carbide layer includes two N+ regions as a third part, which are respectively arranged on opposite sides of the gate oxide layer.

17. The silicon carbide MOSFET device according to claim 16, wherein: The second silicon carbide layer includes a P-base; the silicon carbide MOSFET device also includes a plurality of trenches; the trenches are embedded in the top of the first silicon carbide layer, and the trenches have a top surface flush with a top surface of the fourth silicon carbide layer.

18. A silicon carbide MOSFET device, comprising: a) a silicon carbide substrate of a first doping type; b) a first silicon carbide layer of a first doping type located on the silicon carbide substrate, the first silicon carbide layer having a lower doping amount than the silicon carbide substrate and defining a drift region; c) a second silicon carbide layer of a second doping type embedded on top of the first silicon carbide layer; the second silicon carbide layer comprises a plurality of second portions extending substantially along the first direction; d) a third silicon carbide layer of the first doping type embedded in the top of the second silicon carbide layer; the third silicon carbide layer has a higher doping amount than the first silicon carbide layer; the third silicon carbide layer includes a plurality of third portions extending substantially along the first direction; as well as e) a gate oxide layer overlapping the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer, and the gate oxide layer is in contact with the polysilicon layer; The silicon carbide MOSFET device further includes a fourth silicon carbide layer at least partially overlapping the second silicon carbide layer along a direction perpendicular to the silicon carbide substrate; the fourth silicon carbide layer has a higher doping amount than the second silicon carbide layer and includes a plurality of fourth portions; the fourth portion extends substantially along a second direction perpendicular to the first direction; the first direction and the second direction are both parallel to the silicon carbide substrate; The first doping type is N and the second doping type is P; the third silicon carbide layer is an N+ layer, and the third portions of the third silicon carbide layer are spaced apart from each other along the second direction; the fourth silicon carbide layer is a P+ layer, and the fourth portions are P+ portions spaced apart from each other along the first direction; The P+ portion is doped using multiple consecutive ion implantations with a bimodal distribution.

19. A method for producing a silicon carbide MOSFET device, comprising the following steps: a) providing a first silicon carbide layer of a first doping type on a top portion of the silicon carbide substrate; the first silicon carbide layer comprises a first epitaxial layer and a second epitaxial layer, the doping amounts of which are the same or different but both are lower than the doping amount of the silicon carbide substrate; b) providing a second silicon carbide layer of a second doping type embedded on top of said first silicon carbide layer; c) providing a third silicon carbide layer of the first doping type embedded on top of the second silicon carbide layer; the third silicon carbide layer has a higher doping amount than the first silicon carbide layer; the third silicon carbide layer includes a plurality of third portions extending substantially along the first direction; d) providing a gate oxide layer overlapping the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer; And the gate oxide layer is in contact with the polysilicon layer; as well as e) providing a fourth silicon carbide layer at least partially overlapping the second silicon carbide layer in a direction perpendicular to the silicon carbide substrate; The fourth silicon carbide layer has a higher doping amount than the second silicon carbide layer, and includes a plurality of fourth portions; the fourth portions substantially extend along a second direction perpendicular to the first direction; the first direction and the second direction are both parallel to the silicon carbide substrate; The first doping type is N and the second doping type is P; the third silicon carbide layer is an N+ layer, and the third portions of the third silicon carbide layer are spaced apart from each other along the second direction; the fourth silicon carbide layer is a P+ layer, and the fourth portions are P+ portions spaced apart from each other along the first direction; The second silicon carbide layer includes a plurality of P-well regions spaced apart from each other along the second direction.

20. The method according to claim 19, further comprising the steps of: f) multiple times of continuous ion implantation of a first series of dopants on the first epitaxial layer to form a lower P+ portion; g) multiple times of continuous ion implantation of a second series of dopants on a second epitaxial layer deposited on the top portion of the first epitaxial layer to form an upper P+ portion; The second series of dopants are combined with the first series of dopants along the depth direction of the fourth silicon carbide layer to produce a bimodal distribution morphology.

Images