A memory erasing method and device

Abstract

The present invention relates to an erasing device and method for a memory. The erasing device of the memory controls a switch and a leakage current readout circuit, wherein one end of the control switch is connected to a memory cell and the other end is connected to a switch selection signal, and the leakage current readout circuit includes a transimpedance amplifier and a voltage amplifier. The method comprises: repeatedly performing an erasing operation on the memory cell according to the current difference between the current threshold voltage and the initial threshold voltage until the current difference is less than the set difference. The present invention obtains the leakage current value after the erasing operation through the leakage current readout circuit, calculates the threshold voltage of the memory cell after the erasing operation, and thereby determines the electron residue on the floating gate, so as to realize an effective data erasing operation, and improves the reading accuracy under a wide range of input voltages by improving the circuit design, so as to further improve the effectiveness of data erasing.

Description

Technical Field

[0001] The present invention relates to a method and device for erasing a memory, belonging to the technical field of computer storage. Background Art

[0002] The rapid development of storage technology has garnered widespread attention for solid-state storage. Non-volatile memory is often assumed to be irrecoverable after a single erase operation. However, this is not the case, as data retention can occur in non-volatile memory. One of the hallmarks of non-volatile memory is the storage of information in the form of charge. This data is stored in a floating gate, located between a control gate and the substrate, surrounded by an insulating layer. During programming, hot electrons are injected into the floating gate, increasing the number of electrons on the floating gate and storing a "0" value. During erasing, electrons on the floating gate tunnel back to the source, decreasing the number of electrons on the floating gate and storing a "1" value. However, for a given floating gate cell, after a single program and erase operation, the erase operation cannot fully tunnel the electrons injected into the floating gate during programming back to the source, leaving residual information. This is the data retention phenomenon in non-volatile memory.

[0003] Although the data is ultimately read out as "0" or "1" by the sensor circuit without affecting user experience, some electrons fail to return to the source or channel and remain on the floating gate or trapped in the oxide layer, causing the transistor's threshold voltage to change. Cells that have stored different information have different numbers of residual electrons, resulting in different threshold voltages. An attacker can determine the stored information by measuring the threshold voltage. Existing erasure methods pose significant risks, making effectively eliminating residual data in Flash memory a significant challenge. Summary of the Invention

[0004] The present invention provides a memory erasing method and device, aiming to solve at least one of the technical problems existing in the prior art.

[0005] One aspect of the technical solution of the present invention relates to an erasing device for a memory, comprising a control switch and a leakage current readout circuit.

[0006] One end of the control switch is connected to the storage unit, and the other end is connected to the switch selection signal; the leakage current readout circuit includes a transimpedance amplifier and a voltage amplifier; the transimpedance amplifier includes a first operational amplifier and two feedback resistors, the inverting input of the first operational amplifier is connected to the output of the reference floating gate, and the non-inverting input of the first operational amplifier is connected to the output of the current floating gate; the two ends of one of the feedback resistors are respectively connected to the inverting input and non-inverting output of the first operational amplifier, and the two ends of the other feedback resistor are respectively connected to the non-inverting input and inverting output of the first operational amplifier; the voltage amplifier includes a second operational amplifier, a third operational amplifier, two capacitors C1 and two resistors R2; the inverting input of the second operational amplifier is connected to the non-inverting output of the first operational amplifier, and the non-inverting input of the second operational amplifier is connected to the inverting output of the first operational amplifier; the non-inverting output of the second operational amplifier The inverting input terminal of the third op amp is connected to the inverting output terminal of the second op amp and the non-inverting input terminal of the third op amp; the two ends of one capacitor C1 are respectively connected to the inverting input terminal and the non-inverting output terminal of the third op amp, and the two ends of another capacitor C1 are respectively connected to the non-inverting input terminal and the inverting output terminal of the third op amp; the two ends of one resistor R2 are respectively connected to the inverting input terminal of the second op amp and the non-inverting output terminal of the third op amp, and the two ends of another resistor R2 are respectively connected to the non-inverting input terminal of the second op amp and the inverting output terminal of the third op amp; the third op amp outputs the final result; wherein, the two ends of one resistor R1 are respectively connected to the non-inverting output terminal of the first op amp and the inverting input terminal of the second op amp, and the two ends of the other resistor R1 are respectively connected to the inverting output terminal of the first op amp and the non-inverting input terminal of the second op amp.

[0007] Furthermore, the control switch includes an NMOS tube M NH1 、NMOS tube M NH2 、NMOS tube M NH3 , NMOS tube M1, NMOS tube M2 and charge pump circuit; the NMOS tube M NH1 The gate end of the NMOS tube M NH2 The gate terminal and the NMOS tube M NH3 The gate end of the charge pump circuit is connected to the source end of the NMOS tube M1 and the gate end of the NMOS tube M NH1 The source end of the NMOS tube M NH2 The output end of the charge pump circuit is connected to the gate end of the NMOS tube M2, the source end of the NMOS tube M1, the NMOS tube M NH3The source end of the NMOS tube M1 is connected to the gate end of the NMOS tube M2, the drain end of the NMOS tube M1 is connected to the input voltage of the charge pump circuit, the source end of the NMOS tube M2 is connected to the output voltage of the charge pump circuit, and the drain end of the NMOS tube M2 is connected to the output voltage of the charge pump circuit.

[0008] Furthermore, the charge pump circuit is connected to a charge pump control circuit, which includes a first comparator, a second comparator, a third comparator, a fourth comparator and an error amplifier arranged in parallel, wherein the inverting input terminals of the first comparator, the second comparator, the third comparator, the fourth comparator and the error amplifier are connected to the sampling voltage of the charge pump circuit, the non-inverting input terminals of the first comparator, the second comparator and the third comparator are connected to the first reference voltage of the charge pump circuit, the non-inverting input terminal of the error amplifier is connected to the second reference voltage of the charge pump circuit, and the non-inverting input terminal of the fourth comparator is connected to the third reference voltage of the charge pump circuit; the output terminals of the first comparator, the second comparator and the third comparator are connected to the input terminal of the current drive circuit; and the output terminal of the fourth comparator is connected to the sampling voltage of the charge pump circuit. The input end of the OR gate circuit; the output end of the error amplifier is connected to the non-inverting input end of the fifth comparator and the input end S1 of the two-way selector; the inverting input end of the fifth comparator is connected to the first reference voltage, and the output end of the fifth comparator is connected to the other input end of the OR gate circuit and the input end EN of the two-way selector; the output end of the OR gate circuit is connected to the input end of the AND gate circuit; the input end S0 of the two-way selector is connected to the first reference voltage, the output end of the two-way selector is connected to the input end of the voltage-controlled oscillator, and the input end of the voltage-controlled oscillator is connected to the other input end of the AND gate circuit; the output end of the AND gate circuit is connected to the input end of the current driving circuit; the AND gate circuit outputs the clock control signal CLKA of the charge pump, and the current driving circuit outputs the clock control signal CLKB of the charge pump.

[0009] Furthermore, the output end of the charge pump circuit is connected to an output capacitor.

[0010] Furthermore, the current driving circuit includes a first converter, a second converter, a third converter, and a fourth converter arranged in parallel, wherein the input ends of the first converter, the second converter, the third converter, and the fourth converter are connected to the output end of the AND gate circuit, and the first converter, the second converter, the third converter, and the fourth converter output the clock control signal CLKB; the input end of the second converter is connected to the output end of the first comparator, the input end of the third converter is connected to the output end of the second comparator, and the input end of the fourth converter is connected to the output end of the third comparator.

[0011] Furthermore, the transimpedance Z of the transimpedance amplifier OUT_TIA The calculation is as follows:

[0012]

[0013] Where V OUT_TIA represents the output voltage of the transimpedance amplifier, A TIA represents the gain of the first op amp, R FB represents the feedback resistor.

[0014] Furthermore, it also includes a leakage current steering circuit, which includes a fourth op amp, the inverting input terminal of the fourth op amp is connected to the drain terminal of the storage unit, and the non-inverting input terminal of the fourth op amp is connected to the gate terminal of the storage unit.

[0015] Another aspect of the technical solution of the present invention relates to a method for erasing a memory, which is applied to the memory erasing device of the above embodiment. The method according to the present invention comprises the following steps:

[0016] S1: Acquiring the threshold voltage of the memory cell before the erase operation;

[0017] S2: performing an erase operation on the memory cell; wherein the erase operation is any one of data erase and arbitrary sequence overwrite; obtaining a threshold voltage of the memory cell after the erase operation; and obtaining a current difference between the threshold voltage at the current time and the threshold voltage at the previous time;

[0018] S3: Determine whether the current difference values ​​for N consecutive times are all smaller than the set difference value. If not, repeat step S2 until the N current difference values ​​are all smaller than the set difference value.

[0019] Another aspect of the technical solution of the present invention relates to a computer-readable storage medium having program instructions stored thereon, wherein the program instructions implement the above-mentioned method when executed by a processor.

[0020] Another aspect of the technical solution of the present invention relates to a memory erasing device system, comprising: a computer device, wherein the computer device includes the above-mentioned computer-readable storage medium.

[0021] The beneficial effects of the present invention are as follows.

[0022] The leakage current readout circuit captures the leakage current value after an erase operation, inferring the threshold voltage of the memory cell after the erase operation, thereby determining the residual electrons on the floating gate and achieving effective data erase. A transimpedance amplifier and a voltage amplifier are combined to increase the output swing and improve the accuracy of leakage current identification. By adding a control switch, a segmented readout method is implemented, achieving high-precision leakage current reading over a wide range of input voltages. Improvements to the control circuit structure and current drive circuit design facilitate rapid voltage boosting while maintaining a stable, low-ripple state, thereby enabling the charge pump circuit to output a constant voltage value over a wide range of input voltages and improving the overall performance of the control switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 FIG. 4 is a schematic diagram of the circuit structure of a leakage current readout circuit according to an embodiment of the present invention.

[0024] Figure 2 4 is a schematic diagram of the circuit structure of a control switch according to an embodiment of the present invention.

[0025] Figure 3 is a circuit schematic diagram of a charge pump circuit according to an embodiment of the present invention.

[0026] Figure 4 FIG. 4 is a schematic diagram of a circuit structure of a charge pump control circuit according to an embodiment of the present invention.

[0027] Figure 5 4 is a circuit diagram of a first operational amplifier according to an embodiment of the present invention.

[0028] Figure 6 4 is a circuit diagram of a voltage amplifier according to an embodiment of the present invention.

[0029] Figure 7 4 is a circuit schematic diagram of a leakage current steering circuit according to an embodiment of the present invention.

[0030] Figure 8 FIG. 4 is a noise spectral density diagram of a leakage current readout circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following will provide a clear and complete description of the concept, specific structure and technical effects of the present invention in conjunction with the embodiments and drawings to fully understand the purpose, scheme and effects of the present invention.

[0032] It should be noted that, unless otherwise specified, when a feature is referred to as being "fixed" or "connected" to another feature, it may be directly fixed or connected to the other feature, or it may be indirectly fixed or connected to the other feature. The singular forms "a", "said" and "the" used herein are also intended to include the plural forms, unless the context clearly indicates otherwise. In addition, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art. The terms used in this specification are only for describing specific embodiments and are not intended to limit the invention. The term "and / or" used herein includes any combination of one or more related listed items.

[0033] Should be understood that, although the present disclosure may adopt the term first, second, third etc. to describe various elements, these elements should not be limited to these terms.These terms are only used to distinguish the elements of the same type from each other.For example, without departing from the scope of the present disclosure, the first element may also be referred to as the second element, and similarly, the second element may also be referred to as the first element.The use of any and all examples or exemplary language ("for example", "such as" etc.) provided herein is only intended to better illustrate embodiments of the present invention, and unless otherwise required, will not impose limitations on the scope of the present invention.

[0034] Reference Figure 1 The technical solution of the present invention is an erasing device for a memory, comprising an erasing circuit, a control switch and a leakage current reading circuit applied to a memory cell. It should be noted that the erasing circuit of an embodiment of the present invention adopts the existing erasing method of erasing data and overwriting data of the same cell in an arbitrary sequence. One end of the control switch is connected to the memory cell, and the other end is connected to a switch selection signal. The leakage current reading circuit includes a transimpedance amplifier and a voltage amplifier. The leakage current reading circuit is used to read the floating gate leakage current of the memory cell. The scheme of the leakage current reading circuit of the present invention is to first convert the current signal into a smaller differential voltage signal through a transimpedance amplifier, and then amplify it through the subsequent voltage amplifier.

[0035] The transimpedance amplifier (ITA) includes a first op amp and two feedback resistors R FB , the inverting input terminal V1 of the first op amp is connected to the output terminal of the reference floating gate cell (Cell_R), and the non-inverting input terminal V2 of the first op amp is connected to the output terminal of the current floating gate cell (Cell_1); one of the feedback resistors R FB The two ends of the resistor are connected to the inverting input terminal V1 and the non-inverting output terminal V01 of the first op amp respectively. Another feedback resistor R FBThe two ends are connected to the non-inverting input terminal V2 and the inverting output terminal V02 of the first op amp respectively. The voltage amplifier (VA) includes a second op amp, a third op amp, two capacitors C1 and two resistors R2; the inverting input terminal V3 of the second op amp is connected to the non-inverting output terminal V01 of the first op amp, the non-inverting input terminal V4 of the second op amp is connected to the inverting output terminal V02 of the first op amp; the non-inverting output terminal V03 of the second op amp is connected to the inverting input terminal V5 of the third op amp, the inverting output terminal V04 of the second op amp is connected to the non-inverting input terminal V6 of the third op amp; a capacitor C1 The two ends of capacitor C1 are connected to the inverting input V5 and non-inverting output V05 of the third op amp, respectively. The two ends of capacitor C1 are connected to the non-inverting input V6 and inverting output V06 of the third op amp, respectively. The two ends of resistor R2 are connected to the inverting input V3 of the second op amp and the non-inverting output V05 of the third op amp, respectively. The two ends of resistor R2 are connected to the non-inverting input V4 of the second op amp and the inverting output V06 of the third op amp, respectively. The third op amp outputs the final result. The two ends of resistor R1 are connected to the non-inverting output V01 of the first op amp and the inverting input V3 of the second op amp, respectively. The two ends of resistor R1 are connected to the inverting output V02 of the first op amp and the non-inverting input V4 of the second op amp, respectively.

[0036] Specifically, the memory cell of an embodiment of the present invention is a floating-gate transistor. A floating-gate transistor has two gate layers: the upper gate is the control gate, and the lower gate is called the floating gate. Data storage is achieved by changing the number of electrons on the floating gate and the threshold voltage. The programming operation injects electrons into the floating gate to increase the threshold voltage, while the erase operation "draws" electrons back from the floating gate to reduce the threshold voltage. After a given gate voltage, the magnitude of the threshold voltage is reflected in the magnitude of the leakage current. The residual electrons on the floating gate are externally manifested in changes in the threshold voltage and leakage current. The subsequent readout circuit reads the data based on the magnitude of the leakage current. For example, after an erase operation, the threshold voltage drops, and the applied gate voltage is greater than the threshold voltage, resulting in a larger leakage current.

[0037] See also Figure 2 In this embodiment of the present invention, a memory cell is divided into several memory cell segments (M0-M7), and a switch selection signal (G0-G7) is output through 3-8 decoding. The switch selection signal is input to the control switch (HV Switch0-HV Switch7), thereby determining whether to control V G The signal is passed to V Gi (Represents V G0 -V G7 Any one of them). Among them, V Gi is the gate voltage of the memory cell segment (M0-M7), and V D 、V SThe leakage current of this embodiment is read out using a segmented method. The covered memory cell can be divided into several segments according to the different threshold voltages. Since the leakage current of the memory cells in different segments varies greatly, it is easy to distinguish them, thus achieving a wide range and high-precision reading of the leakage current.

[0038] In one embodiment, see Figure 3 , the control switch includes NMOS tube M NH1 、NMOS tube M NH2 、NMOS tube M NH3 , NMOS tube M1, NMOS tube M2 and charge pump circuit; NMOS tube M NH1 The gate terminal, NMOS tube M NH2 The gate terminal and NMOS tube M NH3 The gate terminals of the charge pump circuit are connected to the source terminal of the NMOS tube M1 and the source terminal of the NMOS tube M2. NH1 The source end of NMOS tube M NH2 The output end of the charge pump circuit is connected to the gate end of the NMOS tube M2, the source end of the NMOS tube M1, and the NH3 The gate terminal of the NMOS tube M1 is connected to the gate terminal of the NMOS tube M2, the drain terminal of the NMOS tube M1 is connected to the input voltage of the charge pump circuit, the source terminal of the NMOS tube M2 is connected to the output voltage of the charge pump circuit, and the drain terminal of the NMOS tube M2 is connected to the output voltage of the charge pump circuit.

[0039] Furthermore, the charge pump circuit of the embodiment of the present invention adopts a cross-coupled charge pump, which is beneficial to improving the boost efficiency. The input terminal of the charge pump circuit is IN and the output terminal is SW. In the initial stage, the nodes A, B and the clock control signal CLK (CLKA / CLKB) are all at 0 potential, and M N1 and M N2 When a certain voltage V is applied to the input terminal IN, IN When the output terminal SW generates a voltage of about V IN +VDD voltage value. When the switch is open, the output SW passes through M NH3 Connected to GND, the input terminal IN is connected to V through M1 HV When the switch is closed, the input terminal IN passes through M NH2 Rising to VDD-V THZ When the clock control signal CLK (CLKA / CLKB) starts to flip, the output terminal SW rises to V IN +VDD, after the output SW is fed back to the M1 terminal, the voltage at the input terminal IN becomes larger, thereby generating a larger output terminal SW voltage, and the cycle continues until the output terminal SW makes M2 fully turned on. At this time, VOTU =V HV . Where V OTU is the output voltage of the charge pump circuit, V HV is the input voltage of the charge pump circuit, V HV V G , and G i It is used to control M NH1 、M NH2 and M NH3 If the control switch is not connected to the charge pump circuit, but directly connects V HV Connected to the M2 gate voltage, then because M2 is an NMOS tube, there will be threshold loss when transmitting high voltage, and the maximum transmission voltage is V HV -V THN voltage value.

[0040] It should be noted that the HV transistors in the embodiment of the present invention are all NMOS transistors. NH3 and M NH1 The gate voltage is high, M NH2 The gate voltage is low, making M NH3 The output terminal SW is connected to 0, so M1 is disconnected, and the input terminal IN is connected to V HV Disconnect, M NH1 The conduction makes the input terminal IN connected to 0, at this time M NH2 The gate voltage is low and the switch is turned off. When the switch is turned on, M NH3 、M NH1 Both disconnected, M NH2 Connected.

[0041] In an application embodiment, see Figure 4 The charge pump circuit (charge pump core) is connected to the charge pump control circuit. The charge pump control circuit includes a first comparator (comparator 1), a second comparator (comparator 2), a third comparator (comparator 3), a fourth comparator (comparator 4) and an error amplifier arranged in parallel. The inverting input terminal (- terminal) of the first comparator, the second comparator, the third comparator, the fourth comparator and the error amplifier is connected to the sampling voltage V of the charge pump circuit. FB The non-inverting input terminals (+ terminals) of the first comparator, the second comparator, and the third comparator are connected to the first reference voltage V of the charge pump circuit. ref1 The non-inverting input terminal (+ terminal) of the error amplifier is connected to the second reference voltage V ref2 The non-inverting input terminal (+ terminal) of the fourth comparator is connected to the third reference voltage V ref3 The output terminals of the first comparator, the second comparator and the third comparator are connected to the input terminal of the current driving circuit; the output terminal of the fourth comparator V skip Connect to the input of the OR gate circuit; the output of the error amplifier Vco Connect the non-inverting input terminal (+ terminal) of the fifth comparator (comparator 5) and the input terminal S1 of the two-way selector; the inverting input terminal (- terminal) of the fifth comparator is connected to the first reference voltage V ref1 , the output terminal V of the fifth comparator MOD Connect the other input end of the OR gate circuit and the input end EN of the two-way selector; the output end of the OR gate circuit is connected to the input end of the AND gate circuit; the input end S0 of the two-way selector is connected to the first reference voltage V ref1 , the output terminal V of the two-way selector MUX The input end of the voltage-controlled oscillator is connected to the other input end of the AND gate circuit; the output end of the AND gate circuit is connected to the input end of the current driving circuit; the AND gate circuit outputs the clock control signal CLKA of the charge pump, and the current driving circuit outputs another clock control signal CLKB of the charge pump.

[0042] Specifically, the charge pump circuit of the embodiment of the present invention adopts a combination of frequency conversion control and cycle skipping control, see Figure 4 , the error amplifier output voltage V CO Determines whether the circuit is working in variable frequency control state or cycle skipping control state. co Greater than the first reference voltage V ref1 When the output signal of the fifth comparator V MOD is high level, at this time the two-way selector selects the signal output of port S1, the signal of which is exactly the output voltage V CO , voltage V CO Controls the output frequency of the voltage controlled oscillator, while V MOD When V is high, the output of the OR gate is high, and the final output of the AND gate is the clock signal of the voltage-controlled oscillator, thereby realizing frequency conversion control. CO Less than the first reference voltage V ref1 When V MOD is low level, the two-way selector selects the signal of the S0 port, which is the first reference voltage V ref1 As the output, the first reference voltage V ref1 Controls the voltage controlled oscillator. However, whether the output frequency of the voltage controlled oscillator is loaded into the charge pump circuit depends on the signal V skip The level of the sampling voltage V FB Higher than the reference voltage V ref3 When the fourth comparator outputs a low level signal, since V MOD and V skipBoth are low level, so the output of the OR gate is low level, forcing the output of the AND gate to a constant level. At this time, the charge pump has no changing clock signal loading, the voltage gradually decreases, and the circuit is in the skip cycle state of the skip cycle control mode; wait until the sampling voltage V FB Lower than the third reference voltage V ref3 And V CO Still less than V ref1 When the pump is in the jump cycle control mode, V ref1 The voltage-controlled oscillator is controlled and its output signal is applied to the charge pump core circuit, causing the output voltage to rise. The charge pump control circuit of this embodiment of the present invention employs variable frequency control during the charge pump boost phase, helping the charge pump quickly boost the voltage to the target value. After the charge pump reaches the target voltage, it employs cycle skipping control during the stable operation phase, helping to reduce the switching power consumption of the charge pump circuit while ensuring that the charge pump outputs a constant voltage across a wide input voltage range.

[0043] Further, participate Figure 4 , the output terminal of the charge pump circuit V out Connected with output capacitor C out , output capacitor C out The other end is grounded, so that by connecting a larger resistor to the output end, it is beneficial to improve the smoothness of the output ripple during skip cycle control. It should be noted that the charge pump control circuit also includes resistors R1-R5, with the two ends of resistor R1 connected to the output end of the charge pump circuit and the inverting input end of the first comparator, respectively. The two ends of resistor R2 are connected to the inverting input end of the first comparator and the inverting input end of the second comparator, respectively. The two ends of resistor R3 are connected to the inverting input end of the second comparator and the inverting input end of the third comparator, respectively. One end of resistor R4 is connected to the inverting input end of the third comparator, and the other end of resistor R4 is connected to the inverting input end of the fourth comparator and the inverting input end of the error amplifier. The inverting input end of the fourth comparator is connected in parallel with the inverting input end of the error amplifier. One end of resistor R5 is connected to the inverting input end of the fourth comparator and the inverting input end of the error amplifier, and the other end of resistor R5 is grounded.

[0044] In an application embodiment, see Figure 4The current drive circuit includes a first converter, a second converter, a third converter, and a fourth converter connected in parallel. The first converter, the second converter, the third converter, and the fourth converter output currents I1, I2, I3, and I4, respectively. Currents I1, I2, I3, and I4 all flow into the clock control signal GLKB input terminal of the charge pump circuit. The input terminals of the first converter, the second converter, the third converter, and the fourth converter are connected to the output terminal of the AND gate circuit, and the first converter, the second converter, the third converter, and the fourth converter output the clock control signal CLKB. The input terminal of the second converter is connected to the output terminal of the first comparator, the input terminal of the third converter is connected to the output terminal of the second comparator, and the input terminal of the fourth converter is connected to the output terminal of the third comparator.

[0045] Specifically, the current drive circuit samples the output voltage in three stages. When the charge pump output voltage is very low, four currents, I1 to I4, will provide charge to the charge pump's pump-up capacitor. Currents I2 to I4 are feedback currents, and I1 is the inherent current of the original circuit. The larger the current, the more charge is provided. Therefore, when the capacitance value remains unchanged, the maximum voltage value V that can be obtained on the pump-up capacitor is gain The larger the value, the shorter the charge pump rise time, which shortens the charge pump boost time and speeds up the charge pump boost speed. Then, as the output voltage of the charge pump increases, the negative terminal sampling voltage from the first comparator to the third comparator will increase to the first reference voltage V ref1 As a result, the first to third comparators are turned off in sequence, and the currents I2 to I4 also become zero in sequence, which gradually reduces the current input to the charge pump capacitor. gain It also decreases. After the charge pump boosts to a stable state, the current supplied to the charge pump boost capacitor is only I1, reaching the minimum value, V gain Reaching the minimum value, it meets the low ripple requirement when the charge pump is in stable state.

[0046] In one embodiment, referring to Figure 1The transimpedance amplifier (TIA) uses a fully differential parallel-parallel feedback transimpedance amplifier. Its common-mode feedback method uses the common-mode feedback of a differential pair. The size of its transimpedance resistance will affect the noise performance and linearity of the entire circuit. Since the leakage current flowing out of the storage cell is not a differential signal, a fully differential input cannot be achieved. Therefore, a storage cell is selected as a reference cell (Cell_R) in each read voltage segment so that the threshold voltage value or leakage current value of the storage cell is the middle value of the read voltage range. The leakage current of the reference cell is input to one end of the TIA as the reference leakage current, and the leakage current of the storage cell (Cell_1) to be measured under the same read voltage is input to the other end of the TIA. The fully differential circuit has a common-mode feedback circuit at the two output ends to ensure that the sum of the voltages at both ends of the output is twice the common-mode voltage value, so that the output swing can be increased without increasing the power supply voltage. The increase in the output swing increases the current detection accuracy of the readout circuit by 1 times. Among them, the transimpedance Z of the transimpedance amplifier OUT_TIA The value is calculated as follows:

[0047] V OUT_TIA =-A TIA (V1-V2)

[0048] (I F_R +V1*s*C F )R FB =(V01-V1)

[0049] (I F_1 +V2*s*C F )R FB =(V02-V2)

[0050] Z OUT_TIA =V OUT_TIA / I F

[0051] V OUT_TIA =V01-V02

[0052] Combining the above equations, we can get the transimpedance Z OUT_TIA The expression in the frequency domain is:

[0053]

[0054] Furthermore, the transimpedance is transformed by LAPLACE to obtain the transimpedance Z OUT_TIA The expression in the time domain is:

[0055]

[0056] Where A TIA represents the gain of the first op amp, V OUT_TIA Represents the output voltage of the transimpedance amplifier.

[0057] Among them, the first term (R FB ) is the ideal transresistance, the second term is the static error due to the limited gain of the operational amplifier, and the third term is the dynamic error due to the limited gain bandwidth. Since the leakage current measured in the present invention is nearly DC, there is sufficient time for the circuit to settle, making the error in the third term negligible. Therefore, the calculation is as follows:

[0058]

[0059] Therefore, according to the preset measurement accuracy, the output voltage V OUT_TIA The required accuracy is to obtain the transimpedance Z OUT_TIA Accuracy, and then further obtain the gain A of the first op amp TIA The value range of .

[0060] In an application embodiment, the first operational amplifier of the embodiment of the present invention is a two-stage operational amplifier, and its circuit schematic diagram is shown in FIG. Figure 5 , the first op amp uses a PMOS input tube, V B1 and V B2 is the bias voltage, C1 and C2 in the figure are used for Miller compensation, and R1 and R2 are used to offset the zero point caused by the Miller compensation capacitor.

[0061] In one embodiment, referring to Figure 6 The voltage amplifier (VA) uses a fully differential non-inverting amplifier. To increase gain, the voltage amplifier (VA) employs a two-stage operational amplifier. The first stage is a folded cascode, and the second stage is a simple op amp consisting of PMOS and NMOS. This second stage not only increases the output swing but also reduces the output resistance. Furthermore, the output of the folded cascode in the first stage is not located on the input branch, enabling a wider input and output range. It should be noted that the output stage of the voltage amplifier uses a resistive common-mode feedback circuit.

[0062] In one embodiment, the erasing device of the present invention includes a leakage current guiding circuit, the circuit schematic diagram of which is shown in FIG. Figure 7 , the fourth op amp in the figure is connected to the external voltage source V G , the other end is connected to the drain terminal V of the floating gate unit D , so that the virtual short characteristic of the op amp can be used to G Copied to the drain terminal V of the floating gate cell DBecause the positive input of the floating gate cell is connected to the gate of the input transistor inside the op amp, no DC current is generated. After applying appropriate voltages to each terminal, the floating gate cell generates leakage current, which is mirrored to the M4 transistor through the current mirror, and then output from M4 to the leakage current readout circuit.

[0063] The memory erasing method according to the technical solution of the present invention, applied to the memory erasing device of the above embodiment, comprises at least the following steps:

[0064] S1: Obtaining a threshold voltage of a memory cell that has not been erased. Specifically, the threshold voltage of the memory cell that has not been erased is defined as an initial threshold voltage.

[0065] S2: Performing an erase operation on the memory cell; wherein the erase operation is either data erase or arbitrary sequence overwrite; obtaining the threshold voltage of the memory cell after the erase operation; and obtaining the current difference between the threshold voltage and the previous threshold voltage. Specifically, the erase operation in the embodiment of the present invention includes two methods: data erase and arbitrary sequence overwrite. Each erase operation is either of the above two methods, and multiple erase operations are performed on the memory cell. The memory cell leakage current after each erase operation is obtained, so that the number of residual electrons on the floating gate after the erase operation can be determined based on the current threshold voltage.

[0066] S3: Determine whether the current difference values ​​for N consecutive times are all less than the set difference value. If not, repeat step S2 until the N current differences are less than the set difference value. Specifically, in the embodiment of the present invention, N=5. When the threshold voltage value after five consecutive erase operations changes slightly, the number of residual electrons on the floating gate changes slightly, making it difficult for an attacker to obtain the stored information based on the threshold voltage, thereby facilitating effective erasure.

[0067] The present invention conducts experimental verification on the erasing device of the memory. Figure 8 , the noise of the leakage current readout circuit is within the allowable range, and the recognition accuracy of the leakage current under a wide range of inputs of the present invention meets the requirements.

[0068] It should be appreciated that the method steps in the embodiments of the present invention can be implemented or executed by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable memory. The method can use standard programming techniques. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if desired, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. In addition, for this purpose, the program can be run on a programmed application-specific integrated circuit.

[0069] Furthermore, the operations of the processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by the context. The processes described herein (or variations and / or combinations thereof) may be performed under the control of one or more computer systems configured with executable instructions and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that is executed collectively on one or more processors, by hardware, or a combination thereof. The computer program includes a plurality of instructions that can be executed by one or more processors.

[0070] Furthermore, the method can be implemented in any type of computing platform that is operably connected to a suitable computer, including but not limited to a personal computer, a minicomputer, a mainframe, a workstation, a network or distributed computing environment, a separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, etc. Various aspects of the present invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, an optical read and / or write storage medium, RS1M, ROM, etc., so that it can be read by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the process described herein. In addition, the machine-readable code, or portions thereof, can be transmitted over a wired or wireless network. When such media includes instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor, the invention described herein includes these and other different types of non-transitory computer-readable storage media. When programmed according to the methods and techniques of the present invention, the present invention can also include the computer itself.

[0071] The computer program can be applied to input data to perform the functions described herein, thereby converting the input data to generate output data that is stored in a non-volatile memory. The output information can also be applied to one or more output devices such as a display. In a preferred embodiment of the present invention, the converted data represents a physical and tangible object, including a specific visual depiction of the physical and tangible object produced on the display.

[0072] The above description is merely a preferred embodiment of the present invention. The present invention is not limited to the aforementioned embodiments. As long as the technical effects of the present invention are achieved by the same means, any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention. Within the scope of protection of the present invention, various modifications and variations of the technical solutions and / or implementation methods are possible.

Claims

1. A memory erasing device, comprising an erasing circuit applied to a memory cell, characterized in that: include: a control switch, one end of the control switch being connected to the storage unit and the other end being connected to a switch selection signal; a leakage current readout circuit, the leakage current readout circuit comprising a transimpedance amplifier and a voltage amplifier; The transimpedance amplifier includes a first operational amplifier and two feedback resistors, wherein the inverting input of the first operational amplifier is connected to the output of the reference floating gate, and the non-inverting input of the first operational amplifier is connected to the output of the current floating gate; the two ends of one of the feedback resistors are respectively connected to the inverting input and the non-inverting output of the first operational amplifier, and the two ends of the other feedback resistor are respectively connected to the non-inverting input and the inverting output of the first operational amplifier; The voltage amplifier includes a second operational amplifier, a third operational amplifier, two capacitors C1, and two resistors R2; the inverting input of the second operational amplifier is connected to the non-inverting output of the first operational amplifier, and the non-inverting input of the second operational amplifier is connected to the inverting output of the first operational amplifier; the non-inverting output of the second operational amplifier is connected to the inverting input of the third operational amplifier, and the inverting output of the second operational amplifier is connected to the non-inverting input of the third operational amplifier; two ends of one capacitor C1 are respectively connected to the inverting input and non-inverting output of the third operational amplifier, and two ends of another capacitor C1 are respectively connected to the non-inverting input and inverting output of the third operational amplifier; two ends of one resistor R2 are respectively connected to the inverting input of the second operational amplifier and the non-inverting output of the third operational amplifier, and two ends of another resistor R2 are respectively connected to the non-inverting input of the second operational amplifier and the inverting output of the third operational amplifier; the third operational amplifier outputs a final result; Among them, the two ends of one resistor R1 are respectively connected to the non-inverting output end of the first op amp and the inverting input end of the second op amp, and the two ends of another resistor R1 are respectively connected to the inverting output end of the first op amp and the non-inverting input end of the second op amp.

2. The memory erasing device according to claim 1, wherein: The control switch includes an NMOS tube M NH1 、NMOS tube M NH2 、NMOS tube M NH3 , NMOS tube M1, NMOS tube M2 and charge pump circuit; the NMOS tube M NH1 The gate end of the NMOS tube M NH2 The gate terminal and the NMOS tube M NH3 The gate end of the charge pump circuit is connected to the source end of the NMOS tube M1 and the gate end of the NMOS tube M NH1 The source end of the NMOS tube M NH2 The output end of the charge pump circuit is connected to the gate end of the NMOS tube M2, the source end of the NMOS tube M1, the NMOS tube M NH3 The source end of the NMOS tube M1 is connected to the gate end of the NMOS tube M2, the drain end of the NMOS tube M1 is connected to the input voltage of the charge pump circuit, the source end of the NMOS tube M2 is connected to the output voltage of the charge pump circuit, and the drain end of the NMOS tube M2 is connected to the output voltage of the charge pump circuit.

3. The memory erasing device according to claim 2, wherein: The charge pump circuit is connected to a charge pump control circuit, which includes a first comparator, a second comparator, a third comparator, a fourth comparator and an error amplifier arranged in parallel, wherein the inverting input terminals of the first comparator, the second comparator, the third comparator, the fourth comparator and the error amplifier are connected to the sampling voltage of the charge pump circuit, the non-inverting input terminals of the first comparator, the second comparator and the third comparator are connected to the first reference voltage of the charge pump circuit, the non-inverting input terminal of the error amplifier is connected to the second reference voltage of the charge pump circuit, and the non-inverting input terminal of the fourth comparator is connected to the third reference voltage of the charge pump circuit; the output terminals of the first comparator, the second comparator and the third comparator are connected to the input terminal of the current drive circuit; the output terminal of the fourth comparator is connected to an OR gate The input end of the circuit; the output end of the error amplifier is connected to the non-inverting input end of the fifth comparator and the input end S1 of the two-way selector; the inverting input end of the fifth comparator is connected to the first reference voltage, and the output end of the fifth comparator is connected to the other input end of the OR gate circuit and the input end EN of the two-way selector; the output end of the OR gate circuit is connected to the input end of the AND gate circuit; the input end S0 of the two-way selector is connected to the first reference voltage, the output end of the two-way selector is connected to the input end of the voltage-controlled oscillator, and the input end of the voltage-controlled oscillator is connected to the other input end of the AND gate circuit; the output end of the AND gate circuit is connected to the input end of the current driving circuit; the AND gate circuit outputs the clock control signal CLKA of the charge pump, and the current driving circuit outputs the clock control signal CLKB of the charge pump.

4. The memory erasing device according to claim 3, wherein: The output end of the charge pump circuit is connected to an output capacitor.

5. The memory erasing device according to claim 4, characterized in that: The current driving circuit includes a first converter, a second converter, a third converter, and a fourth converter arranged in parallel, wherein the input ends of the first converter, the second converter, the third converter, and the fourth converter are connected to the output end of the AND gate circuit, and the first converter, the second converter, the third converter, and the fourth converter output the clock control signal CLKB; the input end of the second converter is connected to the output end of the first comparator, the input end of the third converter is connected to the output end of the second comparator, and the input end of the fourth converter is connected to the output end of the third comparator.

6. The memory erasing device according to claim 1, wherein: The transimpedance Z of the transimpedance amplifier OUT_TIA The calculation is as follows: Where V OUT_TIA represents the output voltage of the transimpedance amplifier, A TIA represents the gain of the first op amp, R FB represents the feedback resistor.

7. The memory erasing device according to claim 6, wherein: It also includes a leakage current steering circuit, which includes a fourth op amp, an inverting input terminal of the fourth op amp connected to the drain terminal of the storage unit, and a non-inverting input terminal of the fourth op amp connected to the gate terminal of the storage unit.

8. A method for erasing a memory, applied to the memory erasing device according to any one of claims 1 to 7, the method comprising the following steps: S1: Acquiring the threshold voltage of the memory cell before the erase operation; S2: performing an erase operation on the memory cell; wherein the erase operation is any one of data erase and arbitrary sequence overwrite; obtaining a threshold voltage of the memory cell after the erase operation; and obtaining a current difference between the threshold voltage at the current time and the threshold voltage at the previous time; S3: Determine whether the current difference value for N consecutive times is smaller than the set difference value. If not, repeat step S2 until the current difference value is smaller than the set difference value. 9 . A computer-readable storage medium having program instructions stored thereon, wherein the program instructions implement the method according to claim 8 when executed by a processor.

10. A memory erasing device system, characterized in that: include: A computer device comprising the computer-readable storage medium according to claim 9.

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