Semiconductor memory device and readout method

Abstract

The present invention provides a semiconductor memory device and a reading method, which can realize high-speed error detection and correction processing time and achieve miniaturization. The flash memory (100) of the present invention has a NAND chip (200) and an ECC chip (300). The NAND chip (200) has: a memory array; a page buffer / sensing circuit including a latch (L1) and a latch (L2); and a dedicated input and output terminal (220) that can transmit data between the NAND chip (200). The latch (L1) includes buffers (C0, C1), and the latch (L2) only includes buffer (C1). The data in the buffer (C0) of the latch (L1) and the data in the buffer (C1) of the latch (L2) are transmitted to the ECC chip (300). In response to the data of the starting address output from the ECC chip (300), the next page is read from the memory array, and the read data is maintained in the latch (L1).

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor memory device such as a NAND type flash memory and a readout method, and particularly relates to error detection and correction. BACKGROUND

[0002] In a NAND type flash memory, repeated programming or erasing of data sometimes causes deterioration of a tunnel insulating film and the like, resulting in a decrease in charge retention characteristics, or threshold variation due to charge trapped in the tunnel insulating film, leading to bit errors. As a countermeasure against such bit errors, an error detection and correction circuit (hereinafter referred to as an ECC circuit) is used in the flash memory. SUMMARY

[0003] Figure 1 A diagram showing the structure of a conventional off-chip ECC-equipped flash memory. A flash memory 10 is configured to include a NAND chip 20 including a NAND type memory array or its peripheral circuit, and the NAND chip 20 is connected to a controller chip 30 on which an ECC function 40 is mounted. The NAND chip 20 and the controller chip 30 are respectively housed in different packages, and each package is mounted on a printed board, for example.

[0004] The NAND chip 20 and the controller chip 30 are mounted with, for example, a serial peripheral interface (SPI) that can transmit data in synchronization with a clock signal, and input / output terminals of #CS, CLK, DI, DO, #WP, and #HOLD are provided in each of the chips. The controller chip 30 sends a command, an address, and data to the NAND chip 20 via the input / output terminals of the SPI.

[0005] The ECC function 40 includes an encoder that encodes data and generates parity data, and a decoder that decodes data based on the parity data. The ECC function 40 performs error detection and correction of a plurality of bits (for example, 2 bits, 4 bits, 8 bits, and the like) by, for example, a Bose Chaudhuri Hocquenghem (BCH) code, and in this case, the BCH decoder includes a syndrome calculation section that evaluates a syndrome of data, a Euclidean algorithm calculation section that calculates an error location polynomial (ELP), an error location search section that calculates a root of the error location polynomial and searches for an error location, and an error correction section that corrects an error based on the searched error location.

[0006] The page buffer / sense circuit of the NAND chip 20 includes two latches, one of which includes two buffers, one of which holds data of a plurality of sectors (e.g., 2 sectors, 4 sectors, etc.). Data transfer between the NAND chip 20 and the controller chip 30 is performed in units of buffers. Also, the ECC function 40 generates parity data, or performs error detection, correction, in units of sectors. One sector encoded by the ECC function 40 includes main data and parity data.

[0007] When the controller chip 30 causes the NAND chip 20 to perform a program operation, the controller chip 30 causes the ECC function 40 to generate parity data from data to be programmed, and transfers the generated parity data and main data to the NAND chip 20 via the DO terminal of the SPI. The NAND chip 20 holds the received main data and parity data in the latches, and programs the data held in the latches in the selected page of the memory array.

[0008] On the other hand, data read out from the memory array in the NAND chip 20 is transferred to the controller chip 30 via the DO terminal of the SPI. The ECC function 40 detects errors based on the parity data, and corrects the main data or the parity data according to the result of the detection.

[0009] Figure 2 A timing chart showing the operation of each part of the ECC function of the controller chip 30 is shown in FIG. 6. The NAND chip 20 performs a read operation according to a read command transferred from the controller chip 30, and outputs the read data to the controller chip 30. At time tO, the NAND IF of the controller chip 30 starts receiving main data and parity data Pt of sector SO from the NAND chip 20, and at time tl, starts receiving main data and parity data Pt of sector SI, and at time t2, time t3, starts receiving main data and parity data Pt of sector S2, sector S3. The ECC function 40 performs syndrome calculation of the main data of sector SO, calculation of the error position polynomial, search for the error position, in the form of pipeline processing, at the same time as the data reception of sector SI, and corrects errors in the main data of sector SO based on the searched error position. Then, the CPU IF of the controller chip 30 transfers the error-corrected data of sector SO to the host device. The ECC processing for sector SI, sector S2, sector S3 is also performed in the same manner, and the error-corrected data of each sector is output in the reception of the sector.

[0010] In a case where read data is transmitted from the NAND chip 20 to the controller chip 30, the correction sub-computation must be performed after the parity data of the sector is transmitted. Therefore, there is a problem that, if the bit width of the DO terminal of the SPI is narrow, the data transmission takes time, the idle state of the controller chip 30 becomes long during the period, the performance of the pipeline processing cannot be sufficiently exerted, and the like. Also, if the size of a page becomes large along with the high integration of the memory array, the occupied area of the page buffer / sense circuit becomes large, thereby causing the chip to become large. Therefore, the space saving of the page buffer / sense circuit is desired.

[0011] The semiconductor storage device of the present application includes: a NAND chip including a memory array of a NAND type, a page buffer / sense circuit including a first latch and a second latch which can hold page data read from the memory array, and a control section which controls a read operation; and an ECC chip including an error detection and correction function. The first latch includes a first holding section which holds a first data section of the page data, and a second holding section which holds a second data section. The second latch is smaller in data size than the first latch, and holds the second data section transmitted from the second holding section of the first latch. The control section transmits the first data section held by the first holding section of the first latch to the ECC chip, and then transmits the second data section held by the second latch to the ECC chip. The ECC chip performs error detection and correction of the first data section and the second data section. The control section reads a next page from the memory array in response to a timing at which the ECC chip outputs the first data section to the outside.

[0012] The read method of the present application is a read method of a semiconductor storage device including: a NAND chip including a memory array of a NAND type and a page buffer / sense circuit including a first latch and a second latch which can hold page data read from the memory array; and an ECC chip including an error detection and correction function of data transmitted from the NAND chip. In the NAND chip, a first data section and a second data section of a page read from the memory array are held in the first latch, the second data section held in the first latch is transmitted to the second latch, and then the first data section held in the first latch is transmitted to the ECC chip, and the second data section held in the second latch is transmitted to the ECC chip. In the ECC chip, error detection and correction of the first data section are performed, and then error detection and correction of the second data section are performed. In response to the ECC chip outputting the first data section which has been error corrected, a next page is read from the memory array in the NAND chip.

[0013] According to the present invention, by making the data size of the second latch of the NAND chip's page buffer / sensing circuit smaller than the data size of the first latch, the NAND chip can be miniaturized and space-saving. Furthermore, by providing an ECC chip separately from the NAND chip, error detection and correction processing can be accelerated. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A diagram showing a schematic structure of a conventional flash memory;

[0015] Figure 2 A timing diagram showing the operation of the ECC function of a conventional flash memory;

[0016] Figure 3 A diagram showing a schematic structure of a flash memory according to an embodiment of the present invention;

[0017] Figure 4 (A) is a diagram showing the main structure of the flash memory of this embodiment. Figure 4 (B) is a diagram showing the main structure of a flash memory as a comparative example;

[0018] Figure 5 A block diagram showing the internal structure of a NAND chip and an ECC chip according to an embodiment of the present invention;

[0019] Figure 6 A timing diagram showing an ECC operation of a flash memory according to an embodiment of the present invention;

[0020] Figure 7 A diagram showing a timing diagram of a continuous read operation of a flash memory according to a comparative example;

[0021] Figure 8 A diagram showing a timing diagram of a continuous read operation of a flash memory according to an embodiment of the present invention;

[0022] Figure 9 1 is a diagram showing a timing diagram when an interruption occurs during a continuous read operation in a flash memory of a comparative example;

[0023] Figure 10 A diagram showing a timing diagram when an interruption occurs during a continuous read operation in the flash memory of this embodiment;

[0024] Figure 11 A diagram showing a timing diagram of a continuous read operation of a flash memory according to a second embodiment of the present invention;

[0025] Figure 12 This diagram shows a timing diagram when an interruption occurs during a continuous read operation in a flash memory according to a second embodiment of the present invention.

[0026] Explanation of symbols

[0027] 10, 100: flash memory

[0028] 20, 200, 200_X: NAND chip

[0029] 30, 400: controller chip

[0030] 40: ECC function

[0031] 210, 310, 330, 410: input / output terminal for SPI

[0032] 220, 320: input / output terminal for ECC

[0033] 230: page buffer / sense circuit

[0034] 240: interface circuit (ECC_IF)

[0035] 250, 350: interface circuit (CTL_IF)

[0036] 260, 370: ECC control section

[0037] 270, 380: controller

[0038] 280: address control section

[0039] 300: ECC chip

[0040] 340: interface circuit (NAND_IF)

[0041] 360: ECC core

[0042] C0, C1: cache

[0043] CK, CLK: clock signal

[0044] L1, L2: latch

[0045] OSC: oscillator

[0046] P0-P2: page

[0047] Pt: parity data

[0048] S0-S7: sector

[0049] SEL1-SEL5: selector

[0050] t0-t9: time DETAILED DESCRIPTION

[0051] Figure 3Fig. 1 is a diagram showing a schematic configuration of a flash memory according to an embodiment of the present application. The flash memory 100 of this embodiment is configured including a NAND chip 200 and an ECC chip 300 electrically connected to the NAND chip 200.

[0052] Although not shown here, the NAND chip 200 typically includes a memory array of the NAND type and a peripheral circuit. The peripheral circuit includes a row decoder, a column decoder, a page buffer / sense circuit, an interface circuit, a controller, an internal voltage generation circuit, and the like, and the controller controls readout, programming, erasure, and the like, in accordance with an input command. The memory array includes a plurality of blocks, and a plurality of NAND strings are formed in each block. The NAND strings can be formed two-dimensionally on a substrate surface or three-dimensionally on a substrate surface. The memory cells can be of a single-level cell (SLC) type storing one bit (binary data), or of a type storing a plurality of bits.

[0053] The NAND chip 200 includes input / output terminals 210 (#CS, CLK, DI, DO, #WP, #HOLD) for SPI and input / output terminals 220 (VALID, CK, DATA) for ECC as an interface with the ECC chip 300. The "#" indicates low active. The #CS is a terminal that receives a chip selection signal for enabling or disabling the chip, the CLK is a terminal that receives a serial clock signal, the DI is a terminal that inputs serial data, the DO is a terminal that outputs serial data, the #WP is a terminal that receives a signal for protecting a status register from being written, and the #HOLD is a terminal that receives a signal for holding the chip. The NAND chip 200 receives a command, an address, and data in synchronization with the serial clock signal CLK or outputs data in synchronization with the serial clock signal CLK via the input / output terminals 210 for SPI.

[0054] As the input and output terminals 220 dedicated to the ECC, the VALID is a terminal that inputs and outputs a VALID signal indicating whether or not data transfer between the NAND chip 200 and the ECC chip 300 is valid, the CK is a terminal that outputs a clock signal CK used for data transfer and ECC processing, and the DATA is a terminal that inputs and outputs data between the NAND chip 200 and the ECC chip 300. Note that the bit width m (data transfer width) of the DO terminal / DI terminal for the SPI is, for example, xl, x4, or x8, but the bit width n of the DATA terminal dedicated to the ECC is configured to be larger than the bit width m of the DO terminal / DI terminal for the SPI (n > m), and is, for example, x32. Therefore, if the frequency of the clock signal CK is the same as that of the clock signal CLK, the data transfer time between the NAND chip 200 and the ECC chip 300 is n / m times faster than the data transfer time of the SPI.

[0055] Further, although not shown here, the NAND chip 200 can include an interface for the ONFi in addition to the input and output terminals 210 for the SPI. The interface for the ONFi includes external control terminals such as a command latch enable (CLE), an address latch enable (ALE), a write enable (#WE), and the like, and input and output terminals such as I / O and the like.

[0056] The ECC chip 300 includes the input and output terminals 310 (#CS, CLK, DI, DO, #WP, #HOLD) for the SPI and the input and output terminals 320 (VALID, CK, DATA) dedicated to the ECC as the interface with the NAND chip 200. The input and output terminals 310 for the SPI of the ECC chip 300 are electrically connected to the corresponding terminals of the input and output terminals 210 for the SPI of the NAND chip 200, respectively, and the input and output terminals 320 dedicated to the ECC are electrically connected to the corresponding terminals of the input and output terminals 220 dedicated to the ECC of the NAND chip 200, respectively.

[0057] The ECC chip 300 also includes input / output terminals 330 (#CS, CLK, DI, DO, #WP, #HOLD) for SPI as an interface with the controller chip 400. The input / output terminals 330 are electrically connected to corresponding terminals of the input / output terminals 410 for SPI of the controller chip 400. Each of the terminals of the input / output terminals 310 (#CS, CLK, DI, DO, #WP, #HOLD) is electrically connected to each of the terminals of the input / output terminals 330 (#CS, CLK, DI, DO, #WP, #HOLD) by internal wiring or the like. That is, the input / output terminals 310 and the input / output terminals 330 are physically arranged apart for the connection of the NAND chip 200 and the controller chip 400, but in terms of electrical properties, the input / output terminals 310 and the input / output terminals 330 are common to the NAND chip 200 and the controller chip 400, and such connection is equivalent to the connection of the input / output terminals 210 for SPI of the NAND chip 200 to the input / output terminals 410 for SPI of the controller chip 400.

[0058] Figure 4 (A) of FIG. 1 is a diagram showing a main part structure of a flash memory of the present embodiment, Figure 4 The NAND chip 200, the NAND chip 200_X include a page buffer / sense circuit that holds data read from the memory array or holds data for programming in the memory array, and the page buffer / sense circuit includes two-stage latches L1, L2. The latches L1, L2 each include a buffer C0, C1, and the latches L1, L2 can perform bidirectional data transfer in units of the buffers C0, C1. The latches L1, L2 each hold one page of data (e.g., 4 KB), and the buffers C0, C1 hold one-half page of data (e.g., 2 KB), and the buffer C0 holds data of four sectors S0 to S3 (e.g., one sector is 512 bytes), and the buffer C1 holds data of four sectors S4 to S7.

[0059] For example, when a page continuous readout operation is performed in the NAND chip 200_X, data of a page read from the memory array is held in the buffers C0, C1 of the latch L1, and then the data held in the buffers C0, C1 of the latch L1 is transferred to the buffers C0, C1 of the latch L2 in units of the buffers. After the transfer from the latch L1 to the latch L2, the next page is read from the memory array, and data of the next page is held in the buffers C0, C1 of the latch L1, and at the same time, the data held in the buffers C0, C1 of the latch L2 is transferred to the ECC chip 300.

[0060] In the NAND chip 200 of the present embodiment, the latch L2 is configured with the data size of the buffer C1, that is, the latch L2 does not include the buffer C0 corresponding to the buffer C0 of the latch L1. When the continuous readout operation of the page is performed, the data of the page read out from the memory array is held in the buffer C0 of the latch L1 and the buffer C1, the data held in the buffer C1 of the latch L1 is transferred to the buffer C1 of the latch L2, and then the data held in the buffer C0 of the latch L1 and the data held in the buffer C1 of the latch L2 are transferred to the ECC chip 300 as one page data.

[0061] The ECC chip 300 performs error detection and correction of the data received from the NAND chip 200, and in response to the ECC chip 300, the data of the initial address corresponding to the buffer C0 is output to the controller chip 400, and the NAND chip performs readout of the next page from the memory array, and holds the readout data in the latch L1. At the time point when the data of the initial address corresponding to the buffer C0 is output to the controller chip 400, the data of the buffer C0 ends the ECC processing, and the data of the buffer C1 of the latch L1 is transferred to the latch L2, so that the overwriting of the data of the next page can be performed in the latch L1.

[0062] In the present embodiment, by setting the data size (storage capacity) of the latch L2 of the page buffer / sense circuit of the NAND chip 200 to half of the latch L2 of the page buffer / sense circuit of the NAND chip 200_X, the miniaturization and space saving of the NAND chip 200 can be achieved.

[0063] Figure 5 A block diagram showing the internal structure of the NAND chip 200 and the ECC chip 300. However, it should be noted that the structure related to the ECC operation is shown in the NAND chip 200, and all the structures are not shown.

[0064] The NAND chip 200 includes: a page buffer / sense circuit 230 including a latch L1 and a latch L2; an oscillator OSC generating a clock signal CK; an interface circuit (hereinafter referred to as an ECC IF) 240 controlling the data transfer with the ECC chip 300 via an ECC dedicated input / output terminal 220; an interface circuit (hereinafter referred to as a CTL IF) 250 controlling the data transfer with the controller chip 400 via an SPI input / output terminal 210; an ECC control section 260; a controller 270 receiving a command and an address input from the input / output terminal 210, including a decoder interpreting the command or an address counter holding and counting the address, and controlling each section based on the decoding result of the command; and an address control section 280 controlling the column address of the page buffer / sense circuit 230.

[0065] The latch Ll includes the buffer C0 and the buffer Cl, the latch L2 includes only the buffer Cl, and the latch Ll and the latch L2 can bi-directionally transfer data of the buffer Cl. The latch Ll holds one page of data (e.g., 4 KB), and the buffer C0 and the buffer Cl hold 1 / 2 page of data (e.g., 2 KB). The buffer Cl of the latch L2 holds 1 / 2 page of data (e.g., 2 KB). The buffer C0 holds data of four sectors S0 to S3 (e.g., one sector is 512 bytes), and the buffer Cl holds data of four sectors S4 to S7.

[0066] The oscillator OSC generates a clock signal CK, which is a frequency most suitable for a data transfer time and a processing time of each section of the ECC operation. Data transfer between the NAND chip 200 and the ECC chip 300 using the DATA terminal is performed in synchronization with the clock signal CK, and the ECC core 360 of the ECC chip 300 performs the ECC processing in synchronization with the clock signal CK. The frequency of the clock signal CK is independent of the frequency of the clock signal CLK of the SPI, and can be set to be higher than the frequency of the clock signal CLK.

[0067] The ECC_IF 240 receives the clock signal CK generated by the oscillator OSC, and supplies the clock signal CK to the CK terminal of the ECC chip 300 via the CK terminal. The ECC_IF 240 outputs read data held in the latch L2 from the DATA terminal to the DATA terminal of the ECC chip 300 at a timing synchronized with the clock signal CK at the time of the read operation, and receives parity data generated by the ECC chip 300 from the DATA terminal at a timing synchronized with the clock signal CK at the time of the program operation.

[0068] The ECC control section 260 supplies the VALID signal to the ECC_IF 240 at the time of the read operation. The VALID signal specifies a period in which data transfer between the input / output terminals 220 and 320 dedicated to the ECC becomes valid, and data transfer in the buffer unit can be performed in the period. The ECC_IF 240 transfers data from the DATA terminal of the NAND chip 200 to the DATA terminal of the ECC chip in the period specified by the VALID signal, for example, in a period in which the VALID signal is at a high level. Further, the ECC_IF 240 outputs the VALID signal from the VALID terminal to the VALID terminal of the ECC chip 300, so that the NAND_IF 340 of the ECC chip 300 can receive data from the NAND chip 200.

[0069] CTL_IF 250 controls input and output of data via the input and output terminal 210. The CTL_IF 250 receives a command, an address, data output from the controller chip 400, and supplies the command and the address to the controller 270, and holds the data in the latch L2 or the latch Ll.

[0070] The controller 270 decodes the input command, and controls a readout, a program, an erase, and the like based on the decoding result. Further, the controller 270 supplies a control flag for identifying a readout or a program to the ECC control section 260 based on the decoding result, or supplies a status signal indicating whether the NAND chip 200 is in a busy state or a standby state to the CTL_IF 250. Furthermore, the controller 270 includes an address counter that counts a column address input from the CTL_IF 250, and supplies an address of the address counter to the address control section 280.

[0071] The ECC control section 260 includes a logic for controlling an ECC process, and an address counter that performs holding and counting of an address for the ECC process. The ECC control section 260 is configured similarly to the ECC control section 370 of the ECC chip 300, that is, the ECC control section 260 is synchronized with the ECC control section 370 so that it can identify what kind of ECC action is performed by the ECC chip 300. Further, a control flag is used for switching of an encoder or a decoder performed by the ECC core 360.

[0072] The address control section 280 receives a column address output from the controller 270 and an ECC column address output from the ECC control section 260, and supplies a column address selected according to an action of the NAND chip 200 to the page buffer / sense circuit 230. A position of data read out from the latch L2 or a position of data written in the latch L2 is controlled by the column address.

[0073] The ECC chip 300 includes a random access memory RAM0, RAMl; an interface circuit (hereinafter, NAND_IF) 340 that controls transmission of data with the NAND chip 200 via the ECC-dedicated input and output terminal 320; an interface circuit (hereinafter, CTL_IF) 350 that controls input and output of data with the NAND chip 200 and the controller chip 400 via the SPI-dedicated input and output terminal 330 and the input and output terminal 310; an ECC core 360 that performs error detection and correction; an ECC control section 370 that includes a logic for controlling the ECC core 360 and an address counter that performs holding and counting of an address for the ECC process; and a controller 380 that receives a command, an address, data input from the input and output terminal 310 and the input and output terminal 330.

[0074] Note that the controller 380 is mounted in the ECC chip 300 to recognize what kind of operation the NAND chip 200 performs, and receives input commands and addresses, and includes a decoder to interpret the commands or an address counter to hold and count the addresses, similarly to the controller 270 of the NAND chip 200. Also, the input and output terminals 330 for SPI are electrically connected to the corresponding terminals of the input and output terminals 310 for SPI, and commands, addresses, and data from the controller 400 are supplied to both the ECC chip 300 and the NAND chip 200.

[0075] The RAM0 and the RAM1 hold 1 / 2 page data, respectively, for example, the RAM0 holds data of the sectors S0 to S3, and the RAM1 holds data of the sectors S4 to S7. When the read operation is performed in the NAND chip 200, the NAND IF 340 receives one page data from the NAND chip 200 in units of sectors via the input and output terminals 220 and 320 during the period in which the VALID signal is high active, and the received data is stored in the RAM0 or the RAM1 selected by the selector SEL1 as Data0 (for example, the sectors S0 to S3) or Data1 (for example, the sectors S4 to S7).

[0076] The ECC controller 370 selects the address of the RAM0 or the RAM1 by the selector SEL3 to supply data read from the selected RAM0 or RAM1 to the ECC core 360 when the ECC core 360 performs error detection and correction of the read data. The ECC core 360 performs syndrome calculation, Euclidean division calculation, and error position search in a pipeline process under the control of the ECC controller 370 with respect to the data read from the RAM0 or the RAM1, and inverts error bits of the data read from the RAM0 or the RAM1 selected by the selector SEL4 in order to correct the error based on the searched error position, and outputs the corrected data to the controller chip 400 via the input and output terminals 330 by the CTL IF 350.

[0077] Also, when the program operation is performed, commands, addresses, and data from the controller chip 400 are input to the ECC chip 300 as well as the NAND chip 200. The controller 380 recognizes the program operation based on the decoding result of the commands, and stores data input from the input and output terminals 330 for SPI in the RAM0 and the RAM1. The ECC controller 370 recognizes the program operation by a control flag from the controller 380, and causes the encoder of the ECC core 360 to operate.

[0078] The ECC core 360, under the control of the ECC control section 370, reads out the input data held in the RAMO or the RAMl, encodes the read-out data in sector units, and generates the parity data for each sector. The generated parity data is transmitted from the DATA terminal to the DATA terminal of the NAND chip 200 via the NAND_IF 340. The NAND chip 200 holds the data received from the controller chip 400 in the latch L2, holds the parity data for each sector received from the ECC chip 300 via the ECC_IF 240 in the latch LI according to the column address designated by the ECC control section 260, and then the controller 270 programs the data held in the latch LI in the memory array.

[0079] Next, the details of the ECC operation of the flash memory 100 of the present embodiment will be described. Figure 6 A timing chart at the time of decoding the read-out data by the ECC core 360 is shown. When the NAND chip 200 performs the read-out operation according to the read-out command, at time tO, the ECC_IF 240 of the NAND chip 200 transmits the main data and the parity data Pt of the sector SO held in the latch LI from the DATA terminal in synchronization with the clock signal CK, and the NAND_IF 340 of the ECC chip 300 starts receiving the main data and the parity data Pt of the sector SO from the DATA terminal, and at time tl, the reception of the main data and the parity data Pt of the sector SO ends. With respect to the transmission time from time tO to time tl, since the data width of the DATA terminal dedicated for ECC and the frequency of the clock signal CK have been optimized for the ECC processing, the time can be shorter than the time for transmitting data via the input / output terminal 210 for SPI. Similarly, at time t2, the transmission of the main data and the parity data Pt of the sector SI ends, at time t3, the transmission of the main data and the parity data Pt of the sector S2 ends, and at time t4, the transmission of the main data and the parity data Pt of the sector S3 ends.

[0080] The data of the sectors SO to S3 received from the NAND chip 200 are sequentially held in the RAMO. At the same time as the data of the sector SO is held in the RAMO, the ECC core 360 starts calculating the syndrome of the sector SO. In some embodiments, the bit width of the DATA terminal or the frequency of the clock signal CK is set in such a manner that the syndrome calculation of the sector SO ends at time tl. After the syndrome is calculated, the ECC core 360 performs the error position polynomial calculation and the error position search for the sector SO in the reception of the sector SI.

[0081] At time t5, the ECC core 360 ​​reads the main data of sector S0 from RAM0 selected by selectors SEL4 and SEL5 in synchronization with the clock signal CLK, inverts bit errors in the main data of sector S0 using ExOR, and outputs the error-corrected main data of sector S0 from the DO terminal of the input / output terminal 330 to the controller chip 400 in synchronization with the SPI clock signal CLK. At times t6, t7, and t8, the ECC core 360 ​​performs error correction on sectors S1, S2, and S3, and sequentially outputs the error-corrected main data of sectors S1, S2, and S3 to the controller chip 400 via the input / output terminal 330. The CPU_IF of the controller chip 400 transmits the main data of sectors S0, S1, S2, and S3 received at times t6, t7, t8, and t9 to the host device. Although not shown here, after the transmission of sector S3, the transmission of data and error detection and correction of sectors S4 to S7 are performed in the same manner as described above.

[0082] Next, the continuous reading operation of pages of the flash memory according to this embodiment will be described. Figure 7 for Figure 4 (B) shows a timing diagram of a continuous read operation of a flash memory of a comparative example (latch L1 and latch L2 include buffers C0 and C1, respectively). Figure 8 1 is a timing diagram of the continuous read operation of the flash memory (latch L2 only includes buffer C1) of this embodiment.

[0083] Figure 7 、 Figure 8 In the figure, the upper half represents the action of the NAND chip 200, and the lower half represents the timing of the ECC chip 300. In the flash memory of the comparative example, the NAND chip 200 starts array reading of the next page after outputting the data of the final address of each page. For example, in response to the final data of sector S7 of page P0 being transmitted from the DATA terminal, the array reading of page P2 is started. The final address of the page is detected by counting the number of toggles of the clock signal CK by the address counter included in the ECC control unit 260. In addition, continuous reading actually starts from the reading of page P1 after the data of page P0 is transmitted to the latch L2.

[0084] The NAND chip 200 transfers the data of the sectors S0-S7 of each page to the ECC chip 300 in units of buffers during the period when the VALID signal is at the high level, and if the ECC chip 300 outputs the data of the sectors S0-S3 or the sectors S4-S7 from the DO terminal in units of buffers, the NAND chip 200 transfers the data of the next page to the ECC chip 300 in units of buffers in response to the timing. The timing at which the data is transferred from the NAND chip 200 to the ECC chip 300 becomes the timing at which the ECC chip 300 outputs the final address in units of buffers to the controller chip 400. For example, the NAND chip 200 starts to transfer the data of the sectors S0-S3 of the page PI in response to the ECC chip 300 outputting the final data of the sector S3 of the page PO.

[0085] As for the timing at which the ECC chip 300 outputs the final address in units of buffers to the controller chip 400, it is sufficient to recognize the number of toggles of the clock signal CLK connected to the NAND chip 200 using the address counter of the controller 270 in the NAND chip 200. The ADD counter in the controller 270 of the NAND chip 200 is used to control the data output from the CTL_IF 250 when the ECC chip 300 is not mounted or when error correction is not performed, but the data is not output from the CTL_IF 250 when error correction is performed, and thus it can be used for the purpose.

[0086] On the other hand, in the flash memory of the present embodiment, the array read of the memory array is performed in response to the output of the data of the initial address of the page from the terminal DO of the ECC chip 300 as shown in Figure 8 For example, if the data of the initial address of the sector S0 of the page PO is output from the terminal DO, the NAND chip 200 starts to read the array of the page PI.

[0087] The NAND chip 200 holds the data of the page read from the memory array in the buffers C0 and C1 of the latch Ll, and then transfers the data of the sectors S4-S7 of the buffer C1 of the latch Ll to the buffer C1 of the latch L2, and transfers the data of the sectors S0-S3 held in the buffer C0 of the latch Ll and the data of the sectors S4-S7 held in the buffer C1 of the latch L2 as one page data to the ECC chip 300 in units of buffers during the period when the VALID signal is at the high level. The timing at which the data is transferred from the NAND chip 200 to the ECC chip 300 is the same as in the case of the comparative example, and becomes the timing at which the ECC chip 300 outputs the data of the final address in units of buffers to the controller chip 400. For example, the NAND chip 200 starts to transfer the data of the sectors S0-S3 of the page PI in response to the ECC chip 300 outputting the data of the final address of the sector S3 of the page PO.

[0088] The ECC chip 300 performs error detection and correction on a sector-by-sector basis, then outputs the corrected data from the DO terminal. When the ECC chip 300 outputs data at the beginning of a page, the NAND chip 200 responds by starting to read the array for the next page and storing the read data in latch L1. When the array read for the next page begins, the data in buffer C1 of latch L1 is transferred to latch L2, so even if latch L1 overwrites the data of the next page, there is no problem.

[0089] The address counter of the controller 270 of the NAND chip 200 is synchronized with the address counter of the controller 380 of the ECC chip 300. The controller 270 of the NAND chip 200 can know the timing of the start address of the page output from the DO terminal of the ECC chip 300 through the column address counted by the address counter.

[0090] Next, the limitations of continuous readout from the flash memory of this embodiment are described. Here, the array readout time is tARRAY, the time it takes for the NAND chip 200 to output one sector's data is tDOUT1, the time it takes for the ECC chip 300 to output one sector's data is tDOUT2, and the latency from the time the NAND chip 200 outputs one sector's data until error detection and correction for that sector is completed is tLTCY.

[0091] In the flash memory of the comparative example, the limitations of formula (1) and formula (2) occur.

[0092] tDOUT1+tLTCY<tDOUT2×4···(1)

[0093] tDOUT1<tDOUT2···(2)

[0094] On the other hand, in the flash memory of this embodiment, as Figure 8 As shown, in addition to the restrictions of formula (1) and formula (2), restrictions of formula (3) and formula (4) also occur.

[0095] tARRAY+tDOUT1+tLTCY<tDOUT2×8···(3)

[0096] tARRAY+tDOUT1×4<tDOUT2×8···(4)

[0097] Here, if tARRAY = 16 μs, the data of one sector is 512 bytes, the bit width of the DATA terminal dedicated to ECC is set to 16 bits, and the frequency of the clock signal CK is set to 80 MHz, tDOUTl = 4 μs and tLTCY = 4 μs are obtained. At this time, the respective limits of the flash memory of the present embodiment are as follows.

[0098] According to (1), tDOUT2 > (4 + 4) / 4 = 2 μs is obtained.

[0099] According to (2), tDOUT2 > 4 μs is obtained.

[0100] According to (3), tDOUT2 > (16 + 4 + 4) / 8 = 3 μs is obtained.

[0101] According to (4), tDOUT2 > (16 + 4 x 4) / 8 = 4 μs is obtained.

[0102] At this time, the frequency of the clock signal CLK and / or the bit width of the DO terminal are set in such a manner that tDOUT2 is greater than 4 μs. Further, if tARRAY is shorter than the time for outputting the data of one buffer (four sectors), an additional limit is generated.

[0103] Figure 9 A timing chart in the case where an interruption occurs in the continuous readout of the page of the flash memory of the comparative example, Figure 10 A timing chart in the case where an interruption occurs in the continuous readout of the page of the flash memory of the present embodiment. For example, the clock signal CLK of the ECC chip 300 is stopped or the like, resulting in an interruption in the data output from the DO terminal in the continuous readout (interruption is shown at the DO terminal). In the case where such an interruption occurs, in the flash memory of the present embodiment, the RAMO and the RAMl of the ECC chip 300 hold the data transmitted from the NAND chip 200, and, before the ECC chip 300 outputs the data of the beginning address of the page, the array readout of the next page is not performed, so that the data of the previous page is held in the latch Ll and the latch L2. Therefore, the data does not disappear due to the interruption, and the NAND chip 200 and the ECC chip 300 share the address of the page which is being readout, so that the continuous readout can be started again after the interruption.

[0104] Next, a second embodiment of the present application will be described. The first embodiment shows a configuration in which the storage capacity (data size) of the latch L2 of the page buffer / sense circuit of the NAND chip 200 is reduced to half of the buffer C1, and in the second embodiment, the storage capacity of the buffer C1 of the latch L2 is further halved. That is, the buffer C1 of the latch L2 of the present embodiment holds 1 / 4 page data. For example, if one page is 4 KB, the C1 of the latch L2 is 1 KB. The data size of the buffer C1 of the latch L2 becomes half of the data size of the buffer C1 of the latch Ll, and thus the data that the buffer C1 of the latch L2 receives from the buffer C1 of the latch Ll at one time becomes 1 / 4 page data (data of two sectors). That is, the buffer C0 of the latch Ll holds data of the sectors S0 to S3, and the buffer C1 of the latch Ll holds data of the sectors S4 to S7. Next, 3 / 4 page data of the sectors S0 to S5 held by the buffers C0, C1 of the latch Ll is transferred to the ECC chip 300, and the data of the sectors S6, S7 held by the buffer C1 of the latch Ll is transferred to the buffer C1 of the latch L2. The buffer C1 of the latch L2 holds data of the sectors S6, S7, and 1 / 4 page data of the sectors S6, S7 held by the buffer C1 of the latch L2 is transferred to the ECC chip 300.

[0105] In the first embodiment, the data transfer between the NAND chip 200 and the ECC chip 300 is performed in units of buffers (sectors S0 to S3 / sectors S4 to S7), but in the second embodiment, the data transfer is performed in units of 1 / 4 page or two sectors. Therefore, the ECC control section 260 of the NAND chip 200 generates the VALID signal that specifies the data transfer period in units of two sectors or in units of 1 / 4 page.

[0106] Figure 11 A timing chart showing the continuous readout operation of the flash memory of the second embodiment will be described. As shown in the figure, in the continuous readout of the present embodiment, as in the first embodiment, the array readout of the memory array is performed in response to the data of the start address of the page output from the DO terminal of the ECC chip 300, and the data transfer from the NAND chip 200 to the ECC chip 300 is performed in response to the data of the start address of two sectors output from the DO terminal of the ECC chip 300. For example, in response to the data of the start address of the sector S0 of the page PO output from the DO terminal of the ECC chip 300, the array readout of the page Pl is performed, and next, in response to the data of the start address of the sector S2 of the page PO, the data transfer of two sectors S0, S1 of the page Pl from the NAND chip 200 to the ECC chip 300 is started.

[0107] Next, the restriction at the time of continuous readout of the flash memory of the second embodiment will be described. Assume that one buffer contains four sectors, set the time of array readout to tARRAY, set the time of data output of one sector from the NAND chip 200 to tDOUTl, and set the time of data output of one sector from the ECC chip 300 to tDOUT2. The restriction at the time of the first embodiment is shown in Equation (1), and the restriction of the second embodiment is shown in Equation (2).

[0108] tARRAY + tDOUTl x 4 < tDOUT2 x 8... (1)

[0109] tARRAY + tDOUTl x 6 < tDOUT2 x 8... (2)

[0110] Here, if tARRAY = 16 μs, the data of one sector is 512 bytes, the bit width of the DATA terminal dedicated to ECC is set to 16 bits, and the frequency of the clock signal CK is set to 80 MHz, then tDOUTl = 4 μs. At this time, the restriction of Equation (2) is as follows.

[0111] tDOUT2 > (16 + 4 x 6) / 8 = 5 μs

[0112] The restriction means that, for example, if it is a product of the SDR type of the input / output terminal x 4, the frequency of the serial clock signal of 200 MHz can be supported.

[0113] Figure 12 A timing chart in the case where an interruption occurs in the continuous readout of the page of the flash memory of the second embodiment. Even if the readout clock signal CLK of the ECC chip 300 is stopped to cause an interruption in readout, the data does not disappear due to overwriting or the like, and the continuous readout can be correctly started again after the interruption.

[0114] Thus, according to the second embodiment, by further reducing the data size of the latch L2 of the page buffer / sense circuit, it is possible to reduce the chip size of the NAND chip 200, and miniaturization and space saving of the flash memory can be achieved.

[0115] Further, in the embodiments, an example in which one page contains eight sectors (one buffer contains four sectors) is shown, but this is an example, and, for example, when one page is 4 KB (one buffer is 2 KB), if one sector is 512 bytes, one page contains eight sectors, and if one page is 2 KB, one page can also contain four sectors. At this time, the ECC chip 300 performs ECC processing in units of sectors (in the programming operation, parity data is generated for each sector, and in the readout operation, error detection and correction of the sector are performed based on the parity data).

[0116] The preferred embodiments of the present application are described in detail, but the present application is not limited to the specific embodiments, and various modifications, changes can be made within the scope of the gist of the present application described in the claims.

Claims

1. A semiconductor memory device comprising: A NAND chip comprising a NAND memory array, a page buffer / sensing circuit, and a control unit, wherein the page buffer / sensing circuit comprises a first latch and a second latch capable of holding page data read from the memory array, and the control unit controls a read operation; and Error detection and correction chip, including error detection and correction functions, The first latch includes: a first holding portion for holding a first data portion of the page data; and a second holding portion for holding a second data portion. The second latch has a smaller data size than the first latch and holds a second data portion transmitted from a second holding portion of the first latch, After the control unit transmits the first data portion held in the first holding portion of the first latch to the error detection and correction chip, the control unit transmits the second data portion held in the second latch to the error detection and correction chip. The error detection and correction chip performs error detection and correction on the first data portion and the second data portion. The control unit reads a next page from the memory array in response to a timing when the error detection and correction chip outputs the first data portion to the outside.

2. The semiconductor memory device according to claim 1, wherein The NAND chip comprises: a first dedicated terminal for transmitting read data to the error detection and correction chip; The error detection and correction chip includes a second dedicated terminal connected to the first dedicated terminal for receiving the read data.

3. The semiconductor memory device according to claim 1 or 2, wherein: The first holding portion and the second holding portion each have a storage capacity for holding 1 / 2 page data, the second latch has a storage capacity for holding 1 / 2 page data, and the control unit transmits data to the error detection and correction chip in units of 1 / 2 page.

4. The semiconductor memory device according to claim 3, wherein When a page contains n sectors and the error detection and correction chip performs data error detection and correction in units of sectors, the following restrictions are imposed: tARRAY is the read time of the memory array, tDOUT1 is the time for the NAND chip to transmit data of one sector to the error detection and correction chip, tDOUT2 is the time for the error detection and correction chip to output data of one sector to the outside, and tLTCY is the delay from the time the NAND chip outputs data of one sector until error detection and correction of the sector is completed. tDOUT1+tLTCY<tDOUT2×n / 2···(1) tDOUT1<tDOUT2···(2) tARRAY+tDOUT1+tLTCY<tDOUT2×n···(3) tARRAY+tDOUT1×n / 2<tDOUT2×n···(4).

5. The semiconductor memory device according to claim 1 or 2, wherein The first holding portion and the second holding portion each have a storage capacity for holding 1 / 2 page data, the second latch has a storage capacity for holding 1 / 4 page data, and the control unit transmits data to the error detection and correction chip in units of 1 / 4 page. The semiconductor memory device according to claim 5 , wherein: When a page contains n sectors and the error detection and correction chip performs data error detection and correction in units of sectors, assuming that the memory array read time is tARRAY, the time for the NAND chip to transmit one sector's data to the error detection and correction chip is tDOUT1, and the time for the error detection and correction chip to output one sector's data to the outside is tDOUT2, the following restrictions apply: tARRAY+tDOUT1×(n×3 / 4)<tDOUT2×n.

7. The semiconductor memory device according to claim 2, wherein The NAND chip transmits the first data portion and the second data portion to the error detection and correction chip from the first dedicated terminal in synchronization with the first clock signal. The error detection and correction chip outputs the corrected data to the outside in synchronization with the second clock signal.

8. The semiconductor memory device according to claim 1, wherein The control unit controls the continuous reading of pages.

9. The semiconductor memory device according to claim 1, wherein The NAND chip and the error detection and correction chip are housed in one package.

10. A readout method for a semiconductor memory device, the semiconductor memory device comprising: A NAND chip includes a NAND memory array and a page buffer / sensing circuit, wherein the page buffer / sensing circuit includes a first latch and a second latch capable of holding page data read from the memory array; and an error detection and correction chip including an error detection and correction function for data transmitted from the NAND chip, and In the NAND chip, the first data portion and the second data portion of the page read from the memory array are held in the first latch, the second data portion held in the first latch is transferred to the second latch, the first data portion held in the first latch is transferred to the error detection and correction chip, and then the second data portion held in the second latch is transferred to the error detection and correction chip. In the error detection and correction chip, after performing error detection and correction on the first data portion, error detection and correction on the second data portion is performed. In response to the error detection and correction chip outputting the error-corrected first data portion, the next page is read out from the memory array in the NAND chip. The readout method according to claim 10 , wherein: In the NAND chip, the first data portion and the second data portion are transmitted from a first dedicated terminal to the error detection and correction chip in synchronization with a clock signal. In the error detection and correction chip, the first data portion and the second data portion are received from a second dedicated terminal in synchronization with the clock signal.

12. The readout method according to claim 10, wherein: The first data portion and the second data portion are each 1 / 2 page data, the second latch receives 1 / 2 page data from the first latch, and the NAND chip transmits the first data portion or the second data portion to the error detection and correction chip in units of 1 / 2 page.

13. The readout method according to claim 10, wherein: When a page contains n sectors and the error detection and correction chip performs data error detection and correction in units of sectors, the following restrictions are imposed: tARRAY is the read time of the memory array, tDOUT1 is the time for the NAND chip to transmit data of one sector to the error detection and correction chip, tDOUT2 is the time for the error detection and correction chip to output data of one sector to the outside, and tLTCY is the delay from the time the NAND chip outputs data of one sector until error detection and correction of the sector is completed. tDOUT1+tLTCY<tDOUT2×n / 2···(1) tDOUT1<tDOUT2···(2) tARRAY+tDOUT1+tLTCY<tDOUT2×n···(3) tARRAY+tDOUT1×n / 2<tDOUT2×n···(4).

14. The readout method according to claim 10, wherein: The first data portion and the second data portion are each 1 / 2 page data, the second latch receives 1 / 4 page data from the first latch, and the NAND chip transmits the first data portion or the second data portion to the error detection and correction chip in units of 1 / 4 page.

15. The readout method according to claim 14, wherein: When a page contains n sectors and the error detection and correction chip performs data error detection and correction in units of sectors, assuming that the memory array read time is tARRAY, the time for the NAND chip to transmit one sector's data to the error detection and correction chip is tDOUT1, and the time for the error detection and correction chip to output one sector's data to the outside is tDOUT2, the following restrictions apply: tARRAY+tDOUT1×(n×3 / 4)<tDOUT2×n.

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