UMOSFET device and method for improving performance of UMOSFET device

Abstract

The present invention discloses a UMOSFET device and a method for improving the performance of a UMOSFET device. The β-Ga2O3 UMOSFET device includes an epitaxial structure and a source, a drain, and a gate that cooperate with the epitaxial structure. The epitaxial structure includes an N-type gallium oxide drift layer, a current blocking layer, and a first N-type gallium oxide epitaxial layer that are stacked in sequence. In addition, a groove structure is further provided in the epitaxial structure, wherein the groove opening of the groove structure is provided on the surface of the first N-type gallium oxide epitaxial layer and the groove bottom is provided in the N-type gallium oxide drift layer; and a second N-type gallium oxide epitaxial layer is continuously provided on the groove wall of the groove structure. The vertical β-Ga2O3 UMOSFET device provided by the present invention has a higher saturation current density, a smaller gate-source leakage current, and can operate at high voltage.

Description

Technical Field

[0001] The present invention particularly relates to a β-Ga2O3 UMOSFET device and a method for improving the performance of the β-Ga2O3 UMOSFET device, belonging to the technical field of semiconductor power devices. Background Art

[0002] In recent years, as the fundamental performance of silicon technology has reached its limits, there has been a surge of interest in developing electronic devices based on wide-bandgap compound semiconductors. β-Ga2O3, with its ultra-wide bandgap of ~4.9 eV and high critical breakdown field strength of 8 MV / cm, has sparked a wave of research. Experimentally, β-Ga2O3 has demonstrated a critical field strength of at least 5 MV / cm, exceeding the theoretical values ​​of GaN and SiC. This technology offers a compelling blueprint for future high-voltage and high-power electronic systems by increasing device-level power density and power conversion efficiency while reducing size and weight. Ga2O3 also exhibits thermal stability and radiation resistance, making it particularly suitable for building equipment and systems that must operate reliably in harsh environments, such as aerospace, detectors, measurement, and nuclear technology. The rapid development of these emerging Ga2O3 technologies is driven by the availability of melt-grown gallium oxide substrates, whose high quality and large size offer Ga2O3 a unique and significant cost advantage over wide-bandgap semiconductors such as GaN and SiC.

[0003] To date, reported β-Ga2O3 metal-oxide semiconductor field-effect transistors (MOSFETs) have almost exclusively been implemented as lateral structures, with off-state breakdown voltages exceeding 750V for depletion-mode and 600V for enhancement-mode devices, respectively. For high-voltage, high-power applications, vertical structures are preferred because the peak electric field is buried in the bulk, avoiding premature device failure caused by surface flashovers and mitigating performance instabilities caused by surface states. Furthermore, the breakdown voltage of vertical MOSFETs scales with the drift layer thickness, rather than the lateral gate-drain separation, meaning higher breakdown voltages can be achieved without sacrificing chip area or current density. However, due to the lack of p-type β-Ga2O3, early research on vertical Ga2O3 MOSFETs employed non-planar fin structures with side-gate modulation to circumvent the need for pn junction isolation between the source and drain. Compared to trench-gate FinFET geometries, planar gate structures avoid reliability issues caused by increased field stress on the gate oxide at the channel corners and eliminate concerns about a poor MOS interface caused by dry-etch damage to the channel sidewalls. The current aperture vertical electron transistor (CAVET) is also one of the methods to realize vertical enhancement mode Ga2O3 MOSFET.

[0004] A structure of a current aperture vertical electron transistor (CAVET) in the prior art is as follows:Figure 1 As shown in the figure, it primarily uses ion implantation to implant Mg or N ions into the Ga2O3 drift layer to form a current blocking layer. A highly doped Ga2O3 thin film is then formed on top of the Ga2O3 drift layer via epitaxy or Si ion implantation to form an ohmic contact with the source electrode. Finally, gate metal and source / drain metals are deposited to successfully fabricate a vertical Ga2O3 MOSFET device with a planar gate structure. The device primarily turns off by depleting electrons beneath the gate metal. A positive voltage is then applied to the gate metal to form an electron accumulation layer in the channel region, turning the device on. However, CAVET suffers from gate-source leakage issues and low current density, making it difficult to meet the requirements of a high breakdown voltage. Summary of the Invention

[0005] The main purpose of the present invention is to provide a β-Ga2O3 UMOSFET device and a method for improving the performance of the β-Ga2O3 UMOSFET device, thereby overcoming the deficiencies in the prior art.

[0006] To achieve the aforementioned object of the invention, the technical solutions adopted by the present invention include:

[0007] In one aspect, the present invention provides a β-Ga2O3 UMOSFET device, comprising an epitaxial structure and a source, a drain and a gate matched with the epitaxial structure.

[0008] The epitaxial structure includes an N-type gallium oxide drift layer, a current blocking layer, and a first N-type gallium oxide epitaxial layer stacked in sequence, and a groove structure is further provided in the epitaxial structure, wherein the groove opening of the groove structure is provided on the surface of the first N-type gallium oxide epitaxial layer and the groove bottom is provided in the N-type gallium oxide drift layer; and a second N-type gallium oxide epitaxial layer is continuously provided on the groove wall of the groove structure, and the conductive channel of the β-Ga2O3 UMOSFET device is located in the second N-type gallium oxide epitaxial layer;

[0009] At least a portion of the gate is within the groove structure, and the gate and the second N-type gallium oxide epitaxial layer are isolated by a dielectric layer, and the source is electrically coupled to the first N-type gallium oxide epitaxial layer.

[0010] Another aspect of the present invention provides a method for improving the performance of a β-Ga2O3 UMOSFET device, comprising the steps of fabricating an epitaxial structure and fabricating a source, a drain, and a gate matching the epitaxial structure. The steps of fabricating the epitaxial structure include:

[0011] forming an N-type gallium oxide drift layer, a current blocking layer, and a first N-type gallium oxide epitaxial layer stacked in sequence;

[0012] Fabricating a groove-shaped structure, with the groove opening of the groove-shaped structure being arranged on the surface of the first N-type gallium oxide epitaxial layer and the groove bottom being arranged in the N-type gallium oxide drift layer;

[0013] forming a second N-type gallium oxide epitaxial layer, and continuously covering the groove wall of the groove structure with the second N-type gallium oxide epitaxial layer, wherein the conductive channel of the β-Ga2O3 UMOSFET device is located in the second N-type gallium oxide epitaxial layer;

[0014] At least a portion of the gate is within the groove structure, the gate and the second N-type gallium oxide epitaxial layer are isolated by a dielectric layer, and the source is electrically coupled to the first N-type gallium oxide epitaxial layer.

[0015] Compared with the prior art, the advantages of the present invention include:

[0016] 1) The vertical β-Ga2O3 UMOSFET device provided by the present invention has a higher saturation current density; compared with the CAVET device, the vertical β-Ga2O3 UMOSFET device provided by the present invention has a higher current density, lower gate-source leakage current, and can operate at high voltage.

[0017] 2) The present invention provides a vertical β-Ga2O3 UMOSFET device whose conductive channel is located in the unintentionally doped β-Ga2O3 epitaxial layer on the sidewall of the groove structure. By increasing the N ion implantation concentration in the high-resistance region of the β-Ga2O3 drift layer, the leakage current of the device in the off state can be reduced while avoiding an increase in the device threshold voltage.

[0018] 3) The present invention provides a vertical β-Ga2O3 UMOSFET device that transfers the conductive channel from the ion-implanted region to the unintentionally doped β-Ga2O3 epitaxial layer located on the sidewalls of the groove structure, effectively lowering the device's threshold voltage. As the gate voltage increases, the conductive channel expands toward the current-blocking layer, significantly improving the device's saturation current density.

[0019] 4) The present invention provides a method for improving the performance of β-Ga2O3 UMOSFET devices, wherein a secondary epitaxial growth is performed on the walls of the etched groove structure to form an unintentionally doped β-Ga2O3 epitaxial layer. Due to the presence of many dangling bonds on the surface of the groove wall of the groove structure, a high-quality unintentionally doped β-Ga2O3 epitaxial layer can be obtained, thereby improving the MOS interface and avoiding the problem of reduced carrier mobility caused by surface etching.

[0020] 5) The present invention provides a method for improving the performance of β-Ga2O3 UMOSFET devices. By depositing a p-type epitaxial layer such as p-NiO and an unintentionally doped β-Ga2O3 epitaxial layer to form a PN junction, the device's field intensity concentration area can be shifted from the dielectric layer to the PN junction depletion region, significantly improving the device's breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic structural diagram of a current aperture vertical electron transistor (CAVET) in the prior art;

[0022] Figure 2 1 is a schematic structural diagram of a β-Ga2O3 UMOSFET device provided in a typical embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of the manufacturing process of a β-Ga2O3 UMOSFET device provided in a typical embodiment of the present invention;

[0024] Figure 4a 、 Figure 4b 、 Figure 4c They are respectively the transfer curve, output curve and breakdown curve of a β-Ga2O3 UMOSFET device in Example 1;

[0025] Figure 5a 、 Figure 5b 、 Figure 5c They are respectively the transfer curve, output curve and breakdown curve of a β-Ga2O3 UMOSFET device in Example 2;

[0026] Figure 6a 、 Figure 6b 、 Figure 6c They are respectively the transfer curve, output curve and breakdown curve of a β-Ga2O3 UMOSFET device in Example 3. DETAILED DESCRIPTION

[0027] In view of the shortcomings of the prior art, the inventors of this case, after long-term research and extensive practice, have proposed the technical solution of the present invention. The following will further explain this technical solution, its implementation process and principles.

[0028] The present invention provides a β-Ga2O3 UMOSFET device. This device forms an unintentionally doped epitaxial layer by performing secondary epitaxy on the walls of a trench structure of the β-Ga2O3 UMOSFET device, thereby transferring the device's conductive channel from an ion implantation region (i.e., a current blocking layer) to the unintentionally doped epitaxial layer, thereby increasing the saturation current. Furthermore, because the number of electrons in the unintentionally doped epitaxial layer formed by the secondary epitaxy is much higher than that in the high-resistance region of the drift layer, sufficient electrons can be accumulated at a very low gate voltage to promote device conduction, thereby reducing the device's threshold voltage. Furthermore, a PN junction formed by the P-type epitaxial layer deposited at the bottom of the trench structure and the unintentionally doped epitaxial layer is utilized to increase the device's breakdown voltage. Using the PN junction to increase the breakdown voltage is of great significance for improving the performance of Ga2O3-based power devices.

[0029] In one aspect, the present invention provides a β-Ga2O3 UMOSFET device, comprising an epitaxial structure and a source, a drain and a gate matched with the epitaxial structure.

[0030] The epitaxial structure includes an N-type gallium oxide drift layer, a current blocking layer, and a first N-type gallium oxide epitaxial layer stacked in sequence, and a groove structure is further provided in the epitaxial structure, wherein the groove opening of the groove structure is provided on the surface of the first N-type gallium oxide epitaxial layer and the groove bottom is provided in the N-type gallium oxide drift layer; and a second N-type gallium oxide epitaxial layer is continuously provided on the groove wall of the groove structure, and the conductive channel of the β-Ga2O3 UMOSFET device is located in the second N-type gallium oxide epitaxial layer;

[0031] At least a portion of the gate is disposed in the groove-shaped structure, and the gate is isolated from the second N-type gallium oxide epitaxial layer by a dielectric layer, and the source is electrically coupled to the first N-type gallium oxide epitaxial layer.

[0032] Furthermore, the second N-type gallium oxide epitaxial layer is unintentionally doped, the first N-type gallium oxide epitaxial layer is highly doped, and the doping concentration of the second N-type gallium oxide epitaxial layer is lower than the doping concentration of the first N-type gallium oxide epitaxial layer.

[0033] Furthermore, the lower the carrier concentration of the second N-type gallium oxide epitaxial layer, the better. Specifically, the doping concentration of the second N-type gallium oxide epitaxial layer can be 5×10 15 cm -3 ~2×10 16 cm -3 The first N-type gallium oxide epitaxial layer needs to be highly doped. Specifically, the doping concentration of the first N-type gallium oxide epitaxial layer is 1×10 19 cm -3 ~5×1019 cm -3 If the doping concentration of the second N-type gallium oxide epitaxial layer is too high, the leakage of the device will increase. Therefore, the doping concentration of the second N-type gallium oxide epitaxial layer is preferably controlled below 15.

[0034] Furthermore, the thickness of the second N-type gallium oxide epitaxial layer is 100-200 nm, and the thickness of the first N-type gallium oxide epitaxial layer is 100-300 nm.

[0035] Furthermore, the epitaxial structure also includes a P-type epitaxial layer, which is disposed at the bottom of the trench structure, and the P-type epitaxial layer is stacked on the second N-type gallium oxide epitaxial layer. The P-type epitaxial layer forms a PN junction with the second N-type gallium oxide epitaxial layer and the N-type gallium oxide drift layer covered by the second N-type gallium oxide epitaxial layer. The carrier concentration of the P-type epitaxial layer is on the order of 18, while the gallium oxide concentrations of the second N-type gallium oxide epitaxial layer and the N-type gallium oxide drift layer are both on the order of 16. Therefore, the depletion region width of the PN junction is approximately 300nm-400nm, which exceeds the thickness of the second N-type gallium oxide epitaxial layer.

[0036] Furthermore, the material of the P-type epitaxial layer includes p-NiO, etc., but is not limited thereto.

[0037] Furthermore, the thickness of the P-type epitaxial layer is 50-150 nm.

[0038] Furthermore, the P-type epitaxial layer and the gate are also isolated by the dielectric layer.

[0039] Furthermore, the current blocking layer is a high resistance region formed by converting the surface region of the N-type gallium oxide drift layer into a compensating acceptor material.

[0040] Furthermore, the compensation acceptor material includes N ions or Mg ions, but is not limited thereto.

[0041] Furthermore, the concentration of the compensation acceptor material in the current blocking layer is 1×10 18 cm -3 ~1×10 19 cm -3 .

[0042] Furthermore, the thickness of the current blocking layer is 300-600 nm, and the thickness of the N-type gallium oxide drift layer is 4-10 μm.

[0043] Furthermore, the depth of the groove structure is 800-1000 nm.

[0044] Furthermore, the groove structure is a U-shaped groove, a V-shaped groove, an inverted trapezoidal groove, etc., but is not limited thereto.

[0045] Furthermore, the N-type gallium oxide drift layer is provided on an N-type gallium oxide substrate, and the drain is provided on a surface of the N-type gallium oxide substrate away from the N-type gallium oxide drift layer and forms an ohmic contact with the N-type gallium oxide substrate.

[0046] Furthermore, the carrier concentration of the first N-type gallium oxide epitaxial layer is greater than the carrier concentration of the N-type gallium oxide substrate and greater than the carrier concentration of the N-type gallium oxide drift layer.

[0047] Furthermore, the materials of the N-type gallium oxide substrate, the N-type gallium oxide drift layer, the first N-type gallium oxide epitaxial layer, and the second N-type gallium oxide epitaxial layer all include β-Ga2O3.

[0048] Another aspect of the present invention provides a method for improving the performance of a β-Ga2O3 UMOSFET device, comprising the steps of fabricating an epitaxial structure and fabricating a source, a drain, and a gate matching the epitaxial structure. The steps of fabricating the epitaxial structure include:

[0049] forming an N-type gallium oxide drift layer, a current blocking layer, and a first N-type gallium oxide epitaxial layer stacked in sequence;

[0050] Fabricating a groove-shaped structure, with the groove opening of the groove-shaped structure being arranged on the surface of the first N-type gallium oxide epitaxial layer and the groove bottom being arranged in the N-type gallium oxide drift layer;

[0051] forming a second N-type gallium oxide epitaxial layer, and continuously covering the groove wall of the groove structure with the second N-type gallium oxide epitaxial layer, wherein the conductive channel of the β-Ga2O3 UMOSFET device is located in the second N-type gallium oxide epitaxial layer;

[0052] At least part of the gate is disposed in the groove structure, the gate and the second N-type gallium oxide epitaxial layer are isolated by a dielectric layer, and the source is electrically coupled to the first N-type gallium oxide epitaxial layer.

[0053] Furthermore, the second N-type gallium oxide epitaxial layer is unintentionally doped, the first N-type gallium oxide epitaxial layer is highly doped, and the doping concentration of the second N-type gallium oxide epitaxial layer is lower than the doping concentration of the first N-type gallium oxide epitaxial layer.

[0054] Furthermore, the doping concentration of the second N-type gallium oxide epitaxial layer is 5×10 15 cm -3 ~2×10 16 cm -3 The doping concentration of the first N-type gallium oxide epitaxial layer is 1×10 19 cm -3 ~5×1019 cm -3 .

[0055] Furthermore, the thickness of the second N-type gallium oxide epitaxial layer is 100-200 nm, and the thickness of the first N-type gallium oxide epitaxial layer is 100-300 nm.

[0056] Furthermore, the step of making the epitaxial structure also includes: forming a P-type epitaxial layer at the bottom of the groove of the groove structure, and stacking the P-type epitaxial layer on the second N-type gallium oxide epitaxial layer, and forming a PN junction between the P-type epitaxial layer, the second N-type gallium oxide epitaxial layer, and the layer covered by the second N-type gallium oxide epitaxial layer.

[0057] Furthermore, the material of the P-type epitaxial layer includes p-NiO, etc., but is not limited thereto.

[0058] Furthermore, the thickness of the P-type epitaxial layer is 50-150 nm.

[0059] Furthermore, the gate and the P-type epitaxial layer are also isolated by the dielectric layer.

[0060] Furthermore, the method specifically includes: injecting a compensation acceptor material into the surface region of the N-type gallium oxide drift layer and activating the compensation acceptor material to deplete electrons in the surface region of the N-type gallium oxide drift layer to form a high-resistance current blocking layer.

[0061] Furthermore, the method specifically includes: injecting a compensating acceptor material into the surface region of the N-type gallium oxide drift layer, and then annealing at 1000-1200°C for 30-60 minutes to activate the compensating acceptor material and deplete the electrons in the surface region, thereby forming a high-resistance current blocking layer.

[0062] Furthermore, the compensation acceptor material includes N ions or Mg ions.

[0063] Furthermore, the concentration of the compensation acceptor material in the current blocking layer is 1×10 18 cm -3 ~1×10 19 cm -3 .

[0064] Furthermore, the thickness of the current blocking layer is 300-600 nm, and the thickness of the N-type gallium oxide drift layer is 4-10 μm.

[0065] In a specific embodiment, the method includes: first forming a SiO2 layer with a thickness of about 100 nm on the surface of the N-type gallium oxide drift layer as an ion implantation sacrificial layer, then implanting a compensating acceptor material into a surface region of the N-type gallium oxide drift layer near the ion implantation sacrificial layer, thereby forming a high resistance region 300-600 nm away from the surface of the N-type gallium oxide drift layer, and then removing the ion implantation sacrificial layer.

[0066] Furthermore, the material of the ion implantation sacrificial layer includes but is not limited to silicon oxide.

[0067] Furthermore, the thickness of the ion implantation sacrificial layer is 50-200 nm.

[0068] In a specific embodiment, the method includes: directly epitaxially growing a highly doped β-Ga2O3 epitaxial layer on the current blocking layer as the first N-type gallium oxide epitaxial layer, or first epitaxially growing a β-Ga2O3 epitaxial layer on the current blocking layer, and then using ion implantation to transform the β-Ga2O3 epitaxial layer into a highly doped β-Ga2O3 epitaxial layer as the first N-type gallium oxide epitaxial layer.

[0069] For example, the β-Ga2O3 epitaxial layer or the highly doped β-Ga2O3 epitaxial layer can be grown by MOCVD (metal organic chemical vapor deposition), CVD (chemical vapor deposition) or MBE (molecular beam epitaxy).

[0070] In a specific embodiment, the preparation method includes: injecting Si ions into the β-Ga2O3 epitaxial layer to transform the β-Ga2O3 epitaxial layer into a highly doped β-Ga2O3 epitaxial layer.

[0071] Furthermore, the depth of the groove structure is 800-1000 nm.

[0072] Furthermore, the groove structure is a U-shaped groove, a V-shaped groove or an inverted trapezoidal groove.

[0073] Furthermore, the N-type gallium oxide drift layer is provided on an N-type gallium oxide substrate, and the drain is provided on a surface of the N-type gallium oxide substrate away from the N-type gallium oxide drift layer and forms an ohmic contact with the N-type gallium oxide substrate.

[0074] Furthermore, the carrier concentration of the first N-type gallium oxide epitaxial layer is greater than the carrier concentration of the N-type gallium oxide substrate and greater than the carrier concentration of the N-type gallium oxide drift layer.

[0075] Furthermore, the materials of the N-type gallium oxide substrate, the N-type gallium oxide drift layer, the first N-type gallium oxide epitaxial layer, and the second N-type gallium oxide epitaxial layer all include β-Ga2O3.

[0076] The technical solution, its implementation process and principles, etc. will be further explained below in conjunction with the accompanying drawings and specific implementation cases. Unless otherwise specified, the semiconductor epitaxial growth equipment, etching process and etching equipment, ion implantation equipment, metal deposition equipment, annealing equipment, etc. used in the embodiments of the present invention are all known to those skilled in the art, and their specific equipment models are not limited here.

[0077] For more specific implementations, see Figure 2 A β-Ga2O3 UMOSFET device comprises an epitaxial structure and a source 81, a drain 82 and a gate 83 matched with the epitaxial structure.

[0078] The epitaxial structure includes a β-Ga2O3 substrate 10, a β-Ga2O3 drift layer 20, a current blocking layer 30, a highly doped β-Ga2O3 epitaxial layer 40 and an unintentionally doped β-Ga2O3 epitaxial layer 50, wherein the β-Ga2O3 substrate 10, the β-Ga2O3 drift layer 20, the current blocking layer 30 and the highly doped β-Ga2O3 epitaxial layer 40 are stacked in sequence;

[0079] A groove structure 101 is provided in the region of the epitaxial structure corresponding to the gate 83 (which can be understood as the gate region). The groove opening of the groove structure 101 is provided on the surface of the highly doped β-Ga2O3 epitaxial layer 40 facing away from the current blocking layer 30, and the groove bottom is provided in the β-Ga2O3 drift layer 20. The unintentionally doped β-Ga2O3 epitaxial layer 50 is continuously covered on the groove wall (including the groove bottom and sidewalls) of the groove structure 101.

[0080] A portion of the gate 83 is disposed within the groove structure 101, and another portion is disposed on the highly doped β-Ga2O3 epitaxial layer 40 located outside the groove structure 101, and the gate 83 is isolated from the highly doped β-Ga2O3 epitaxial layer 40 and the unintentionally doped β-Ga2O3 epitaxial layer 50 by a dielectric layer 70. The source 81 is disposed on the highly doped β-Ga2O3 epitaxial layer 40 and forms an ohmic contact with the highly doped β-Ga2O3 epitaxial layer 40. The drain 60 is disposed on a surface of the β-Ga2O3 substrate 10 that is opposite to the β-Ga2O3 drift layer 20 and forms an ohmic contact with the β-Ga2O3 substrate 10.

[0081] Among them, the conductivity types of the β-Ga2O3 substrate 10, the β-Ga2O3 drift layer 20, the highly doped β-Ga2O3 epitaxial layer 40, and the unintentionally doped β-Ga2O3 epitaxial layer 50 are all n-type, and the current blocking layer 30 is a high resistance region formed after electrons are depleted.

[0082] Specifically, the unintentionally doped β-Ga2O3 epitaxial layer 50 changes the corner of the bottom of the groove structure from a right angle to a shape with a certain arc, which suppresses the local field concentration and promotes the improvement of the breakdown voltage.

[0083] The present invention can still achieve enhancement mode by controlling the carrier concentration in the unintentionally doped β-Ga2O3 epitaxial layer 50, and transfer the conductive channel to the unintentionally doped β-Ga2O3 epitaxial layer 50, so that the saturation current of the device can be increased from 500A / cm 2 ~700A / cm 2 Increased to 1000A / cm 2 ~1500A / cm 2 .

[0084] Specifically, the doping concentration of the unintentionally doped β-Ga2O3 epitaxial layer 50 is less than the doping concentration of the highly doped β-Ga2O3 epitaxial layer 40, wherein the doping concentration of the unintentionally doped β-Ga2O3 epitaxial layer 50 is 5×10 15 cm -3 ~2×10 16 cm -3 The doping concentration of the highly doped β-Ga2O3 epitaxial layer 40 is 1×10 19 cm -3 ~5×10 19 cm -3 .

[0085] Specifically, the first N-type gallium oxide epitaxial layer can ensure good ohmic contact, and the second N-type gallium oxide epitaxial layer can reduce the interface state density of the etched sidewall.

[0086] Specifically, the thickness of the unintentionally doped β-Ga2O3 epitaxial layer 50 is 100-200 nm, and the thickness of the highly doped β-Ga2O3 epitaxial layer 40 is 100-300 nm.

[0087] Specifically, a P-type epitaxial layer 60 is further provided at the bottom of the groove-shaped structure 101, and the P-type epitaxial layer 60 is stacked on the unintentionally doped β-Ga2O3 epitaxial layer 50 and forms a PN junction with the unintentionally doped β-Ga2O3 epitaxial layer 50 and the β-Ga2O3 drift layer 20 covered by the unintentionally doped β-Ga2O3 epitaxial layer 50. The P-type epitaxial layer 60 and the gate 83 are also isolated by the dielectric layer 70. Through the formed PN junction, the field strength concentration area can be transferred from the dielectric layer to the PN junction, thereby increasing the breakdown voltage of the device from 300V~500V to 700V~1000V.

[0088] Specifically, the material of the P-type epitaxial layer 60 includes a P-type material such as p-NiO, and the thickness of the P-type epitaxial layer is 50-150 nm.

[0089] Specifically, the current blocking layer 30 is a high resistance region formed by injecting a compensating acceptor material into the surface region of the β-Ga2O3 drift layer 20 (the surface region of the β-Ga2O3 drift layer 20 facing away from the β-Ga2O3 substrate). The compensating acceptor material can be N ions or Mg ions, etc. The concentration of the compensating acceptor material in the current blocking layer 30 is 1×10 18 cm -3 ~1×10 19 cm -3 .

[0090] Specifically, the present invention utilizes N ion and other compensating acceptor material injection techniques to deplete electrons in the drift layer, thereby fabricating a vertical enhancement-mode β-Ga2O3 UMOSFET device. Specifically, electron depletion can be achieved by injecting N ions or Mg ions, such as compensating acceptors, into the β-Ga2O3 drift layer. A high-concentration β-Ga2O3 thin film is then epitaxially grown on the surface of the electron-depleted β-Ga2O3 drift layer to facilitate the subsequent formation of a source ohmic contact. Simultaneously, a trench-shaped structure formed by ICP etching facilitates the deposition of a dielectric layer and gate metal. When a forward voltage is applied to the gate, electrons accumulate on the sidewalls of the trench structure until the device turns on. The present invention utilizes ion implantation to deplete electrons in the β-Ga2O3 drift layer to achieve a vertical enhancement-mode β-Ga2O3 UMOSFET device, which is of great significance for improving the performance and reliability of Ga2O3-based power devices.

[0091] The operating principle of a vertical β-Ga2O3 UMOSFET device provided by the present invention is that a high-resistance region depletes electrons, blocking current between the source and drain, thereby achieving an enhancement mode. When the gate voltage is increased, electrons accumulate near the high-resistance region on the side of the contact area between the high-resistance region and the sidewall of the trench structure. When a sufficient number of electrons accumulates, the device turns on. Therefore, the number of electrons can be controlled by adjusting the doping concentration of the second N-type gallium oxide epitaxial layer on the sidewall, thereby controlling the device threshold voltage. (The higher the doping concentration, the lower the threshold voltage. In the extreme case, when the doping concentration is too high, there are enough electrons to promote device conduction without applying a gate voltage, and the device is not an enhancement mode device but a depletion mode device.) Because the core of the device is the contact area between the high-resistance region and the sidewall of the trench structure, the number of electrons in this area affects whether the device turns on. Therefore, even if the doping concentration of the epitaxial layer at the bottom of the trench structure is high, it will not promote device conduction. However, because the epitaxial layers of the sidewall and the trench bottom are grown simultaneously, the doping concentration should be the same.

[0092] Specifically, the thickness of the current blocking layer is 300-600 nm, and the thickness of the β-Ga2O3 drift layer 20 is 4-10 μm.

[0093] Specifically, the depth of the groove structure is 800-1000 nm, and the groove structure is a U-shaped groove, a V-shaped groove, an inverted trapezoidal groove, or the like.

[0094] Specifically, the carrier concentration of the highly doped β-Ga 2 O 3 epitaxial layer 40 is greater than the carrier concentration of the β-Ga 2 O 3 substrate 10 and greater than the carrier concentration of the β-Ga 2 O 3 drift layer 20 .

[0095] Example 1

[0096] See also Figure 3 A method for preparing a β-Ga2O3 UMOSFET device comprises the following steps:

[0097] 1) performing organic cleaning on a β-Ga2O3 substrate 10 having a β-Ga2O3 drift layer 20, wherein the β-Ga2O3 drift layer 20 has a thickness of 10 μm;

[0098] 2) growing a 100 nm thick SiO2 thin film on the first surface of the β-Ga2O3 drift layer 20 as an ion implantation sacrificial layer by using PECVD (plasma enhanced chemical vapor deposition) or other methods, wherein the first surface is the side of the β-Ga2O3 drift layer 20 facing away from the β-Ga2O3 substrate 10;

[0099] 3) Using an ion implanter, N ions and other compensation acceptor materials are implanted into the β-Ga2O3 drift layer 20. The implantation region extends from the surface of the β-Ga2O3 drift layer 20 to 300 to 600 nm from the first surface, and a 1×10 18 cm -3 ~1×10 19 cm -3 N ion concentration;

[0100] 4) annealing at 1000-1200° C. for 30-60 min using an annealing furnace or other annealing equipment to activate N ions, thereby forming an electron-depleted current blocking layer 30 in the β-Ga2O3 drift layer 20, wherein the thickness of the current blocking layer 30 is 300-600 nm;

[0101] 5) Using MOCVD / CVD / MBE and other methods, a highly doped (doping concentration of 1×10 19 cm -3 ~5×10 19 cm -3)β-Ga2O3 epitaxial layer 40;

[0102] 6) A groove structure 101 with a depth of 800 nm to 1000 nm is etched in the gate region of the highly doped β-Ga2O3 epitaxial layer 40 using an ICP / RIE etching method, with the notch of the groove structure being located on the surface of the highly doped β-Ga2O3 epitaxial layer 40 and the bottom of the groove being located within the β-Ga2O3 drift layer 20. A wet etching repair is then performed, wherein the groove structure 101 may be a U-shaped groove, a V-shaped groove, or an inverted trapezoidal groove, etc.; after etching, the sidewalls of the groove structure will have many dangling bonds, because the physical bombardment in the dry etching directly breaks the Ga-O bonds. According to epitaxial growth experience, the epitaxial layer crystals grown in the region with dangling bonds have better quality;

[0103] 7) using PECVD (plasma enhanced chemical vapor deposition) or other methods to grow a SiO2 film with a thickness of about 100 nm on the surface of the sample structure obtained in step 6) as a mask;

[0104] 8) After photolithography, the sample obtained in step 7) is subjected to an etching method such as NLD to remove the mask of the groove structure area to expose the groove wall of the groove structure;

[0105] 9) placing the sample obtained in step 8) into a growth chamber of an MOCVD device, and performing secondary epitaxy in the groove-shaped structure region, thereby growing an unintentionally doped β-Ga2O3 epitaxial layer 50 in the groove-shaped structure and continuously covering the groove wall of the groove-shaped structure, wherein the unintentionally doped β-Ga2O3 epitaxial layer 50 has a thickness of 100 to 200 nm and a doping concentration of 5×10 15 cm -3 ~2×10 16 cm -3 ;

[0106] 10) Using ALD (atomic layer deposition) equipment / process, a layer of Al2O3 film with a thickness of approximately 40 nm is deposited on the surfaces of the highly doped β-Ga2O3 epitaxial layer 40 and the unintentionally doped β-Ga2O3 epitaxial layer 50 as a dielectric layer 70, and a hole is opened in the source region of the Al2O3 film to expose the highly doped β-Ga2O3 epitaxial layer 40;

[0107] 11) Ti / Au metal (thickness of 50 / 150 nm) is deposited on the source region of the surface of the highly doped β-Ga2O3 epitaxial layer 40 facing away from the current blocking layer 30 and on the surface of the β-Ga2O3 substrate 10 facing away from the β-Ga2O3 drift layer 20 by electron beam evaporation or the like, and the metal is removed by lift-off stripping process to prepare the source 81 and drain 82 of the device;

[0108] 12) Rapidly annealing the sample obtained in step 11) using an RTP (rapid annealing furnace) or the like, so that the source electrode 81 and the highly doped β-Ga2O3 epitaxial layer 40, and the drain electrode 60 and the β-Ga2O3 substrate 10 achieve ohmic contact;

[0109] 13) Ni / Au metal (50 / 150 nm) is deposited on the dielectric layer 70 by electron beam evaporation or the like as the gate 70 of the device, thereby obtaining a vertical enhancement mode β-Ga2O3 UMOSFET device.

[0110] The transfer curve, output curve and breakdown curve of the β-Ga2O3 UMOSFET device obtained in Example 1 are shown in Figure 1. Figure 4a 、 Figure 4b 、 Figure 4c As shown, Figure 4b The output curve includes multiple current density curves, and the multiple current density curves are obtained by testing at different voltages.

[0111] Example 2

[0112] See also Figure 3 A method for preparing a β-Ga2O3 UMOSFET device comprises the following steps:

[0113] 1) performing organic cleaning on a β-Ga2O3 substrate 10 having a β-Ga2O3 drift layer 20, wherein the β-Ga2O3 drift layer 20 has a thickness of 10 μm;

[0114] 2) growing a 100 nm thick SiO2 thin film on the first surface of the β-Ga2O3 drift layer 20 as an ion implantation sacrificial layer by using PECVD (plasma enhanced chemical vapor deposition) or other methods, wherein the first surface is the side of the β-Ga2O3 drift layer 20 facing away from the β-Ga2O3 substrate 10;

[0115] 3) Using an ion implanter, N ions and other compensation acceptor materials are implanted into the β-Ga2O3 drift layer 20. The implantation region extends from the surface of the β-Ga2O3 drift layer 20 to 300 to 600 nm from the first surface, and a 1×10 18 cm -3 ~1×10 19 cm -3 N ion concentration;

[0116] 4) annealing at 1000-1200° C. for 30-60 min using an annealing furnace or other annealing equipment to activate N ions, thereby forming an electron-depleted current blocking layer 30 in the β-Ga2O3 drift layer 20, wherein the thickness of the current blocking layer 30 is 300-600 nm;

[0117] 5) Using MOCVD / CVD / MBE and other methods, a highly doped (doping concentration of 1×10 19 cm -3 ~5×10 19 cm -3 )β-Ga2O3 epitaxial layer 40;

[0118] 6) using ICP / RIE or other etching methods to carve a groove structure 101 with a depth of 800 nm to 1000 nm in the gate region on the surface of the highly doped β-Ga2O3 epitaxial layer 40, with the notch of the groove structure being located on the surface of the highly doped β-Ga2O3 epitaxial layer 40 and the bottom of the groove being located in the β-Ga2O3 drift layer 20, followed by wet etching repair, wherein the groove structure 101 may be a U-shaped groove, a V-shaped groove, or an inverted trapezoidal groove, etc.;

[0119] 7) using PECVD (plasma enhanced chemical vapor deposition) or other methods to grow a SiO2 film with a thickness of about 100 nm on the surface of the sample structure obtained in step 6) as a mask;

[0120] 8) After photolithography, the sample obtained in step 7) is subjected to an etching method such as NLD to remove the mask of the groove structure area to expose the groove wall of the groove structure;

[0121] 9) placing the sample obtained in step 8) into a growth chamber of an MOCVD device, and performing secondary epitaxy in the groove-shaped structure region, thereby growing an unintentionally doped β-Ga2O3 epitaxial layer 50 in the groove-shaped structure and continuously covering the groove wall of the groove-shaped structure, wherein the unintentionally doped β-Ga2O3 epitaxial layer 50 has a thickness of 100 to 200 nm and a doping concentration of 5×10 15 cm -3 ~2×10 16 cm -3 ;

[0122] 10) depositing a 100 nm thick p-NiO layer 60 on the unintentionally doped β-Ga2O3 epitaxial layer 50 at the bottom of the groove structure using a sputtering process, wherein the p-NiO layer 60 forms a PN junction with the unintentionally doped β-Ga2O3 epitaxial layer 50;

[0123] 11) Using ALD (atomic layer deposition) equipment / process, a layer of Al2O3 film with a thickness of approximately 40 nm is deposited as a dielectric layer 70 on the surfaces of the highly doped β-Ga2O3 epitaxial layer 40, the unintentionally doped β-Ga2O3 epitaxial layer 50, and the p-NiO layer 60, and a hole is opened in the source region of the Al2O3 film to expose the highly doped β-Ga2O3 epitaxial layer 40;

[0124] 12) Depositing Ti / Au metal (50 / 150 nm thick) on the source region of the surface of the highly doped β-Ga2O3 epitaxial layer 40 facing away from the current blocking layer 30 and on the surface of the β-Ga2O3 substrate 10 facing away from the β-Ga2O3 drift layer 20 by electron beam evaporation or the like, and performing metal stripping by a lift-off process to prepare the source 81 and drain 82 of the device;

[0125] 13) Rapidly annealing the sample obtained in step 12) using an RTP (rapid annealing furnace) or the like, so that the source electrode 81 and the highly doped β-Ga2O3 epitaxial layer 40, and the drain electrode 60 and the β-Ga2O3 substrate 10 achieve ohmic contact;

[0126] 14) Ni / Au metal (50 / 150 nm) is deposited on the dielectric layer 70 by electron beam evaporation or the like as the gate 70 of the device, thereby obtaining a vertical enhancement mode β-Ga2O3 UMOSFET device.

[0127] The transfer curve, output curve and breakdown curve of the β-Ga2O3 UMOSFET device obtained in Example 2 are shown in Figure 2. Figure 5a 、 Figure 5b 、 Figure 5c As shown, Figure 5b The output curve includes multiple current density curves, and the multiple current density curves are obtained by testing at different voltages.

[0128] Example 3

[0129] The method for preparing a β-Ga2O3 UMOSFET device in this embodiment is basically the same as that in Example 1, except that steps 7) to 9) are omitted in this embodiment, and the vertical enhancement mode β-Ga2O3 UMOSFET device formed in this embodiment does not include an unintentionally doped β-Ga2O3 epitaxial layer 50.

[0130] The transfer curve, output curve and breakdown curve of the β-Ga2O3 UMOSFET device obtained in Example 3 are shown in Figure 2. Figure 6a 、 Figure 6b 、 Figure 6c As shown, Figure 6b The output curve includes multiple current density curves, and the multiple current density curves are obtained by testing at different voltages.

[0131] Depend on Figure 4a 、 Figure 4b 、 Figure 4c 、 Figure 5a 、 Figure 5b 、 Figure 5c 、 Figure 6a 、 Figure 6b 、 Figure 6c The transfer curves, output curves, and breakdown curves of the devices of Examples 1 to 3 show that, since Examples 1 and 2 have an unintentionally doped β-Ga2O3 epitaxial layer 50 formed by secondary epitaxy, the number of electrons therein is much higher than the number of electrons in the high-resistance region. Therefore, their threshold voltage is lower than that of Example 3, the off-state leakage is increased, and the saturation current is also increased. The reason why the breakdown voltage of the device in Example 1 is slightly higher than that of Example 3 is mainly because the presence of dangling bonds promotes the improvement of the quality of the unintentionally doped β-Ga2O3 epitaxial layer 50, and the deposited secondary epitaxial layer changes the corner of the bottom of the U-shaped groove from a right angle to a shape with a certain arc, suppressing the local field concentration and promoting the improvement of the breakdown voltage. In Example 2, the deposited p-NiO forms a PN junction with the unintentionally doped β-Ga2O3 epitaxial layer 50, which places the field strength in the PN junction depletion region, greatly improving the breakdown characteristics.

[0132] The present invention provides a vertical β-Ga2O3 UMOSFET device and a preparation method thereof. Based on the secondary epitaxial growth of a β-Ga2O3 thin film in a groove structure region of the β-Ga2O3 UMOSFET device, the conductive channel of the device is transferred out of the ion implantation region and into an unintentionally doped β-Ga2O3 epitaxial layer located on the sidewall of the groove structure, thereby effectively improving the saturation current / saturation current density of the device and reducing the threshold voltage of the device. In addition, the present invention can also reduce the off-state leakage of the device by increasing the implantation concentration in the ion implantation region. The ion implantation region is a high-resistance region. Because the high-resistance region is high-resistance, it still contains a certain number of electrons, thus generating some off-state leakage. When the secondary epitaxial growth is performed to form a second N-type gallium oxide epitaxial layer, more electrons are generated in the second N-type gallium oxide epitaxial layer due to unintentional doping, resulting in greater off-state leakage. At this time, if the implantation concentration of N ions is increased to deplete more electrons in the high-resistance region, the off-state leakage can be reduced.

[0133] The present invention provides a vertical β-Ga2O3 UMOSFET device and its fabrication method. By adjusting the doping concentration of the unintentionally doped β-Ga2O3 epitaxial layer located on the sidewalls of the trench structure, the device's threshold voltage can be controlled, enabling diverse applications. Furthermore, the present invention provides a vertical β-Ga2O3 UMOSFET device and its fabrication method. Furthermore, the device's field intensity concentration region is shifted away from the device through a PN junction located at the bottom of the trench structure, thereby improving the device's withstand voltage capability.

[0134] It should be understood that the above embodiments are merely illustrative of the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent variations or modifications made in accordance with the spirit and substance of the present invention are intended to be encompassed within the scope of protection of the present invention.

Claims

1. A β-Ga2O3 UMOSFET device comprising an epitaxial structure and a source, a drain, and a gate coordinated with the epitaxial structure, characterized in that: The epitaxial structure includes an N-type gallium oxide drift layer, a current blocking layer, and a first N-type gallium oxide epitaxial layer stacked in sequence, and a groove structure is further provided in the epitaxial structure, wherein the groove opening of the groove structure is provided on the surface of the first N-type gallium oxide epitaxial layer and the groove bottom is provided in the N-type gallium oxide drift layer; and a second N-type gallium oxide epitaxial layer is continuously provided on the groove wall of the groove structure, the conductive channel of the β-Ga2O3 UMOSFET device is located in the second N-type gallium oxide epitaxial layer, and the current blocking layer is a high-resistance region formed by converting the surface region of the N-type gallium oxide drift layer into a compensating acceptor material. At least a portion of the gate is disposed in the groove-shaped structure, and the gate is isolated from the second N-type gallium oxide epitaxial layer by a dielectric layer, and the source is electrically coupled to the first N-type gallium oxide epitaxial layer.

2. The β-Ga2O3 UMOSFET device according to claim 1, wherein: The second N-type gallium oxide epitaxial layer is unintentionally doped, the first N-type gallium oxide epitaxial layer is highly doped, and the doping concentration of the second N-type gallium oxide epitaxial layer is lower than the doping concentration of the first N-type gallium oxide epitaxial layer.

3. The β-Ga2O3 UMOSFET device according to claim 2, wherein: The doping concentration of the second N-type gallium oxide epitaxial layer is 5×10 15 cm -3 ~2×10 16 cm -3 The doping concentration of the first N-type gallium oxide epitaxial layer is 1×10 19 cm -3 ~5×10 19 cm -3 .

4. The β-Ga2O3 UMOSFET device according to claim 2, wherein: The doping concentration of the first N-type gallium oxide epitaxial layer is greater than the doping concentration of the N-type gallium oxide drift layer.

5. The β-Ga2O3 UMOSFET device according to claim 2, wherein: The thickness of the second N-type gallium oxide epitaxial layer is 100-200 nm, and the thickness of the first N-type gallium oxide epitaxial layer is 100-300 nm.

6. The β-Ga2O3 UMOSFET device according to claim 1, 2, 3, 4, or 5, wherein: The epitaxial structure also includes a P-type epitaxial layer, which is arranged at the bottom of the groove of the groove-shaped structure, and the P-type epitaxial layer is stacked on the second N-type gallium oxide epitaxial layer. The P-type epitaxial layer forms a PN junction with the second N-type gallium oxide epitaxial layer and the N-type gallium oxide drift layer covered by the second N-type gallium oxide epitaxial layer.

7. The β-Ga2O3 UMOSFET device according to claim 6, wherein: The material of the P-type epitaxial layer includes p-NiO.

8. The β-Ga2O3 UMOSFET device according to claim 6, wherein: The P-type epitaxial layer and the gate are also isolated by the dielectric layer.

9. The β-Ga2O3 UMOSFET device according to claim 1, wherein: The compensating acceptor material includes N ions or Mg ions.

10. The β-Ga2O3 UMOSFET device according to claim 1, wherein: The concentration of the compensation acceptor material in the current blocking layer is 1×10 18 cm -3 ~1×10 19 cm -3 .

11. The β-Ga2O3 UMOSFET device according to claim 1, wherein: The thickness of the current blocking layer is 300-600 nm, and the thickness of the N-type gallium oxide drift layer is 4-10 μm.

12. The β-Ga2O3 UMOSFET device according to claim 1, wherein: The depth of the groove structure is 800-1000 nm.

13. The β-Ga2O3 UMOSFET device according to claim 1, wherein: The groove structure is a U-shaped groove, a V-shaped groove or an inverted trapezoidal groove.

14. The β-Ga2O3 UMOSFET device according to claim 1, wherein: The N-type gallium oxide drift layer is arranged on an N-type gallium oxide substrate. The drain is arranged on a surface of the N-type gallium oxide substrate away from the N-type gallium oxide drift layer and forms an ohmic contact with the N-type gallium oxide substrate.

15. The β-Ga2O3 UMOSFET device according to claim 14, wherein: The carrier concentration of the first N-type gallium oxide epitaxial layer is greater than the carrier concentration of the N-type gallium oxide substrate and greater than the carrier concentration of the N-type gallium oxide drift layer.

16. The β-Ga2O3 UMOSFET device according to claim 14, wherein: The materials of the N-type gallium oxide substrate, the N-type gallium oxide drift layer, the first N-type gallium oxide epitaxial layer, and the second N-type gallium oxide epitaxial layer all include β-Ga2O3.

17. A method for improving the performance of a β-Ga2O3 UMOSFET device, comprising the steps of fabricating an epitaxial structure and fabricating a source, a drain, and a gate matching the epitaxial structure, wherein: The steps for making the epitaxial structure include: An N-type gallium oxide drift layer, a current blocking layer, and a first N-type gallium oxide epitaxial layer are formed, which are stacked in sequence. The method for manufacturing the current blocking layer includes: injecting a compensating acceptor material into a surface region of the N-type gallium oxide drift layer and activating the compensating acceptor material to deplete electrons in the surface region of the N-type gallium oxide drift layer to form a high-resistance current blocking layer; Fabricating a groove-shaped structure, with the groove opening of the groove-shaped structure being arranged on the surface of the first N-type gallium oxide epitaxial layer and the groove bottom being arranged in the N-type gallium oxide drift layer; forming a second N-type gallium oxide epitaxial layer, and continuously covering the groove wall of the groove structure with the second N-type gallium oxide epitaxial layer, wherein the conductive channel of the β-Ga2O3 UMOSFET device is located in the second N-type gallium oxide epitaxial layer; At least part of the gate is disposed in the groove structure, the gate and the second N-type gallium oxide epitaxial layer are isolated by a dielectric layer, and the source is electrically coupled to the first N-type gallium oxide epitaxial layer.

18. The method according to claim 17, wherein: The second N-type gallium oxide epitaxial layer is unintentionally doped, the first N-type gallium oxide epitaxial layer is highly doped, and the doping concentration of the second N-type gallium oxide epitaxial layer is lower than the doping concentration of the first N-type gallium oxide epitaxial layer.

19. The method according to claim 18, wherein: The doping concentration of the second N-type gallium oxide epitaxial layer is 5×10 15 cm -3 ~2×10 16 cm -3 The doping concentration of the first N-type gallium oxide epitaxial layer is 1×10 19 cm -3 ~5×10 19 cm -3 .

20. The method according to claim 18, wherein: The doping concentration of the first N-type gallium oxide epitaxial layer is greater than the doping concentration of the N-type gallium oxide drift layer.

21. The method according to claim 18, wherein: The thickness of the second N-type gallium oxide epitaxial layer is 100-200 nm, and the thickness of the first N-type gallium oxide epitaxial layer is 100-300 nm.

22. The method according to claim 17 or 18, characterized in that The step of making the epitaxial structure further includes: A P-type epitaxial layer is formed at the bottom of the trench structure, and the P-type epitaxial layer is stacked on the second N-type gallium oxide epitaxial layer. The P-type epitaxial layer forms a PN junction with the second N-type gallium oxide epitaxial layer and the N-type gallium oxide drift layer covered by the second N-type gallium oxide epitaxial layer.

23. The method according to claim 22, wherein: The material of the P-type epitaxial layer includes p-NiO.

24. The method according to claim 22, wherein: The gate and the P-type epitaxial layer are also isolated by the dielectric layer.

25. The method according to claim 17, characterized in that Specifically include: A compensation acceptor material is injected into the surface region of the N-type gallium oxide drift layer, and then annealed at 1000-1200° C. for 30-60 minutes to activate the compensation acceptor material and deplete electrons in the surface region, thereby forming a high-resistance current blocking layer.

26. The method according to claim 17 or 25, characterized in that: The compensating acceptor material includes N ions or Mg ions.

27. The method according to claim 17 or 25, wherein: The concentration of the compensation acceptor material in the current blocking layer is 1×10 18 cm -3 ~1×10 19 cm -3 .

28. The method according to claim 17 or 25, wherein: The thickness of the current blocking layer is 300-600 nm, and the thickness of the N-type gallium oxide drift layer is 4-10 μm.

29. The method according to claim 17, wherein: The depth of the groove structure is 800-1000 nm.

30. The method according to claim 17, wherein: The groove structure is a U-shaped groove, a V-shaped groove or an inverted trapezoidal groove.

31. The method according to claim 17, wherein: The N-type gallium oxide drift layer is arranged on an N-type gallium oxide substrate. The drain is arranged on a surface of the N-type gallium oxide substrate away from the N-type gallium oxide drift layer and forms an ohmic contact with the N-type gallium oxide substrate.

32. The method according to claim 31, characterized in that: The carrier concentration of the first N-type gallium oxide epitaxial layer is greater than the carrier concentration of the N-type gallium oxide substrate and greater than the carrier concentration of the N-type gallium oxide drift layer.

33. The method according to claim 31, wherein: The materials of the N-type gallium oxide substrate, the N-type gallium oxide drift layer, the first N-type gallium oxide epitaxial layer, and the second N-type gallium oxide epitaxial layer all include β-Ga2O3.

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