Controller and method for controlling a step-down converter

Abstract

The present application provides a controller and a method for controlling a buck converter. The controller includes a voltage-to-current module and a switching signal generation module. The voltage-to-current module determines an operation mode of the controller according to an output voltage of the buck converter and a preset maximum output voltage. The operation mode of the controller includes a normal mode and a limit mode. In the normal mode, the voltage-to-current module generates a first current according to an input voltage of the buck converter and generates a second current according to the output voltage of the buck converter. In the limit mode, the voltage-to-current module generates the first current according to the input voltage and generates the second current according to the maximum output voltage. The switching signal generation module generates a ramp signal according to the first current and the second current, and generates a first switching signal and a second switching signal according to the ramp signal, a first voltage signal, a second voltage signal, a reference signal and the output voltage of the buck converter to control an upper switch and a lower switch of the buck converter, respectively.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of controller technology, and in particular, to a controller and method for a buck converter. BACKGROUND

[0002] Figure 1 A buck converter 100 is shown. The buck converter 100 receives an input voltage Vin and generates an output voltage Vout. A conventional method of controlling the buck converter 100 is to alternately turn on the upper switch Ql and the lower switch Q2 of the buck converter 100 such that the variation of the inductor current remains constant in each control period, i.e. Constant Ripple Current control method. The drawback of this conventional control method is that the on-time of the upper switch Ql is inversely proportional to the difference between the input voltage Vin and the output voltage Vout. When the input voltage Vin and the output voltage Vout are close in magnitude, or the output voltage Vout is greater than or equal to the input voltage Vin, the buck converter 100 can lose control and fail to operate properly. IN OUT IN OUT IN OUT OUT IN SUMMARY

[0003] The present application provides a controller for controlling a buck converter. The controller includes a voltage-to-current module and a switch signal generation module. The voltage-to-current module determines the operation mode of the controller according to the output voltage of the buck converter and a preset maximum output voltage. The operation mode of the controller includes a normal mode and a limit mode. In the normal mode, the voltage-to-current module generates a first current according to the input voltage of the buck converter and a second current according to the output voltage of the buck converter. In the limit mode, the voltage-to-current module generates the first current according to the input voltage and the second current according to the maximum output voltage. The switch signal generation module generates a ramp signal according to the first current and the second current, and generates a first switch signal and a second switch signal according to the ramp signal and a first voltage signal, a second voltage signal, a reference signal and the output voltage of the buck converter to control the upper switch and the lower switch of the buck converter, respectively.

[0004] ​​​​​​​​The present application also provides a method for controlling a buck converter, comprising the steps of: setting a maximum output voltage; monitoring an output voltage of the buck converter; if the output voltage of the buck converter is less than the maximum output voltage, generating a first current according to an input voltage of the buck converter and generating a second current according to the output voltage of the buck converter; if the output voltage of the buck converter is greater than or equal to the maximum output voltage, generating the first current according to the input voltage and generating the second current according to the maximum output voltage; generating a ramp signal according to the first current and the second current; and generating a first switch signal and a second switch signal according to the ramp signal and a first voltage signal, a second voltage signal, a reference signal and the output voltage of the buck converter to control an upper switch and a lower switch of the buck converter, respectively.

[0005] As mentioned above, the present application discloses a controller for controlling a buck converter and a method for controlling a buck converter. When the output voltage of the buck converter is greater than or equal to the maximum output voltage, the controller enters a limit mode. In the limit mode, the duty cycle of the upper switch of the buck converter is constant, and the on time of the upper switch is not related to the output voltage of the buck converter, so that the circuit will not be out of control due to the values of the input voltage and the output voltage of the buck converter being close to each other, and thus the whole circuit is more stable and effective. BRIEF DESCRIPTION OF DRAWINGS

[0006] The objectives, specific features and advantages of the present application will become further apparent from the following description of the embodiments thereof, taken in conjunction with the accompanying drawings.

[0007] Figure 1 A conventional buck converter is shown;

[0008] Figure 2 A circuit for controlling a buck converter according to an embodiment of the present application is shown;

[0009] Figure 3 A circuit diagram of a controller for controlling a buck converter according to an embodiment of the present application is shown;

[0010] Figure 4 A circuit diagram of a voltage-to-current module in the controller according to an embodiment of the present application is shown;

[0011] Figure 5 A timing diagram of the controller according to an embodiment of the present application is shown;

[0012] Figure 6 A timing diagram of the controller according to an embodiment of the present application is shown;

[0013] Figure 7 A flowchart of a method for controlling a buck converter according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0014] The embodiments of the present invention will be described in detail below. Although the present invention has been described and illustrated through these embodiments, it should be noted that the present invention is not limited to these embodiments. Rather, the present invention covers all alternatives, variations, and equivalents within the spirit and scope of the invention as defined in the appended claims.

[0015] Furthermore, to better illustrate the invention, numerous specific details are set forth in the following detailed embodiments. Those skilled in the art will understand that the invention can be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits have not been described in detail in order to highlight the spirit of the invention.

[0016] Figure 2 The diagram shows a circuit 200 for controlling a buck converter according to an embodiment of the present invention. The circuit 200 includes a controller 210. The controller 210 has ports including a power supply port PWR, a reference signal input port REF, voltage input ports VR1 and VR2, a feedback port FB, and switch control ports SW1 and SW2. The power supply port PWR receives the input voltage V of the buck converter. IN The reference signal input port REF receives the reference signal VREF, and the voltage input ports VR1 and VR2 receive the first voltage signal V1 and the second voltage signal V2, respectively. The feedback port FB receives the output voltage V of the buck converter. OUT The switch control ports SW1 and SW2 control the upper switch Q1 and lower switch Q2 of the buck converter respectively using the first switch signal HDR and the second switch signal LDR.

[0017] Figure 3 The diagram shown is a circuit diagram of a controller 210 for controlling a buck converter according to an embodiment of the present invention. Figure 3 Combining Figure 2 Description. Controller 210 includes a voltage-to-current module 310 for adjusting the output voltage V of the buck converter. OUT and the preset maximum output voltage V OUTMAX The operating mode of controller 210 is determined. Controller 210 has two operating modes: normal mode and limiting mode. If the output voltage V... OUT Less than the maximum output voltage V OUTMAX The judgment module 310 causes the controller 210 to operate in normal mode. If the output voltage V OUT Greater than or equal to the maximum output voltage V OUTMAX The judgment module 310 causes the controller 210 to operate in the restricted mode. In normal mode, the voltage-to-current module 310 determines the current based on the input voltage V of the buck converter. IN Generate the first current IVIN According to the output voltage V of the buck converter OUT Generate a second current I VOUT In limited mode, the voltage-to-current module 310 adjusts the current based on the input voltage V of the buck converter. IN Generate the first current I VIN Based on the maximum output voltage V of the buck converter OUTMAX Generate a second current I VOUTMAX The controller 210 also includes a switching signal generation module 340, used to generate a switching signal based on the first current I. VIN Second current I VOUT Or I VOUTMAX A ramp signal VRAMP is generated, and a first switching signal HDR and a second switching signal LDR are generated based on the ramp signal VRAMP, the first voltage signal V1, the second voltage signal V2, the reference signal VREF, and the output voltage VOUT to control the upper switch Q1 and the lower switch Q2 of the buck converter, respectively.

[0018] Figure 4 The diagram shown is a circuit diagram of a voltage-to-current module 310 in a controller 210 according to an embodiment of the present invention. The voltage-to-current module 310 includes a first operational amplifier OTA1, a second operational amplifier OTA2, a maximum output voltage generation module 401, and a setting voltage generation module 402.

[0019] The first operational amplifier OTA1 is used to generate the first current I. VIN Its positive terminal receives the input voltage V. IN The negative terminal and output terminal are connected to resistor RS3, and the first current I... VIN The voltage-to-current module 310 includes a current mirror 406 for converting the first current I flowing through resistor RS3. VIN Copy it to the current path containing the charging switch 404 to charge capacitor C2.

[0020] The maximum output voltage generation module 401 is used to generate voltage based on the input voltage V. IN Generate maximum output voltage V OUTMAX .exist Figure 4 In this embodiment, the maximum output voltage generation module 401 includes a voltage divider composed of resistors RS1 and RS2, and the maximum output voltage V OUTMAX The input voltage V is divided by a voltage divider IN The voltage is obtained by voltage division. The resistance values ​​of resistors RS1 and / or RS2 can be adjusted as needed. In one embodiment, the controller 210 has an adjustment port connected to the voltage divider circuit 401 to adjust the resistance values ​​of resistors RS1 and / or RS2. Assuming the resistance values ​​of resistors RS1 and RS2 are R1 and R2 respectively, the maximum output voltage V is...OUTMAX It can be obtained from the following formula:

[0021]

[0022] The voltage generation module 402 sets the output voltage V monitored in real time by the controller 210. OUT and the maximum output voltage V OUTMAX Generate the set voltage VSET. Figure 4 In one embodiment, the voltage generation module 402 includes a function for comparing the output voltage V. OUT and maximum output voltage V OUTMAX The comparator COMP4 and the selector for generating the setting voltage VSET based on the output of comparator COMP4.

[0023] The first input terminal of comparator COMP4 receives the input voltage V via a voltage divider. IN The second input terminal receives the output voltage V. OUT If the output voltage V OUT Less than the maximum output voltage V OUTMAX Selector 403 selects the output voltage V. OUT As the set voltage VSET is applied, controller 210 enters normal mode; if the output voltage V... OUT Greater than or equal to the maximum output voltage V OUTMAX Selector 403 selects the maximum output voltage V. OUTMAX As the set voltage VSET, the controller 210 enters the restricted mode.

[0024] The second operational amplifier OTA2 generates a second current based on the set voltage VSET. Its positive terminal is coupled to the output of selector 403 to receive the set voltage VSET, and its negative terminal and output terminal are coupled to resistor RS4. The second current is the current flowing through resistor RS4. In normal mode, the second current generated by the second operational amplifier OTA2 is I. VOUT In restricted mode, the second current generated by the second operational amplifier OTA2 is I. VOUTMAX .

[0025] refer to Figure 3 The switch signal generation module 340 includes a first operational amplifier OTA1 and a second operational amplifier OTA2 (shown in...). Figure 4 The capacitor C2 is coupled to the first operational amplifier OTA1, and the charging switch 404 (shown in) is coupled between the capacitor C2 and the first operational amplifier OTA1. Figure 4 The charging switch 404 is made of... Figure 3The charging signal PWM is generated by the switching signal generation module 340. When the PWM is in the first state (e.g., high level), the charging switch 404 is turned on, and capacitor C2 is charged by the charging current. This charging current is the first current I. VIN Second current I VOUT (When controller 210 is operating in normal mode) or I VOUTMAX The difference (when controller 210 is operating in restricted mode). When the PWM is in the second state (e.g., low level), the charging switch 404 is open, and capacitor C2 generates a discharge current, which is the second current I. VOUT (When controller 210 is operating in normal mode) or I VOUTMAX (When controller 210 is operating in limit mode). The ramp signal VRAMP is the voltage across capacitor C2.

[0026] like Figure 3 As shown, the switch signal generation module 340 also includes a first comparator COMP1, a second comparator COMP2, a third comparator COMP3, and an RS flip-flop 320. The first comparator COMP1 generates a first comparison result based on a first voltage signal V1 and a ramp signal VRAMP. The second comparator COMP2 generates a second comparison result based on a second voltage signal V2 and a ramp signal VRAMP. The third comparator COMP3 generates a second comparison result based on a reference signal VREF and an output voltage V. OUT A third comparison result is generated. The RS flip-flop 320 generates a charging signal PWM based on the first, second, and third comparison results to control the charging switch 404. The output of the first comparator COMP1 is coupled to the R input of the RS flip-flop 320, and the outputs of the second and third comparators COMP2 and COMP3 are coupled to the S input of the RS flip-flop 320 via an AND gate 312. The Q output of the RS flip-flop 320 outputs the charging signal PWM. The switch signal generation module 340 also includes a drive unit 330, which generates a first switch signal HDR and a second switch signal LDR based on the second and third comparison results and the charging signal PWM. Figure 3 In this example, the drive unit 330 includes a buffer 316, inverters 361 and 362, a NAND gate 306, and an AND gate 363. The buffer 316 is coupled to the Q output of the RS flip-flop 320, and the charging signal PWM generates a first switching signal HDR via the buffer 316. The AND gate 363 performs an AND operation between LDR_EN and the inverted PWM signal to generate a second switching signal LDR.

[0027] Figure 5 The diagram shown is a timing diagram of controller 210 in normal mode. Figure 6 The timing diagram of controller 210 in restricted mode is shown. Figure 5 ,Figure 6 The application will be described Figure 3 and Figure 4 .

[0028] In normal mode, the first operational amplifier OTA1 generates a first current I VIN , and the second operational amplifier OTA2 generates a second current I VOUT . Assuming the resistance of RS3 and RS4 is R, the first current I VIN and the second current I VOUT can be derived from the following equations:

[0029]

[0030]

[0031] In normal mode, as shown in Figure 4 , the controller 210 controls the charging switch 404 to charge and discharge the capacitor C2 to generate a ramp signal VRAMP through the charging signal PWM. Referring to Figure 5 , in normal mode, when PWM is high, the charging switch 404 is on, the first current I VIN charges the capacitor C2, while the capacitor C2 discharges with the second current I VOUT . Therefore, the current (charging current) IRAMP of the capacitor C2 is I VIN -I VOUT . The voltage VRAMP on the capacitor C2 increases. When VRAMP is greater than the first voltage signal V1, Figure 3 , the comparator COMP1 outputs a high level to the R terminal of the RS flip-flop 320, so that PWM becomes low, and the charging switch 404 is off. Referring to Figure 4 , after the charging switch 404 is off, the capacitor C2 discharges with the second current I VOUT , so the current (discharging current) IRAMP of the capacitor C2 is -I VOUT , and the voltage VRAMP on the capacitor C2 decreases. When VRAMP drops to less than the second voltage signal V2, Figure 3 , the comparator COMP2 outputs a high level. The AND gate 318 performs AND operation on the inverted PWM and the output of the comparator COMP2, and outputs a high level to turn on the switch 303. The switch 303 is coupled between the positive terminal of the capacitor C2 and the voltage input port VR2 (shown in Figure 2 ), and when the switch 303 is on, the voltage on the capacitor C2 is clamped at the voltage of the second voltage signal V2. When the output voltage V OUTWhen VRAMP drops below the reference signal VREF, the output of comparator COMP3 is high, and the LDR_EN signal outputted by NAND gate 306 is low. When PWM is high, switch 303 is off, and charging switch 404 is on, so that capacitor C2 is charged, and the voltage VRAMP on capacitor C2 is greater than the second voltage signal V2, the output of comparator COMP2 is low, and the LDR_EN signal is high. Further, the driving unit 330 generates the first switch signal HDR and the second switch signal LDR according to PWM and LDR_EN to control the upper switch Ql and the lower switch Q2 of the buck converter, respectively. OUT When VRAMP drops below the reference signal VREF, the output of comparator COMP3 is high, and the LDR_EN signal outputted by NAND gate 306 is low. When PWM is high, switch 303 is off, and charging switch 404 is on, so that capacitor C2 is charged, and the voltage VRAMP on capacitor C2 is greater than the second voltage signal V2, the output of comparator COMP2 is low, and the LDR_EN signal is high. Further, the driving unit 330 generates the first switch signal HDR and the second switch signal LDR according to PWM and LDR_EN to control the upper switch Ql and the lower switch Q2 of the buck converter, respectively.

[0032] In the normal mode, the charging time T ON (Reference Figure 5 , i.e. the time for the voltage on capacitor C2 to rise from the voltage of the second voltage signal V2 to the voltage of the first voltage signal VI, i.e. the on-time of the upper switch Ql) and the discharging time T OFF , i.e. the time for the voltage on capacitor C2 to drop from the voltage of the first voltage signal VI to the voltage of the second voltage signal V2, i.e. the on-time of the lower switch Q2) can be expressed as:

[0033]

[0034]

[0035] wherein T SET = VI - V2, C is the resistance of capacitor C2, and R is the resistance of resistor RS3 and resistor RS4. As can be seen from equation 4, the on-time of the upper switch Ql is inversely proportional to the difference between the input voltage V IN and the output voltage V OUT . When the input voltage V IN decreases or the output voltage V OUT increases, the difference between the input voltage V IN and the output voltage V OUT decreases, and the on-time T ON of the upper switch Ql increases accordingly. In addition, according to the principle of the buck converter, the relationship between the input voltage V IN and the output voltage V OUT in the normal mode is:

[0036] V OUT =V IN ×DT (6)

[0037] Where DT is the duty cycle of the upper switch Q1 within one switching cycle T. (Reference) Figure 5 The sum of the conduction times of the upper switch Q1 and the lower switch Q2 is T. The duty cycle DT can be expressed as:

[0038]

[0039] As can be seen, in normal mode, the duty cycle DT changes with the input voltage V. IN and output voltage V OUT It changes dynamically with the changes.

[0040] In restricted mode, the first operational amplifier OTA1 generates a first current I. VIN The second operational amplifier OTA2 generates a second current I. VOUTMAX Assuming that the resistance of both resistors RS3 and RS4 is R, the first current I... VIN Second current I VOUTMAX It can be obtained from the following equation:

[0041]

[0042]

[0043] In restricted mode, such as Figure 4 As shown, the controller 210 controls the charging switch 404 to charge and discharge capacitor C2 via a charging signal PWM, generating a ramp signal VRAMP. (Reference) Figure 6 In the limited mode, when the PWM signal is high, switch 404 is turned on, and the first current I... VIN Capacitor C2 is charged, and simultaneously capacitor C2 is charged with a second current I. VOUTMAX Discharge. Therefore, the magnitude of the current (charging current) IRAMP of capacitor C2 is I. VIN -I VOUTMAX The voltage VRAMP across capacitor C2 increases. When VRAMP exceeds the first voltage signal V1, Figure 3 The comparator COMP1 outputs a high level to the R terminal of the RS flip-flop 320, causing the PWM to go low and the charging switch 404 to open. (Reference) Figure 4 After switch 404 is opened, capacitor C2 flows with a second current I VOUTMAX Discharge occurs, therefore the current (discharge current) IRAMP of capacitor C2 is -I VOUTMAX The voltage VRAMP across capacitor C2 decreases. When VRAMP drops below the voltage signal V2,Figure 3 The comparator COMP2 in the circuit outputs a high level. AND gate 318 performs a bitwise AND operation between the inverted PWM signal and the output of comparator COMP2, then outputs a high level to turn on switch 303. In limit mode, the output voltage V is controlled until VRAMP drops below the second voltage signal V2. OUT The voltage has dropped below the reference signal VREF, and comparator COMP3 outputs a high level. Therefore, when VRAMP drops to the second voltage signal V2, AND gate 312 outputs a high level to the S terminal of RS flip-flop 320, causing PWM to become high. The LDR_EN signal is generated by NAND gate 306 based on the output of comparator COMP2 and the inverted output of comparator COMP3. When PWM is high, switch 303 is open, charging switch 404 is closed, capacitor C2 charges, and the voltage VRAMP on capacitor C2 is greater than the second voltage signal V2. Comparator COMP2 outputs a low level, and the LDR_EN signal is high. In limit mode, before VRAMP drops to the voltage signal V2, the output voltage V... OUT When the voltage drops below the reference signal VREF, comparator COMP3 outputs a high level, and the LDR_EN signal is also high. When VRAMP drops to the second voltage signal V2, the LDR_EN signal remains high because comparator COMP3 outputs a high level. Furthermore, the drive unit 330 generates a first switching signal HDR and a second switching signal LDR based on PWM and LDR_EN to control the upper switch Q1 and lower switch Q2 of the buck converter, respectively.

[0044] In limited mode, the output voltage V OUT Restricted to V OUTMAX According to the principle of buck converter:

[0045] V OUTMAX =V IN ×DT (10)

[0046] Where DT is the duty cycle of the upper switch Q1 within one switching cycle T.

[0047] Also refer to equation (1):

[0048]

[0049] According to equations (1) and (10), the duty cycle DT in the restricted mode is DT = R2 / (R1 + R2), where DT is a constant. In the restricted mode, the charging time T of capacitor C2 is... ON (refer to Figure 6 That is, the time it takes for the voltage of capacitor C2 to rise from the voltage value of voltage signal V2 to the voltage value of voltage signal V1 (which is also the conduction time of the upper switch Q1) and the discharge time T of capacitor C2. OFF(i.e. the time for the voltage of the capacitor C2 to drop from the voltage value of the first voltage signal V1 to the voltage value of the second voltage signal V2, i.e. the on time of the lower switch Q2) can be respectively expressed as:

[0050]

[0051]

[0052] wherein T SET = V1-V2, C is the resistance value of the resistor C2, and R is the resistance value of the resistor RS3 and the resistor RS4. From equation (11), it can be seen that in the limiting mode, the on time T ON of the upper switch Q1 is irrelevant to the output voltage V OUT , thus will not cause the circuit to lose control because the values of the input voltage V IN and the output voltage V OUT are relatively close.

[0053] Figure 7 Fig. 1 shows a flow chart of a method for controlling a buck converter according to an embodiment of the present application.

[0054] In step 701, a maximum output voltage is set. In one embodiment, a voltage divider is used to divide the input voltage of the buck converter to obtain the maximum output voltage.

[0055] In step 702, the output voltage of the buck converter is monitored.

[0056] In step 703, if the output voltage is less than the maximum output voltage, a first current is generated according to the input voltage of the buck converter, and a second current is generated according to the output voltage of the buck converter.

[0057] In step 704, if the output voltage is greater than or equal to the maximum output voltage, a first current is generated according to the input voltage of the buck converter, and a second current is generated according to the maximum output voltage.

[0058] In step 705, a ramp signal is generated according to the first current and the second current. In one embodiment, the ramp signal is generated by charging and discharging a capacitor, the charging current for charging the capacitor is the difference between the first current and the second current, the discharging current of the capacitor is the second current, and the voltage on the capacitor is the ramp signal.

[0059] In step 706, first and second switch signals are generated according to the ramp signal and the first voltage signal, the second voltage signal, a reference signal and the output voltage to control the upper switch and the lower switch of the buck converter, respectively.

[0060] As mentioned above, the present application discloses a controller and a method for controlling a buck converter. When the input voltage VIN and output voltage V OUT closer, such as when output voltage V OUT greater than or equal to a preset maximum output voltage V OUTMAX , the controller enters a limit mode. In the limit mode, the duty cycle of the upper switch Q1 of the buck converter is constant, and the on time of Q1 is independent of output voltage V OUT and input voltage V IN and output voltage V OUT closer, the circuit will not be out of control, and thus the entire circuit is more stable and efficient.

[0061] The above detailed description and accompanying drawings only represent common embodiments of the present application. Obviously, various additions, modifications and substitutions can be made without departing from the spirit and scope of the present application as defined by the claims. Those skilled in the art should understand that the present application can be changed in form, structure, layout, proportion, material, element, component and other aspects without departing from the inventive principles in actual application according to specific environment and working requirements. Therefore, the embodiments disclosed herein are only for illustration and not for limitation, and the scope of the present application is defined by the appended claims and their legal equivalents, and not limited to the foregoing description.

Claims

1. A controller for controlling a buck converter, comprising: A voltage-to-current module is used to determine the operating mode of the controller based on the output voltage of the buck converter and a preset maximum output voltage. The operating modes include a normal mode and a restricted mode. In the normal mode, the voltage-to-current module generates a first current based on the input voltage of the buck converter and a second current based on the output voltage of the buck converter. In the restricted mode, the voltage-to-current module generates the first current based on the input voltage and the second current based on the maximum output voltage. A switching signal generation module is used to generate a ramp signal based on the first current and the second current, and to generate a first switching signal and a second switching signal based on the ramp signal, a first voltage signal, a second voltage signal, a reference signal, and the output voltage of the buck converter, so as to control the upper switch and the lower switch of the buck converter respectively. When the output voltage of the buck converter is greater than or equal to the maximum output voltage, the controller enters the limiting mode. In the limiting mode, the duty cycle of the upper switch of the buck converter is constant, and the conduction time of the upper switch is not related to the output voltage of the buck converter.

2. The controller according to claim 1, wherein, The voltage-to-current module includes: A first operational amplifier is used to generate the first current, wherein the positive terminal of the first operational amplifier receives the input voltage, the negative terminal and the output terminal of the first operational amplifier are connected to a first resistor, and the first current is the current flowing through the first resistor.

3. The controller according to claim 2, wherein, The voltage-to-current module includes: A maximum output voltage generation module is used to generate the maximum output voltage based on the input voltage; A voltage generation module is configured to generate a setting voltage based on the output voltage of the buck converter and the maximum output voltage; and A second operational amplifier is used to generate the second current according to the set voltage.

4. The controller according to claim 3, wherein, The voltage generation module includes: A comparator is used to compare the output voltage of the buck converter with the maximum output voltage; A selector is used to generate the set voltage based on the output of the comparator. The positive terminal of the second operational amplifier is coupled to the output terminal of the selector to receive the set voltage, and the negative terminal and output terminal of the second operational amplifier are coupled to a second resistor, wherein the second current is the current flowing through the second resistor.

5. The controller according to claim 4, wherein, If the output voltage of the buck converter is less than the maximum output voltage, the selector selects the output voltage of the buck converter as the set voltage, and the controller enters the normal mode; if the output voltage of the buck converter is greater than or equal to the maximum output voltage, the selector selects the maximum output voltage as the set voltage, and the controller enters the restricted mode.

6. The controller according to claim 4, wherein, The maximum output voltage generation module includes a voltage divider, and the maximum output voltage is obtained by dividing the input voltage by the voltage divider. The first input terminal of the comparator receives the input voltage through the voltage divider, and the second input terminal of the comparator receives the output voltage of the buck converter.

7. The controller according to claim 3, wherein, The switching signal generation module includes: A capacitor, coupled to the first operational amplifier and the second operational amplifier; A charging switch is coupled between the capacitor and the first operational amplifier. When the charging switch is turned on, the capacitor is charged by the charging current, which is the difference between the first current and the second current. When the charging switch is turned off, the capacitor generates a discharge current, which is the second current. The ramp signal is the voltage across the capacitor.

8. The controller according to claim 7, wherein, The switching signal generation module includes: A first comparator is configured to generate a first comparison result based on the first voltage signal and the ramp signal; A second comparator is used to generate a second comparison result based on the second voltage signal and the ramp signal; A third comparator is used to generate a third comparison result based on the reference signal and the output voltage of the buck converter; and An RS trigger is used to generate a charging signal based on the first comparison result, the second comparison result, and the third comparison result to control the charging switch.

9. The controller according to claim 8, wherein, The output of the first comparator is coupled to the R input of the RS flip-flop, the outputs of the second comparator and the third comparator are coupled to the S input of the RS flip-flop through an AND gate, and the Q output of the RS flip-flop outputs the charging signal.

10. The controller according to claim 8, wherein the switch signal generation module further comprises: The driving unit is configured to generate the first switching signal and the second switching signal based on the second comparison result, the third comparison result, and the charging signal.

11. A method for controlling a buck converter, comprising: Set the maximum output voltage; Monitor the output voltage of the buck converter; If the output voltage of the buck converter is less than the maximum output voltage, a first current is generated based on the input voltage of the buck converter, and a second current is generated based on the output voltage of the buck converter. If the output voltage of the buck converter is greater than or equal to the maximum output voltage, the first current is generated based on the input voltage, and the second current is generated based on the maximum output voltage; A ramp signal is generated based on the first current and the second current; as well as Based on the ramp signal, the first voltage signal, the second voltage signal, the reference signal, and the output voltage of the buck converter, a first switching signal and a second switching signal are generated to control the upper and lower switches of the buck converter, respectively. When the output voltage of the buck converter is greater than or equal to the maximum output voltage, the controller enters a limiting mode. In the limiting mode, the duty cycle of the upper switch of the buck converter is constant, and the conduction time of the upper switch is not related to the output voltage of the buck converter.

12. The method according to claim 11, wherein, The steps for setting the maximum output voltage include: The input voltage is divided using a voltage divider to obtain the maximum output voltage.

13. The method of claim 11, further comprising: The capacitor is charged and discharged to generate the ramp signal.

14. The method according to claim 13, wherein, The charging current for the capacitor is the difference between the first current and the second current, the discharging current generated by the capacitor is the second current, and the ramp signal is the voltage across the capacitor.

15. The method according to claim 14, wherein, The steps of charging and discharging the capacitor to generate the ramp signal include: A first comparison result is generated based on the first voltage signal and the ramp signal; A second comparison result is generated based on the second voltage signal and the ramp signal; A third comparison result is generated based on the reference signal and the output voltage of the buck converter; and A charging signal is generated based on the first comparison result, the second comparison result, and the third comparison result to control the charging switch coupled to the capacitor. When the charging switch is turned on, the capacitor is charged by the charging current; when the charging switch is turned off, the capacitor generates the discharging current.

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