Controller of power conversion circuit and control method of output stage of power conversion circuit

Abstract

The invention discloses a controller of a power conversion circuit and a control method of an output stage of the power conversion circuit. The controller is coupled to the output stage and provides a pulse width modulation signal to control the output stage to generate an output voltage and an output current. The controller comprises a control circuit, a mode judging circuit and an adjusting circuit. The control circuit is coupled to the output stage and generates a pulse width modulation signal to the output stage. The mode determination circuit is coupled to the output stage. When the power conversion circuit enters the light load mode, the mode judgment circuit generates a starting signal according to the output current. The adjusting circuit is respectively coupled to the output stage, the mode judging circuit and the control circuit. When the enabling signal enables the adjusting circuit, the adjusting circuit generates a first adjusting signal to the control circuit according to a feedback voltage related to the output voltage and a first reference value so as to adjust the pulse width modulation signal. According to the controller of the power conversion circuit and the control method of the output stage of the controller, noise in an audio range during light-load application can be avoided, efficiency loss of a fixed-on-time (COT) buck converter caused by the audio noise is avoided, and overlarge ripple of output voltage is avoided.

Description

Technical Field

[0001] This invention relates to power conversion circuits, and more particularly to a controller for a power conversion circuit and a control method for its output stage. Background Technology

[0002] like Figure 1 As shown, a conventional buck converter 1 with a fixed on-time (COT) converts the input voltage VIN into a stable output voltage VOUT to provide the load current ILD. The positive input terminal + of the comparator CM of the buck converter 1 receives the compensation signal COMP generated by the operational amplifier EA based on the reference voltage VREF and the feedback voltage VFB, while the negative input terminal - of the comparator CM receives the ramp signal RAMP. The comparison result TR between the compensation signal COMP and the ramp signal RAMP output by the comparator CM is sent to the fixed on-time trigger circuit TG. The fixed on-time trigger circuit TG generates a trigger signal STG with a fixed on-time TON, which is sent to the first drive circuit DR1 and the second drive circuit DR2. This causes the first drive circuit DR1 and the second drive circuit DR2 to respectively output pulse width modulation (PWM) signals to control the switching operation between the high-side switch HS and the low-side switch LS in the output stage OS.

[0003] However, in light-load applications, the switching frequency of the high-side switch HS and the low-side switch LS in the output stage OS may decrease to the audible audio range (i.e., 20Hz to 20kHz). Additionally, due to the inverse piezoelectric effect of capacitor materials, electrical energy applied to the input capacitor of a buck converter or the output capacitor of a boost converter is converted into mechanical energy, causing the capacitor to vibrate. If the vibration frequency is within the audio range, this is considered noise.

[0004] like Figure 2A and Figure 2B As shown, the switching cycle TSW includes the on-time TON and the off-time TOFF. On and off are based on the high-side switch HS. The pulse width modulation (PWM) signal has a high level during the on-time TON and a low level during the off-time TOFF. To avoid the switching frequency in the output stage OS dropping to the audio range, the current solution is to set a minimum switching frequency (e.g., 25kHz / 40us). When 40us is elapsed (time t1), the low-side switch LS is turned on first, pulling the output voltage VOUT low through a negative current, causing the circuit to enter the on-time TON of the next switching cycle at time t2.

[0005] However, since the existing method requires first lowering the output voltage VOUT, without load and without fine-tuning the fixed on-time TON of the trigger signal STG, the output voltage VOUT will gradually increase and exceed the safe value.

[0006] Therefore, the above-mentioned problems still need to be further resolved. Summary of the Invention

[0007] In view of this, the present invention proposes a controller for a power conversion circuit and a control method for its output stage, so as to effectively solve the above-mentioned problems encountered in the prior art.

[0008] According to one embodiment of the present invention, a controller for a power conversion circuit is provided. In this embodiment, the controller of the power conversion circuit is coupled to an output stage. The controller provides a pulse width modulation (PWM) signal to control the output stage to generate an output voltage and an output current. The controller includes a control circuit, a mode determination circuit, and an adjustment circuit. The control circuit is coupled to the output stage and generates a PWM signal to the output stage. The mode determination circuit is coupled to the output stage. When the power conversion circuit enters a light-load mode, the mode determination circuit generates an enable signal based on the output current. The adjustment circuit is coupled to the output stage, the mode determination circuit, and the control circuit. When the enable signal activates the adjustment circuit, the adjustment circuit generates a first adjustment signal to the control circuit based on a feedback voltage related to the output voltage and a first reference value to adjust the PWM signal.

[0009] In one embodiment, under light load mode, when the feedback voltage is greater than a first reference value, the first adjustment signal is used to shorten the conduction time of the pulse width modulation signal.

[0010] In one embodiment, the adjustment circuit includes a first adjustment unit and a second adjustment unit. The first adjustment unit generates a first adjustment signal to the control circuit based on a feedback voltage and a first reference value. The second adjustment unit generates a second adjustment signal to the control circuit based on a feedback voltage and a second reference value to adjust the off-time of the pulse width modulation signal.

[0011] In one embodiment, under light load mode, when the feedback voltage is greater than the second reference value, the second adjustment signal is used to extend the off-time of the pulse width modulation signal.

[0012] In one embodiment, the control circuit adjusts the on-time and off-time of the pulse width modulation signal according to the first adjustment signal and the second adjustment signal, respectively, so as to maintain the switching frequency of the output stage outside the audio frequency range.

[0013] In one embodiment, the first adjustment unit and the second adjustment unit generate a first current signal and a second current signal respectively through a transconductance amplifier based on the feedback voltage, a first reference value and a second reference value, so as to change the on-time and off-time of the pulse width modulation signal.

[0014] In one embodiment, the first adjustment unit and the second adjustment unit change the on-time and off-time of the pulse width modulation signal through a compensation signal.

[0015] According to another embodiment of the present invention, a control method for the output stage of a power conversion circuit is provided. In this embodiment, the output stage includes a high-side switch and a low-side switch. The output stage is controlled by a pulse-width modulation signal to generate an output voltage and an output current. The control method includes the following steps: when the switching frequency of the high-side switch and the low-side switch of the output stage decreases to a threshold frequency, fixing the switching frequency at the threshold frequency; generating a transfer current based on the voltage difference between the feedback voltage of the output voltage and the reference voltage; and delaying the turn-off time of the low-side switch based on the transfer current.

[0016] Compared with existing technologies, the controller for the power conversion circuit and the control method for its output stage proposed in this invention can achieve the following specific effects:

[0017] (1) Avoid noise in the audio range when using lightly loaded applications;

[0018] (2) To avoid efficiency loss caused by audio noise in fixed on-time (COT) buck converters; and

[0019] (3) Avoid excessive output voltage ripple.

[0020] The advantages and spirit of the present invention can be further understood through the following detailed embodiments and accompanying drawings. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a buck converter with a fixed on-time in the prior art.

[0022] Figure 2A and Figure 2B The waveforms of inductor current, output voltage, and pulse width modulation signal in the prior art are shown.

[0023] Figure 3 This is a schematic diagram of the controller of a power conversion circuit according to a specific embodiment of the present invention.

[0024] Figure 4 for Figure 3 A schematic diagram of the adjustment circuit.

[0025] Figure 5 and Figure 6 These are schematic diagrams of controllers for power conversion circuits according to other specific embodiments of the present invention.

[0026] Figure 7 The waveforms are shown for the voltage difference between the feedback voltage and the first reference value, the voltage difference between the feedback voltage and the second reference value, the output voltage, the node voltage, and the inductor current, respectively.

[0027] Figure 8This is a flowchart of a control method for the output stage of a power conversion circuit according to another specific embodiment of the present invention.

[0028] Explanation of key component symbols:

[0029] 1…Step-down converter

[0030] 3…Power conversion circuit

[0031] 30… Controller

[0032] 300… control circuit

[0033] 302…Mode Detection Circuit

[0034] 304… Adjustment Circuit

[0035] 306…compensation circuit

[0036] OS…output level

[0037] TR… Comparison Results

[0038] PWM...Pulse Width Modulation Signal

[0039] VOUT…output voltage

[0040] ISEN… Output Current

[0041] EN… Enable signal

[0042] VFB…feedback voltage

[0043] VREF1…First Reference Value

[0044] VREF2…Second Reference Value

[0045] ADJ1…First Adjustment Signal

[0046] ADJ2…Second Adjustment Signal

[0047] 304A…First Adjustment Unit

[0048] 304B…Second Adjustment Unit

[0049] TG… Fixed On-Time Trigger Circuit

[0050] DR1…First drive circuit

[0051] DR2…Second drive circuit

[0052] ZCD…Zero Current Detection Circuit

[0053] DL...delay circuit

[0054] OTA1…First transconductance amplifier

[0055] OTA2…Second transconductance amplifier

[0056] ICOMP1…First Current Signal

[0057] ICOMP2…Second Current Signal

[0058] STG…trigger signal

[0059] EA…Operational Amplifier

[0060] CM...comparator

[0061] R…resistance

[0062] C…capacitor

[0063] GND…Ground terminal

[0064] COMP…compensation signal

[0065] RAMP…Ramp Signal

[0066] +…positive input terminal

[0067] -…Negative input terminal

[0068] HS…High-side switch

[0069] LS…low-side switch

[0070] SW... Switch Node

[0071] VSW…node voltage

[0072] VIN…Input voltage

[0073] L…Inductor

[0074] IL…Inductor current

[0075] CO…output capacitor

[0076] ILD…load current

[0077] LC... Low-clamp circuit

[0078] t1~t4…time

[0079] ΔT…delay time

[0080] TSW... Switching Cycle

[0081] TON…conduction time

[0082] TOFF…Shutdown time

[0083] VFB-VREF1… Voltage difference between feedback voltage and first reference value

[0084] VFB-VREF2… Voltage difference between feedback voltage and second reference value

[0085] VOFF1…First shutdown voltage value

[0086] VOFF2…Second turn-off voltage value

[0087] IL1…positive inductor current value

[0088] IL2…negative inductor current value

[0089] ta…time

[0090] tb…time

[0091] zc…zero current point

[0092] S10~S60…Steps Detailed Implementation

[0093] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Elements / components referred to by the same or similar reference numerals in the drawings and embodiments are used to represent the same or similar parts.

[0094] According to a specific embodiment of the present invention, a controller for a power conversion circuit is provided. In this embodiment, the power conversion circuit may be a buck converter or a boost converter with a fixed on-time (COT), but is not limited thereto.

[0095] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the controller for the power conversion circuit in this embodiment. (See diagram below.) Figure 3 As shown, the power conversion circuit 3 includes a controller 30 and an output stage OS. The controller 30 is coupled to the output stage OS and provides a pulse width modulation (PWM) signal to control the output stage OS to generate an output voltage VOUT and an output current ISEN.

[0096] The controller 30 includes a control circuit 300, a mode determination circuit 302, an adjustment circuit 304, and a compensation circuit 306. The control circuit 300 is coupled to the output stage OS, the adjustment circuit 304, and the compensation circuit 306. The mode determination circuit 302 is coupled to the output stage OS and the adjustment circuit 304. The adjustment circuit 304 is coupled to the output stage OS, the control circuit 300, and the mode determination circuit 302. The compensation circuit 306 is coupled to the output stage OS and the control circuit 300.

[0097] The control circuit 300 generates a pulse width modulation (PWM) signal to the output stage OS. The compensation circuit 306 receives a feedback voltage VFB related to the output voltage VOUT and generates a comparison result TR based on the feedback voltage VFB to the control circuit 300 to compensate for the on-time (coarse adjustment) of the PWM signal generated by the control circuit 300.

[0098] When the power conversion circuit 3 enters the light load mode, the mode determination circuit 302 generates an enable signal EN to the adjustment circuit 304 based on the output current ISEN of the output stage OS. The adjustment circuit 304 receives the first reference value VREF1, the second reference value VREF2, and the feedback voltage VFB related to the output voltage VOUT.

[0099] When the enable signal EN activates the adjustment circuit 304, the adjustment circuit 304 generates a first adjustment signal ADJ1 to the control circuit 300 based on the feedback voltage VFB and the first reference value VREF1, and generates a second adjustment signal ADJ2 to the control circuit 300 based on the feedback voltage VFB and the second reference value VREF2. The control circuit 300 adjusts the on-time TON and off-time TOFF of the pulse width modulation signal PWM according to the first adjustment signal ADJ1 and the second adjustment signal ADJ2, respectively, to maintain the switching frequency of the output stage OS outside the audio frequency range.

[0100] It should be noted that in light load mode, when the feedback voltage VFB is greater than the first reference value VREF1, the adjustment circuit 304 provides the control circuit 300 with the first adjustment signal ADJ1 to shorten the conduction time TON of the pulse width modulation signal PWM; in light load mode, when the feedback voltage VFB is greater than the second reference value VREF2, the adjustment circuit 304 provides the control circuit 300 with the second adjustment signal ADJ2 to extend the off-time TOFF of the pulse width modulation signal PWM.

[0101] Please refer to Figure 4 The adjustment circuit 304 includes a first adjustment unit 304A and a second adjustment unit 304B. The first adjustment unit 304A generates a first adjustment signal ADJ1 to the control circuit 300 based on the feedback voltage VFB and a first reference value VREF1, thereby adjusting the on-time TON of the pulse width modulation signal PWM. The second adjustment unit 304B generates a second adjustment signal ADJ2 to the control circuit 300 based on the feedback voltage VFB and a second reference value VREF2, thereby adjusting the off-time TOFF of the pulse width modulation signal PWM.

[0102] In fact, the first adjustment unit 304A and the second adjustment unit 304B of the adjustment circuit 304 can generate the first current signal ICOMP1 and the second current signal ICOMP2 respectively according to the feedback voltage VFB, the first reference value VREF1 and the second reference value VREF2 through the transconductance amplifier (OTA) to change the on-time TON and off-time TOFF of the pulse width modulation signal PWM.

[0103] For example, such as Figure 5 As shown, the control circuit 300 includes a fixed on-time trigger circuit TG, a first drive circuit DR1, a second drive circuit DR2, a zero-current detection circuit ZCD, and a delay circuit DL. The fixed on-time trigger circuit TG is coupled to the first adjustment unit 304A, the compensation circuit 306, and the first drive circuit DR1 of the adjustment circuit 304. The first drive circuit DR1 is coupled to the control terminal of the high-side switch HS of the output stage OS. The zero-current detection circuit ZCD is coupled between the switching node SW and the delay circuit DL. The delay circuit DL is coupled to the second adjustment unit 304B, the zero-current detection circuit ZCD, and the second drive circuit DR2 of the adjustment circuit 304. The second drive circuit DR2 is coupled to the control terminal of the low-side switch LS of the output stage OS.

[0104] The first adjustment unit 304A includes a first transconductance amplifier OTA1, and the second adjustment unit 304B includes a second transconductance amplifier OTA2. In practice, the first transconductance amplifier OTA1 and the second transconductance amplifier OTA2 can be combined together, or they can be combined with the error amplifier of a conventional COT architecture to significantly reduce the area of ​​the circuit design.

[0105] The positive input terminal + and negative input terminal - of the first transconductance amplifier OTA1 receive the first reference value VREF1 and the feedback voltage VFB, respectively. The voltage difference (VFB-VREF1) between the feedback voltage VFB and the first reference value VREF1 is converted into a first current signal ICOMP1, which is output as the first adjustment signal ADJ1 to the fixed-on-time trigger circuit TG of the control circuit 300. This shortens the on-time TON of the pulse width modulation signal PWM, causing the maximum output voltage VOUT to decrease and remain below a safe value. Assuming the transconductance of the first transconductance amplifier OTA1 is GM1, the current value of the first current signal ICOMP1 will be equal to the voltage difference (VFB-VREF1) between the feedback voltage VFB and the first reference value VREF1 multiplied by the transconductance value GM1 of the first transconductance amplifier OTA1.

[0106] Similarly, the positive input terminal + and negative input terminal - of the second transconductance amplifier OTA2 receive the second reference value VREF2 and the feedback voltage VFB, respectively. The voltage difference (VFB-VREF2) between the feedback voltage VFB and the second reference value VREF2 is converted into a second current signal ICOMP2, which is output as the second adjustment signal ADJ2 to the delay circuit DL of the control circuit 300 to change the off-time TOFF of the pulse width modulation signal PWM. Assuming the transconductance value of the second transconductance amplifier OTA2 is GM2, the current value of the second current signal ICOMP2 will be equal to the voltage difference (VFB-VREF2) between the feedback voltage VFB and the second reference value VREF2 multiplied by the transconductance value GM2 of the second transconductance amplifier OTA2.

[0107] The zero-current detection circuit ZCD detects whether the switching node SW has zero current and transmits the detection result to the delay circuit DL. After the zero-current detection circuit ZCD detects the zero-current detection point, the delay circuit DL delays the turn-off time TOFF of the low-side switch LS (note that the turn-off time TOFF is based on the high-side switch HS) by a delay time ΔT according to the second adjustment signal ADJ2. This prolongs the conduction time of the low-side switch LS, making the inductor current IL negative and ensuring that the feedback voltage VFB does not exceed the second reference value VREF2. In other words, the voltage difference (VFB-VREF2) between the feedback voltage VFB and the second reference value VREF2 will not be greater than zero. After the delay time ΔT ends, the low-side switch LS turns off, and the negative inductor current IL is reverse-boosted back to the input voltage VIN to improve the conversion efficiency of the power conversion circuit 3.

[0108] It should be noted that by delaying the time after the zero-current detection point, rather than forcing the low-side switch LS to turn on and causing the voltage to drop, the feedback voltage VFB will not be lower than the second reference value VREF2. This results in a larger minimum output voltage VOUT, effectively improving the problem of large ripple. Furthermore, since the feedback voltage VFB will not be lower than the second reference value VREF2, the power conversion circuit 3 loses less energy and has higher conversion efficiency.

[0109] In another embodiment, such as Figure 6 As shown, the adjustment circuit 304 includes a low-clamp circuit LC, which receives the compensation signal COMP and generates a first current signal ICOMP1 and a second current signal ICOMP2 according to the compensation signal COMP, respectively, as the first adjustment signal ADJ1 and the second adjustment signal ADJ2. These signals are then output to the fixed on-time trigger circuit TG and the delay circuit DL of the control circuit 300 to change the on-time TON and off-time TOFF of the pulse width modulation signal PWM.

[0110] Please refer toFigure 7 When the switching frequency of the output stage OS drops to the minimum switching frequency threshold (e.g., audio range) of 30kHz, it will enter ultrasonic operating mode (USM) after one switching cycle TSW of the low-side switch LS.

[0111] Starting at time ta, the node voltage VSW of the switching node SW will rise from 0V to the input voltage VIN, and the inductor current IL will correspondingly rise from 0A to a positive inductor current value IL1, and then begin to decrease from the positive inductor current value IL1 along a slope. When the inductor current IL drops to 0A, the zero current detection circuit ZCD will detect that the switching node SW has zero current; this time is called the zero current point ZC.

[0112] During the period from time ta to the zero current point ZC, the voltage difference (VFB-VREF1) between the feedback voltage VFB and the first reference value VREF1 will be greater than the first turn-off voltage value VOFF1. Similarly, the voltage difference (VFB-VREF2) between the feedback voltage VFB and the second reference value VREF2 will be greater than the second turn-off voltage value VOFF2. This means that the output voltage VOUT related to the feedback voltage VFB will rise because the energy consumed by the load is less than the energy provided by the high-side switch HS, until the zero current point ZC.

[0113] As can be seen from the foregoing, the present invention can reduce the conduction time TON of the pulse width modulation signal PWM by using the first current signal ICOMP1, which is the first adjustment signal ADJ1, and the conduction time TON of the pulse width modulation signal PWM will have a minimum value, for example, about 30ns, but is not limited thereto.

[0114] Starting from the zero-current point ZC, the inductor current IL begins to become negative until time tb drops to a negative inductor current value IL2, and the output voltage VOUT will correspondingly begin to decrease. Under heavy load, the low-side switch LS will turn off at the zero-current point ZC, so the turn-off time TOFF of the low-side switch LS (note that the turn-off time TOFF is based on the high-side switch HS) is from time ta to the zero-current point ZC. However, under light load, this invention will delay the turn-off time TOFF of the low-side switch LS by a delay time ΔT according to the second adjustment signal ADJ2 through the delay circuit DL. Therefore, the turn-off time TOFF of the low-side switch LS will become from time ta to time tb. At this time, due to the negative inductor current IL causing reverse boost, the node voltage VSW of the switching node SW will rise from 0V to the input voltage VIN again, thereby improving the conversion efficiency of the power conversion circuit 3.

[0115] According to another embodiment of the present invention, there is a control method for the output stage of a power conversion circuit. In this embodiment, the output stage includes a high-side switch and a low-side switch, and the high-side switch and the low-side switch are switched at a switching frequency. The output stage is controlled by a pulse width modulation signal to generate an output voltage and an output current.

[0116] Please refer to Figure 8 The control method for the output stage of the power conversion circuit includes the following steps:

[0117] Step S10: Determine whether the switching frequency of the output stage has decreased to a threshold frequency (e.g., audio range);

[0118] Step S20: If the judgment result of step S10 is yes, that is, the switching frequency of the output stage has been reduced to the threshold frequency, the switching frequency is fixed at the threshold frequency; if the judgment result is no, that is, the switching frequency of the output stage has not been reduced to the threshold frequency, step S10 is executed again.

[0119] Step S30: Generate a transfer current based on the voltage difference between the feedback voltage of the output voltage and the reference voltage;

[0120] Step S40: Delay the turn-off time of the low-side switch by a certain delay time according to the transfer current;

[0121] Step S50: Determine whether the delay period has ended;

[0122] Step S60: If the judgment result of step S50 is yes, that is, the delay time has ended, turn off the low-side switch; if the judgment result is no, that is, the delay time has not ended, repeat step S50.

[0123] Compared with existing technologies, the controller for the power conversion circuit and the control method for its output stage proposed in this invention can achieve the following specific effects:

[0124] (1) Avoid noise in the audio range when using lightly loaded applications;

[0125] (2) To avoid efficiency loss caused by audio noise in fixed on-time (COT) buck converters; and

[0126] (3) Avoid output voltage exceeding safe value.

Claims

1. A controller for a power conversion circuit, coupled to an output stage, characterized in that, The controller provides a pulse width modulation signal to control the output stage to generate output voltage and output current. The controller includes: The control circuit, coupled to the output stage, generates the pulse width modulation signal to the output stage; A mode determination circuit, coupled to the output stage, generates an enable signal based on the output current when the power conversion circuit enters a light-load mode; and An adjustment circuit is coupled to the output stage, the mode determination circuit, and the control circuit respectively. When the enable signal activates the adjustment circuit, the adjustment circuit generates a first adjustment signal to the control circuit based on the feedback voltage related to the output voltage and a first reference value, so as to adjust the pulse width modulation signal.

2. The controller for the power conversion circuit as described in claim 1, characterized in that, In the light load mode, when the feedback voltage is greater than the first reference value, the first adjustment signal is used to shorten the conduction time of the pulse width modulation signal.

3. The controller for the power conversion circuit as described in claim 1, characterized in that, The adjustment circuit includes: The first adjustment unit generates the first adjustment signal to the control circuit based on the feedback voltage and the first reference value, so as to adjust the on-time of the pulse width modulation signal; and The second adjustment unit generates a second adjustment signal to the control circuit based on the feedback voltage and the second reference value, so as to adjust the off time of the pulse width modulation signal.

4. The controller for the power conversion circuit as described in claim 3, characterized in that, In the light-load mode, when the feedback voltage is greater than the second reference value, the second adjustment signal is used to extend the off-time of the pulse width modulation signal.

5. The controller for the power conversion circuit as described in claim 3, characterized in that, The control circuit adjusts the on-time and off-time of the pulse width modulation signal according to the first adjustment signal and the second adjustment signal, respectively, so as to maintain the switching frequency of the output stage outside the audio frequency range.

6. The controller for the power conversion circuit as described in claim 3, characterized in that, The first adjustment unit and the second adjustment unit generate a first current signal and a second current signal respectively through a transconductance amplifier based on the feedback voltage, the first reference value and the second reference value, so as to change the on-time and the off-time of the pulse width modulation signal.

7. The controller for the power conversion circuit as described in claim 3, characterized in that, The first adjustment unit and the second adjustment unit change the on-time and off-time of the pulse width modulation signal through a compensation signal.

8. A control method for the output stage of a power conversion circuit, characterized in that, The output stage includes a high-side switch and a low-side switch. The output stage is controlled by a pulse-width modulation signal to generate output voltage and output current. The control method includes the following steps: When the switching frequency of the high-side switch and the low-side switch of the output stage decreases to the threshold frequency, the switching frequency is fixed at the threshold frequency. A transfer current is generated based on the voltage difference between the feedback voltage of the output voltage and the reference voltage; as well as The turn-off time of the low-side switch is delayed according to the transfer current.

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