High-side mosfet switch chip with short circuit protection and short circuit protection control method thereof

Abstract

The application provides a high-side MOSFET switch chip with short-circuit protection and a short-circuit protection control method thereof, and aims to solve the technical problem that the existing high-side MOSFET switch chip is easy to burn the power MOS tube when the output is short-circuited. The high-side MOSFET switch chip comprises a charge pump, an oscillator, a logic control unit, a linear voltage stabilizer, a power MOS tube and a short-circuit protection unit. The short-circuit protection unit is connected with a VBB pin, a high-side power supply voltage Vs, an OUT pin and a power MOS tube GATE driving end, respectively, and comprises a first-stage Von detection circuit, a second-stage Von detection and clamping current limiting circuit, a delay time generation circuit and an enable signal generation circuit. When certain threshold voltage and delay requirements are met, the short-circuit protection unit pulls down the GATE driving end voltage to turn off the power MOS tube and lock the short-circuit protection state, or clamps the voltage drop between the GATE driving end and the VOUT pin to a clamping voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to a high side MOSFET switch chip, in particular to a high side MOSFET switch chip with short circuit protection. BACKGROUND

[0002] The high side MOSFET switch chip is an electronic device for replacing relays or fuses, which is generally placed in the high side of a branch of the automobile power supply, and can provide switching power supply and self-detection.

[0003] Figure 1 It is the system structure and pin diagram of the existing high side MOSFET switch chip. If the chip output is short-circuited, a large current will flow through the power MOS tube, and even burn the power MOS tube. If the existing short circuit protection unit is directly added to the chip, the short circuit protection unit must add a delay circuit, so that the on voltage Von is greater than the set value after a delay time, the power MOS tube is turned off, otherwise the short circuit protection unit without delay circuit will cause the output voltage Vout of the VOUT pin to suddenly change when the inductive load is connected, which will cause the short circuit protection to be triggered, and then the system will restart. Therefore, the existing short circuit protection unit is not suitable for application in the high side MOSFET switch chip. SUMMARY

[0004] The present application aims to provide a high side MOSFET switch chip with short circuit protection and a short circuit protection control method thereof, which solves the technical problem that the existing high side MOSFET switch chip is easy to burn the power MOS tube when the output is short-circuited.

[0005] To achieve the above-mentioned purpose, the technical solution of the present application is:

[0006] A short circuit protection control method of a high side MOSFET switch chip, which is characterized in that:

[0007] After starting, the input voltage of the IN pin is sent to the high side MOSFET switch chip, the high side power supply voltage Vs is output through the linear voltage stabilizer, and the short circuit protection unit performs first Von detection and second Von detection;

[0008] The first Von detection refers to that if the turn-on voltage Von is greater than the first short-circuit threshold voltage Vth1 and the maintaining time exceeds the first delay time Tdelay1, the chip internal driving signal inL is generated as a short-circuit protection signal after the second delay time Tdelay2, the GATE driving end voltage is pulled down, so as to turn off the power MOS tube and lock the short-circuit protection state; if the turn-on voltage Von is greater than the first short-circuit threshold voltage Vth1 and the maintaining time does not exceed the first delay time Tdelay1, the voltage drop of the GATE driving end and the OUT pin is clamped to the clamping voltage;

[0009] The second Von detection refers to that if the turn-on voltage Von is greater than the third short-circuit threshold voltage Vth3 and less than the first short-circuit threshold voltage Vth1, or the turn-on voltage Von is greater than the second short-circuit threshold voltage Vth2 and less than the third short-circuit threshold voltage Vth3 and the maintaining time exceeds the second delay time Tdelay2, the voltage drop of the GATE driving end and the VOUT pin is clamped to the clamping voltage;

[0010] The first short-circuit threshold voltage Vth1 > the third short-circuit threshold voltage Vth3 > the second short-circuit threshold voltage Vth2;

[0011] The second delay time Tdelay2 > the first delay time Tdelay1.

[0012] Further, the first Von detection is specifically that in the current mirror circuit, the reference current generated by the voltage drop of the second voltage stabilizing tube added to the reference resistor R1 is compared with the detection current generated by the turn-on voltage Von added to the detection resistor R2, so as to judge whether the turn-on voltage Von reaches the first short-circuit threshold voltage Vth1; if the turn-on voltage Von is always greater than the first short-circuit threshold voltage Vth1 within the first delay time Tdelay1, the chip internal driving signal inL is output as a short-circuit protection signal to pull down the GATE driving end voltage after the second delay time Tdelay2, so as to turn off the power MOS tube and lock the short-circuit protection state; if the turn-on voltage Von is greater than the first short-circuit threshold voltage Vth1 and the maintaining time does not exceed the first delay time Tdelay1, the voltage drop of the GATE driving end and the OUT pin is clamped to the clamping voltage; wherein the turn-on voltage Von refers to the difference between the input voltage Vbb of the VBB pin and the output voltage Vout of the VOUT pin, and the first short-circuit threshold voltage Vth1 has a linear relationship with the voltage drop of the second voltage stabilizing tube;

[0013] The second stage Von detection is specifically that, if the turn-on voltage Von is greater than the third short-circuit threshold voltage Vth3 and less than the first short-circuit threshold voltage Vth1, or the turn-on voltage Von is greater than the second short-circuit threshold voltage Vth2 and less than the third short-circuit threshold voltage Vth3 and the maintaining time exceeds the second delay time Tdelay2, the voltage drop of the GATE driving end and the VOUT pin is clamped to the clamping voltage; wherein the third short-circuit threshold voltage Vth3 is equal to the clamping voltage of the three field effect tubes, and the second short-circuit threshold voltage Vth2 is equal to the clamping voltage of one field effect tube; in the second delay time Tdelay2 of the second stage Von detection, the output short-circuit protection signal is shielded.

[0014] Further, the high-side power voltage Vs of the linear voltage regulator is Vbb-Vdz1+Vgs_p1, wherein Vdz1 is the voltage drop of the first voltage stabilizing tube, and Vgs_p1 is the clamping voltage of the first PMOS tube.

[0015] The clamping voltage is (R3+R4) / R3*Vgs_p17, wherein R3 is the resistance value of the third resistor R3, R4 is the resistance value of the fourth resistor, and Vgs_p17 is the clamping voltage of the seventeenth PMOS tube P17.

[0016] After a period of time of starting up and the EN enabling output, the short-circuit protection unit performs the first stage Von detection and the second stage Von detection.

[0017] The application further provides a high-side MOSFET switch chip with short-circuit protection, which is used for implementing the above method and comprises a VBB pin, an IN pin, an IS pin, an OUT pin, a charge pump, an oscillator, a logic control unit, a linear voltage regulator and a power MOS tube; the linear voltage regulator is used for generating a high-side power voltage Vs according to the input voltage of the IN pin.

[0018] The speciality thereof lies in that: it further comprises a short-circuit protection unit; the short-circuit protection unit is connected with the VBB pin, the high-side power voltage Vs, the OUT pin and the GATE driving end of the power MOS tube respectively.

[0019] The short-circuit protection unit comprises a first stage Von detection circuit, a second stage Von detection and clamping current limiting circuit, a delay time generation circuit and an enabling signal generation circuit.

[0020] The first stage Von detection circuit is used for comparing the current Ionsc generated by the turn-on voltage Von with the reference current Idz generated by the IN pin, and outputting a detection signal Vonsc, which is used for judging whether the turn-on voltage Von reaches the first short-circuit threshold voltage Vth1.

[0021] The enable signal generation circuit is used for outputting an enable signal EN after a time delay;

[0022] The delay time generation circuit is used for generating a first delay time Tdelay1 and a second delay time Tdelay2 according to the enable signal EN, and outputting a chip internal driving signal inL;

[0023] The second Von detection and clamping current limiting circuit is used for judging whether the turn-on voltage Von is greater than a third short-circuit threshold voltage Vth3 or the turn-on voltage Von is greater than a second short-circuit threshold voltage Vth2 after a time delay of the second delay time Tdelay2, and then clamping the voltage drop between the GATE driving end and the OUT pin to a clamping voltage;

[0024] The first short-circuit threshold voltage Vth1> the third short-circuit threshold voltage Vth3> the second short-circuit threshold voltage Vth2;

[0025] The second delay time Tdelay2> the first delay time Tdelay1.

[0026] Further, the first Von detection circuit comprises a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a second zener Dz2, a reference resistor R1, a detection resistor R2, a second field effect tube N2, a third field effect tube N3, a fourth NMOS tube N4, and a fifth NMOS tube N5.

[0027] The source electrodes of the fourth PMOS transistor P4, the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh PMOS transistor P7 and the eighth PMOS transistor P8 are connected to the VBB pin; the gate electrode and the drain electrode of the fourth PMOS transistor P4 are connected to the negative electrode of the second voltage stabilizing tube Dz2, the positive electrode of the second voltage stabilizing tube Dz2 is connected to the source electrode of the second PMOS transistor P2, the drain electrode and the gate electrode of the second PMOS transistor P2 are connected to the drain electrode of the second field effect transistor N2, the gate electrode and the source electrode of the second field effect transistor N2 are connected to the IN pin; the gate electrode and the drain electrode of the fifth PMOS transistor P5 are connected to one end of the reference resistor R1, the other end of the reference resistor R1 is connected to the source electrode of the third PMOS transistor P3, the gate electrode of the third PMOS transistor P3 is connected to the gate electrode of the second PMOS transistor P2, the drain electrode of the third PMOS transistor P3 is connected to the IN pin; the gate electrode of the sixth PMOS transistor P6 is connected to the gate electrode of the fifth PMOS transistor P5, the drain electrode of the sixth PMOS transistor P6 is connected to the drain electrode of the fifth NMOS transistor N5; the drain electrode of the eighth PMOS transistor P8 is connected to the drain electrode and the gate electrode of the fourth NMOS transistor N4, the source electrode of the fourth NMOS transistor N4 and the source electrode of the fifth NMOS transistor N5 are connected to the high-side power supply voltage Vs; the gate electrode of the eighth PMOS transistor P8 is connected to the gate electrode of the seventh PMOS transistor P7; the gate electrode and the drain electrode of the seventh PMOS transistor P7 are connected to one end of the detection resistor R2, the other end of the detection resistor R2 is connected to the drain electrode of the third field effect transistor N3, the gate electrode and the source electrode of the third field effect transistor N3 are connected to the OUT pin; the drain electrode of the sixth PMOS transistor P6 is used to output the detection signal Vonsc output by the first-stage Von detection circuit.

[0028] Further, the delay time generating circuit comprises a first current source I1, a first NOT gate inv1, a ninth PMOS transistor P9, a sixth NMOS transistor N6, a second capacitor C2, a seventh NMOS transistor N7, a second NOT gate inv2, a third NOT gate inv3, a second current source I2, a fourth NOT gate inv4, a tenth PMOS transistor P10, an eighth NMOS transistor N8, a third capacitor C3, a fifth NOT gate inv5, a sixth NOT gate inv6, a first NAND gate nand1, a second NAND gate nand2, a seventh NOT gate inv7.

[0029] One end of the first current source I1 is connected to the VBB pin, and the other end is connected to the source of the ninth PMOS tube P9; the input end of the first non-inverter inv1 is connected to the detection signal Vonsc output by the first Von detection circuit, and the output end is connected to the gate of the ninth PMOS tube P9 and the gate of the sixth NMOS tube N6; the drain of the ninth PMOS tube P9 and the drain of the sixth NMOS tube N6 are both connected to one end of the second capacitor C2, the drain of the seventh NMOS tube N7 and the input end of the second non-inverter inv2; the output end of the second non-inverter inv2 is connected to the input end of the third non-inverter inv3, and the output end of the third non-inverter inv3 is connected to one of the input ends of the first NAND gate nand1; the source of the sixth NMOS tube N6, the source of the seventh NMOS tube N7 and the other end of the second capacitor C2 are all connected to the high-side power supply voltage Vs;

[0030] One end of the second current source I2 is connected to the VBB pin, and the other end is connected to the source of the tenth PMOS tube P10; the input end of the fourth non-inverter inv4 is connected to the enable signal EN, and the output end is connected to the gate of the tenth PMOS tube P10 and the gate of the eighth NMOS tube N8; the drain of the tenth PMOS tube P10 and the drain of the eighth NMOS tube N8 are both connected to one end of the third capacitor C3 and the input end of the fifth non-inverter inv5; the output end of the fifth non-inverter inv5 is connected to the input end of the sixth non-inverter inv6, and the output end of the sixth non-inverter inv6 is connected to the other input end of the first NAND gate nand1; the source of the eighth NMOS tube N8 and the other end of the third capacitor C3 are both connected to the high-side power supply voltage Vs;

[0031] The output signal of the first NAND gate nand1 and the enable signal EN are sent into the two input ends of the second NAND gate nand2, and the output end of the second NAND gate nand2 is connected to the GATE drive end of the chip through the seventh non-inverter inv7; the gate of the seventh NMOS tube N7 is connected to the output end of the fourth non-inverter inv4; the output end of the third non-inverter inv3 is used to output the first delay time signal Tdelay1; the output end of the fifth non-inverter inv5 is used to output the second delay time signal Tdelay2; the output end of the second NAND gate nand2 is also connected to the input end of the second Von detection and clamping current limiting circuit.

[0032] Further, the second Von detection and clamping current limiting circuit includes a third current source I3, a current mirror composed of an eleventh PMOS tube P11 and a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a fourteenth PMOS tube P14, a fifteenth PMOS tube P15, a sixteenth PMOS tube P16, a seventeenth PMOS tube P17, a ninth NMOS tube N9, a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12, a third resistor R3, a fourth resistor R4 and a fifth resistor R5;

[0033] The input end of the third current source I3 is connected with a high side power supply voltage Vs, the output end is connected with the drain and gate of an eleventh PMOS P11 and the gate of a twelfth PMOS P12; the source of the eleventh PMOS P11 and the source of the twelfth PMOS P12 are connected with a VBB pin; the drain of the twelfth PMOS P12 is connected with the source of a thirteenth PMOS P13 and the source of a fifteenth PMOS P15; the gate and the drain of the thirteenth PMOS P13 are connected with the source of a fourteenth PMOS P14, the gate and the drain of the fourteenth PMOS P14 and the drain of the fifteenth PMOS P15 are connected with the source of a sixteenth PMOS P16; the drain of the sixteenth PMOS P16 is connected with the drain and gate of a ninth NMOS N9, the gate of a tenth NMOS N10 and the gate of an eleventh NMOS N11; the drain of the tenth NMOS N10 is connected with the gate of a power MOS, the source of a seventeenth PMOS P17 and the drain of a twelfth NMOS N12 through a fourth resistor R4 and a third resistor R3 in sequence; the gate of the seventeenth PMOS P17 is connected with the connection point of the fourth resistor R4 and the third resistor R3, the drain is connected with the drain of the eleventh NMOS N11, one end of a fifth resistor R5 and the gate of the twelfth NMOS N12; the source of the ninth NMOS N9, the source of the tenth NMOS N10, the source of the eleventh NMOS N11, the other end of the fifth resistor and the source of the twelfth NMOS N12 are connected with an OUT pin; the gate of the fifteenth PMOS P15 is used for receiving a second delay time signal Tdelay2.

[0034] Further, the enable signal generating circuit comprises an enable opening unit, a first stage hysteresis unit, a shaping and second stage hysteresis unit and a delay unit; the enable opening unit comprises a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, an eighteenth PMOS P18 and a ninth resistor R9; the first stage hysteresis unit comprises a seventeenth NMOS N17; the shaping and second stage hysteresis unit comprises a nineteenth PMOS P19, a thirteenth field effect tube N13, a fourteenth NMOS N14, a fifteenth NMOS N15, an eighth non-inverter inv8 and a ninth non-inverter inv9;

[0035] The sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 are connected in series, one end of the sixth resistor R6, the source of the eighteenth PMOS P18 and the source of the nineteenth PMOS P19 are connected to the VBB pin; the drain of the eighteenth PMOS P18, the gate of the nineteenth PMOS P19 and the gate of the thirteenth NMOS N13 are connected to one end of the ninth resistor R9; the gate of the eighteenth PMOS P18 is connected to the connection point of the sixth resistor R6 and the seventh resistor R7; the connection point of the seventh resistor R7 and the eighth resistor R8 is connected to the drain of the seventeenth NMOS N17, and the gate of the seventeenth NMOS N17 is connected to the output end of the eighth inverter inv8; the drain of the nineteenth PMOS P19 and the drain of the thirteenth NMOS N13 are both connected to the input end of the eighth inverter inv8; the source of the thirteenth NMOS N13 and the drain of the fifteenth NMOS N15 are both connected to the drain and the gate of the fourteenth NMOS N14; the gate of the fifteenth NMOS N15 and the output end of the eighth inverter inv8 are both connected to the input end of the ninth inverter inv9; the output end of the ninth inverter inv9 is connected to the input end of the delay unit; and the delay unit is used for delaying the output enable signal EN.

[0036] The source of the seventeenth NMOS N17, the other end of the eighth resistor R8, the other end of the ninth resistor R9, the source of the fourteenth NMOS N14 and the source of the fifteenth NMOS N15 are all connected to the high-side power supply voltage Vs.

[0037] Further, the delay unit comprises a fourth current source I4, a twentieth PMOS P20, a sixteenth NMOS N16, a fourth capacitor C4, a tenth inverter inv10 and an eleventh inverter inv11.

[0038] The input end of the fourth current source I4 is connected to the VBB pin, and the output end is connected to the source of the twentieth PMOS P20; the gate of the twentieth PMOS P20 and the gate of the sixteenth NMOS N16 are both connected to the output end of the ninth inverter inv9; the drain of the twentieth PMOS P20 and the drain of the sixteenth NMOS N16 are connected to one end of the fourth capacitor C4, and output the enable signal EN after passing through the tenth inverter inv10 and the eleventh inverter inv11 in sequence; the source of the sixteenth NMOS N16 and the other end of the fourth capacitor C4 are both connected to the high-side power supply voltage Vs.

[0039] Further, the linear voltage stabilizer is a low-dropout linear voltage stabilizer, comprising a first voltage stabilizing tube Dz1, a first field effect tube N1, a first PMOS tube P1 and a first capacitor C1; wherein: a negative electrode of the first voltage stabilizing tube Dz1 is connected with a VBB pin and one end of the first capacitor C1, the other end of the first capacitor C1 is connected with a source electrode of the first PMOS tube P1, a gate electrode of the first PMOS tube P1 is connected with a positive electrode of the first voltage stabilizing tube Dz1 and a drain electrode of the first field effect tube N1, a gate electrode and a source electrode of the first field effect tube N1 are connected with an IN pin and a drain electrode of the first PMOS tube P1; and the source electrode of the first PMOS tube P1 is used for outputting a high-side power supply voltage Vs.

[0040] The first field effect tube N1, the second field effect tube N2 and the third field effect tube N3 are high-voltage depletion-mode or JEFT field effect tubes.

[0041] The first PMOS tube P1, the second PMOS tube P2 and the third PMOS tube P3 are high-voltage PMOS tubes.

[0042] The fourth PMOS tube P4, the fifth PMOS tube P5, the sixth PMOS tube P6, the seventh PMOS tube P7 and the eighth PMOS tube P8 are low-voltage PMOS tubes.

[0043] The sixteenth PMOS tube P16 is a high-voltage PMOS tube.

[0044] The reference resistor R1 and the detection resistor R2 are resistors of the same type, consistent width-length ratio and high matching.

[0045] The beneficial effects of the present application are as follows:

[0046] 1. The short-circuit protection unit is added in the high-side MOSFET switch chip, and the short-circuit protection unit generates a short-circuit protection signal when the chip is short-circuited, so as to pull down the gate drive voltage Vgs of the power MOS tube or turn off the power MOS tube and lock the protection state, so as to achieve the purpose of current limiting and protect the power MOS tube. Specifically, the unit compares the on voltage Von with the first short-circuit threshold voltage Vth1, the second short-circuit threshold voltage Vth2 and the third short-circuit threshold voltage Vth3 to protect the power MOS tube from short circuit or voltage clamping.

[0047] 2. The low-dropout linear voltage stabilizer is adopted to realize the high-side power supply, and the low-voltage devices are used to complete the function design of short-circuit protection, so as to save the area and simplify the circuit design.

[0048] 3. The short-circuit protection unit added in the present application does not affect the normal work of the high-side MOSFET switch chip. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 is the system structure diagram of the prior high-side MOSFET switch chip;

[0050] Figure 2 is the external connection relationship diagram of the short-circuit protection unit in the high-side MOSFET switch chip of the present application;

[0051] Figure 3 is the flow chart of the short-circuit protection method in the present application;

[0052] Figure 4 is the schematic diagram of the low-dropout linear regulator (LDO) in the present application;

[0053] Figure 5 is the schematic diagram of the first-stage Von detection circuit in the short-circuit protection unit;

[0054] Figure 6 is the schematic diagram of the delay time generation circuit in the short-circuit protection unit;

[0055] Figure 7 is the schematic diagram of the second-stage Von detection and clamping current limiting circuit in the short-circuit protection unit;

[0056] Figure 8 is the schematic diagram of the enable signal generation circuit;

[0057] Figure 9 is the working waveform of each input signal after the output short-circuit:

[0058] Figure 10 is the working waveform of each input signal after the normal operation and then the output short-circuit:

[0059] Figure 11 is the working waveform of the second-stage Von detection and clamping current limiting circuit and the clamping voltage Vgs of the power MOS tube. DETAILED DESCRIPTION

[0060] Referring to Figure 2 , the present application adds an oscillator, a low-dropout linear regulator and a short-circuit protection unit in the prior high-side MOSFET switch chip, wherein the oscillator is used to provide an internal clock signal.

[0061] Figures 4 to 8 are the electrical principle schematic diagrams of the low-dropout linear regulator, the first-stage Von detection circuit, the delay time generation circuit, the second-stage Von detection and clamping current limiting circuit and the enable signal generation circuit in the high-side MOSFET switch chip with short-circuit protection of the present application.

[0062] Among them:

[0063] Figure 4The figure is a low dropout regulator (LDO) schematic diagram. The first field effect transistor N1 is a high-voltage depletion mode or JFET field effect transistor, which is used to generate a current bias. The first zener Dz1 is used as a reference voltage. The first PMOS is a high-voltage PMOS transistor, which is used to withstand high voltage. As can be seen from the figure, the output voltage of the low dropout regulator = Vbb-Vs = Vdz1-Vgs_p1.

[0064] Figure 5 The figure is a first-stage Von detection circuit. The fourth PMOS P4 to the seventh PMOS P7 are all high-side low-voltage PMOS transistors. The second PMOS P2 and the third PMOS P3 are high-voltage PMOS transistors, which are used to withstand high voltage. The field effect transistors N2 and N3 are high-voltage depletion mode or JFET field effect transistors, which work in the saturation region and are used to provide a bias current. The working principle of the first-stage Von detection circuit is that the voltage drop of the first zener is added to the reference resistor R1 to generate a reference current Idz. The on-voltage Von is added to the detection resistor R2 to generate a detection current Ionsc. According to the working principle of the current mirror, the detection current Ionsc will be compared with the reference current Idz, so as to determine whether the detection signal Vonsc reaches the first short-circuit threshold voltage Vth1.

[0065] Figure 6 The figure is a delay time generation circuit. The first current source I1, the first NOT gate inv1, the ninth PMOS P9, the sixth NMOS N6, the second capacitor C2, the seventh NMOS N7, the second NOT gate inv2, and the third NOT gate inv3 constitute a first delay time generation unit. When the ninth PMOS P9 is turned on and the sixth NMOS N6 and the seventh NMOS N7 are turned off, the first current source I1 charges the first capacitor C1 until the second NOT gate inv2 flips, and then the first delay Tdelay1 ends. The detection signal Vonsc is the detection signal output by the first-stage Von detection circuit. Similarly, the second current source I2, the fourth NOT gate inv4, the tenth PMOS P10, the eighth NMOS N8, the third capacitor C3, the fifth NOT gate inv5, and the sixth NOT gate inv6 constitute a second delay time generation unit, which is used to generate a second delay Tdelay2. The EN is an enable signal.

[0066] Figure 7is the second level Von detection and clamping current limiting circuit. In the figure, the third current source I3 provides current bias, the eleventh PMOS tube P11 and the twelfth PMOS tube P12 constitute a current mirror; the sum of the clamping voltage of the thirteenth PMOS tube P13, the fourteenth PMOS tube P14 and the ninth NMOS tube N9 is the third short-circuit threshold voltage Vth3 reference voltage; when the turn-on voltage Von=(Vbb-Vout) is greater than the third short-circuit threshold voltage Vth3 (i.e. the clamping voltage of the three field effect tubes), the tenth NMOS tube N10 is turned on, followed by the seventeenth PMOS tube P17 and the twelfth NMOS tube N12, which clamps the voltage drop of the GATE driving end and the OUT pin, and the clamping voltage is (R3+R4) / R3xVgs_p17, thereby achieving the purpose of current limiting. After the delay Tdelay2 time, if the turn-on voltage Von is greater than the second short-circuit threshold voltage Vth2 (i.e. the clamping voltage of one field effect tube), the voltage drop of the GATE driving end and the OUT pin is clamped. Among them, the sixteenth PMOS tube P16 is a high-voltage PMOS tube, which is used as a switch, and the internal driving signal inL is low only when the turn-on voltage Von is detected, i.e. the power MOS tube is in the on state.

[0067] Figure 8 is an enable signal generation circuit. In the figure, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the eighteenth PMOS tube P18, the ninth resistor R9 constitute an enable opening module; the seventeenth NMOS tube N17 is used for setting the hysteresis voltage after starting; the nineteenth PMOS tube P19, the thirteenth NMOS tube N13, the fourteenth NMOS tube N14, the fifteenth NMOS tube N15, the eighth non-inverter inv8, the ninth non-inverter inv9 constitute a shaper and a second level hysteresis, output high and low level; wherein the eighth non-inverter inv8 outputs the uvloH signal to the gate of the seventeenth NMOS tube N17; the fourth current source I4, the twentieth PMOS tube P20, the sixteenth NMOS tube N16, the fourth capacitor C4, the tenth non-inverter inv10, the eleventh non-inverter inv11 constitute a delay circuit, i.e. output the enable signal EN after a period of time.

[0068] Referring to Figure 3 , the present application realizes the short-circuit protection flow chart of the high-side MOSFET switch chip:

[0069] 1) The IN pin input signal is connected, first the linear voltage regulator inside the high-side MOSFET switch chip is established, the internal linear voltage regulator is the high-side voltage regulator, wherein the high-side power supply voltage Vs is regarded as the high-side ground; then the short-circuit protection function is realized under the high-side voltage regulator;

[0070] 2) In the second delay time Tdelay2, the output short-circuit protection signal is shielded;

[0071] At the same time, the first Von detection is carried out; if the on voltage Von > the first short-circuit threshold voltage Vth1 and the on voltage Von > the first short-circuit threshold voltage Vth1 is kept for the second delay time Tdelay1, it is determined that the output is short-circuited, and the short-circuit protection signal is pulled down to the GATE driving end to turn off the power MOS tube, and the protection state is locked;

[0072] At the same time, the second Von detection is carried out; if the on voltage Von > the third short-circuit threshold voltage Vth3, the short-circuit protection signal is pulled down to the GATE driving end and the clamping voltage Vgs of the power MOS tube is clamped to achieve the purpose of current limiting.

[0073] 3) After the second delay time Tdelay2 ends, if the on voltage Von > the second short-circuit threshold voltage Vth2, the GATE driving end is pulled down and the clamping voltage Vgs of the power MOS tube is clamped to achieve the purpose of current limiting.

[0074] Figure 9 It is the working waveform of the chip of the application when the output is short-circuited first and each input is opened. The output is short-circuited first, the input voltage is input at the IN pin at t1, the high-side power supply voltage Vs is established, the enable signal EN is triggered and the internal driving signal inL is generated after a delay at t2, then the power MOS tube is turned on, the output current IL rises, and after a delay Tdelay2, the short-circuit protection is triggered at t3, the power MOS tube is turned off, and the output current IL becomes 0.

[0075] Figure 10 It is the working waveform of the chip of the application when the output is short-circuited first and each input is opened. The output is short-circuited first, the input voltage is input at the IN pin at t1, the high-side power supply voltage Vs is established, the enable signal EN is triggered and the internal driving signal inL is generated after a delay at t2, then the power MOS tube is turned on, the output current IL rises, and after a delay Tdelay2, the short-circuit protection is triggered at t3, the power MOS tube is turned off, and the output current IL becomes 0.

[0076] Figure 11is the working waveform of the second level Von detection and clamping current limiting circuit and the clamping voltage Vgs of the power MOS. Before the input signal is turned on, the load power supply works normally. At t1, the input signal of IN pin is turned on, the high side power supply voltage Vs is established, at t2, the power MOS is turned on, the conduction voltage Von decreases, between t2 and t3, because the conduction voltage Von is greater than the third short circuit threshold voltage Vth3, the clamping voltage Vgs of the power MOS is clamped to limit the output current; until t3, the conduction voltage Von is less than the third short circuit threshold voltage Vth3, the current limiting is released, the clamping voltage Vgs of the power MOS rises to the normal voltage; after the start is completed, at t4, the load is increased, so that the conduction voltage Von is greater than the second short circuit threshold voltage Vth2, the current limiting mode is entered, the clamping voltage Vgs of the power MOS is pulled down to limit the output current, that is, after the start is completed, the threshold value of entering the current limiting mode decreases from the third short circuit threshold voltage Vth3 to the second short circuit threshold voltage Vth2, until t5, the conduction voltage Von is less than the second short circuit threshold voltage Vth2, the output current limiting is released; at t6, the output is short-circuited, the conduction voltage Von suddenly increases and is greater than the first short circuit threshold voltage Vth1, at this time, the current limiting is entered and the short circuit protection delay is started, until t7, the short circuit protection delay is ended, the short circuit protection is triggered, the power MOS is turned off, and the clamping voltage Vgs of the power MOS begins to decrease to 0.

Claims

1. A short-circuit protection control method of a high-side MOSFET switch chip, characterized in that: after starting, an input voltage of an IN pin is sent to the high-side MOSFET switch chip, a high-side power supply voltage Vs is output by a linear voltage regulator, and a first Von detection and a second Von detection are performed by a short-circuit protection unit; the first Von detection is specifically that, in a current mirror circuit, a reference current generated by applying a voltage drop of a second voltage stabilizing tube to a reference resistor R1 is compared with a detection current generated by applying a turn-on voltage Von to a detection resistor R2, so as to determine whether the turn-on voltage Von reaches a first short-circuit threshold voltage Vth1, if the turn-on voltage Von is always greater than the first short-circuit threshold voltage Vth1 within a first delay time Tdelay1, after a second delay time Tdelay2 ends, an internal driving signal inL of the chip is output as a short-circuit protection signal to pull down a voltage of a GATE driving end, so as to turn off a power MOS tube and lock a short-circuit protection state, if the turn-on voltage Von is greater than the first short-circuit threshold voltage Vth1 and a maintaining time is not more than the first delay time Tdelay1, a voltage drop between the GATE driving end and an OUT pin is clamped to a clamping voltage; wherein the turn-on voltage Von is a difference between an input voltage Vbb of a VBB pin and an output voltage Vout of the OUT pin, the first short-circuit threshold voltage Vth1 has a linear relationship with the voltage drop of the second voltage stabilizing tube; the second Von detection is specifically that, if the turn-on voltage Von is greater than a third short-circuit threshold voltage Vth3 and less than the first short-circuit threshold voltage Vth1, or the turn-on voltage Von is greater than a second short-circuit threshold voltage Vth2 and less than the third short-circuit threshold voltage Vth3 and a maintaining time is more than the second delay time Tdelay2, a voltage drop between the GATE driving end and the OUT pin is clamped to the clamping voltage; wherein the third short-circuit threshold voltage Vth3 is equal to a clamping voltage of three field effect tubes, and the second short-circuit threshold voltage Vth2 is equal to a clamping voltage of one field effect tube; during the second delay time Tdelay2 of the second Von detection, an output short-circuit protection signal is shielded; the first short-circuit threshold voltage Vth1 > the third short-circuit threshold voltage Vth3 > the second short-circuit threshold voltage Vth2; and the second delay Tdelay2 > the first delay Tdelay1. 2.The short-circuit protection control method of the high-side MOSFET switch chip according to claim 1, characterized in that: the high-side power supply voltage Vs of the linear voltage regulator is Vbb-Vdz1+Vgs_p1, wherein Vdz1 is a voltage drop of a first voltage stabilizing tube, and Vgs_p1 is a clamping voltage of a first PMOS tube; the clamping voltage is (R3+R4) / R3×Vgs_p17, wherein R3 is a resistance value of a third resistor R3, R4 is a resistance value of a fourth resistor, and Vgs_p17 is a clamping voltage of a seventeenth PMOS tube P17; and the short-circuit protection unit performs the first Von detection and the second Von detection only after a period of time after starting and an EN enabling output. ​ ​ ​ ​ ​ ​ ​ ​ 3. A short-circuit protection high-side MOSFET switch chip for implementing the method of any one of claims 1 to 2, comprising a VBB pin, an IN pin, an IS pin, an OUT pin, a charge pump, an oscillator, a logic control unit, a linear voltage regulator, and a power MOSFET; the linear voltage regulator is configured to generate a high-side power supply voltage Vs according to an input voltage of the IN pin; further comprising a short-circuit protection unit; the short-circuit protection unit is connected to the VBB pin, the high-side power supply voltage Vs, the OUT pin, and a GATE drive end of the power MOSFET, respectively; the short-circuit protection unit comprises a first Von detection circuit, a second Von detection and clamping current limiting circuit, a delay time generation circuit, and an enable signal generation circuit; the first Von detection circuit is configured to compare a current Ionsc generated by a turn-on voltage Von with a reference current Idz generated by the IN pin, and output a detection signal Vonsc, the detection signal Vonsc is configured to determine whether the turn-on voltage Von reaches a first short-circuit threshold voltage Vth1; the enable signal generation circuit is configured to output an enable signal EN after a delay; the delay time generation circuit is configured to generate a first delay Tdelay1 and a second delay Tdelay2 according to the enable signal EN, and output a chip internal drive signal inL; the second Von detection and clamping current limiting circuit is configured to determine whether the turn-on voltage Von is greater than a third short-circuit threshold voltage Vth3 or the turn-on voltage Von is greater than a second short-circuit threshold voltage Vth2 after a delay of the second delay time Tdelay2, and then clamp a voltage drop between the GATE drive end and the OUT pin to a clamping voltage; the first short-circuit threshold voltage Vth1 > the third short-circuit threshold voltage Vth3 > the second short-circuit threshold voltage Vth2; the second delay Tdelay2 > the first delay Tdelay1. characterized in that 4. The short-circuit protection high-side MOSFET switch chip of claim 3, wherein: the first Von detection circuit comprises a second PMOS P2, a third PMOS P3, a fourth PMOS P4, a fifth PMOS P5, a sixth PMOS P6, a seventh PMOS P7, an eighth PMOS P8, a second zener Dz2, a reference resistor R1, a detection resistor R2, a second field effect transistor N2, a third field effect transistor N3, a fourth NMOS N4, and a fifth NMOS N5. ​ ​ ​ ​ ​ ​ ​ ​ ​ The source of the fourth PMOS P4, the fifth PMOS P5, the sixth PMOS P6, the seventh PMOS P7 and the eighth PMOS P8 are connected to the VBB pin; the gate and the drain of the fourth PMOS P4 are connected to the negative electrode of the second voltage stabilizer Dz2, the positive electrode of the second voltage stabilizer Dz2 is connected to the source of the second PMOS P2, the drain and the gate of the second PMOS P2 are connected to the drain of the second field effect transistor N2, the gate and the source of the second field effect transistor N2 are connected to the IN pin; the gate and the drain of the fifth PMOS P5 are connected to one end of the reference resistor R1, the other end of the reference resistor R1 is connected to the source of the third PMOS P3, the gate of the third PMOS P3 is connected to the gate of the second PMOS P2, the drain of the third PMOS P3 is connected to the IN pin; the gate of the sixth PMOS P6 is connected to the gate of the fifth PMOS P5, the drain of the sixth PMOS P6 is connected to the drain of the fifth NMOS N5; the drain of the eighth PMOS P8 is connected to the drain and the gate of the fourth NMOS N4, the source of the fourth NMOS N4 and the source of the fifth NMOS N5 are connected to the high side power supply voltage Vs; the gate of the eighth PMOS P8 is connected to the gate of the seventh PMOS P7; the gate and the drain of the seventh PMOS P7 are connected to one end of the detection resistor R2, the other end of the detection resistor R2 is connected to the drain of the third field effect transistor N3, the gate and the source of the third field effect transistor N3 are connected to the OUT pin; the drain of the sixth PMOS P6 is used to output the detection signal Vonsc of the first stage Von detection circuit.

5. The high side MOSFET switch chip with short circuit protection according to claim 4, characterized in that: The delay time generating circuit comprises a first current source I1, a first non-inverter inv1, a ninth PMOS P9, a sixth NMOS N6, a second capacitor C2, a seventh NMOS N7, a second non-inverter inv2, a third non-inverter inv3, a second current source I2, a fourth non-inverter inv4, a tenth PMOS P10, an eighth NMOS N8, a third capacitor C3, a fifth non-inverter inv5, a sixth non-inverter inv6, a first NAND gate nand1, a second NAND gate nand2, a seventh non-inverter inv7. One end of the first current source I1 is connected to the VBB pin, and the other end is connected to the source of the ninth PMOS tube P9; the input end of the first non-inverter inv1 is connected to the detection signal Vonsc output by the first Von detection circuit, and the output end is connected to the gate of the ninth PMOS tube P9 and the gate of the sixth NMOS tube N6; the drain of the ninth PMOS tube P9 and the drain of the sixth NMOS tube N6 are both connected to one end of the second capacitor C2, the drain of the seventh NMOS tube N7 and the input end of the second non-inverter inv2; the output end of the second non-inverter inv2 is connected to the input end of the third non-inverter inv3, and the output end of the third non-inverter inv3 is connected to one of the input ends of the first NAND gate nand1; the source of the sixth NMOS tube N6, the source of the seventh NMOS tube N7 and the other end of the second capacitor C2 are all connected to the high-side power supply voltage Vs; One end of the second current source I2 is connected to the VBB pin, and the other end is connected to the source of the tenth PMOS tube P10; the input end of the fourth non-inverter inv4 is connected to the enable signal EN, and the output end is connected to the gate of the tenth PMOS tube P10 and the gate of the eighth NMOS tube N8; the drain of the tenth PMOS tube P10 and the drain of the eighth NMOS tube N8 are both connected to one end of the third capacitor C3 and the input end of the fifth non-inverter inv5; the output end of the fifth non-inverter inv5 is connected to the input end of the sixth non-inverter inv6, and the output end of the sixth non-inverter inv6 is connected to the other input end of the first NAND gate nand1; the source of the eighth NMOS tube N8 and the other end of the third capacitor C3 are both connected to the high-side power supply voltage Vs; The output signal of the first NAND gate nand1 and the enable signal EN are sent into the two input ends of the second NAND gate nand2, and the output end of the second NAND gate nand2 is connected to the GATE drive end of the chip through the seventh non-inverter inv7; the gate of the seventh NMOS tube N7 is connected to the output end of the fourth non-inverter inv4; the output end of the third non-inverter inv3 is used to output the first delay time signal Tdelay1; the output end of the fifth non-inverter inv5 is used to output the second delay time signal Tdelay2; the output end of the second NAND gate nand2 is also connected to the input end of the second Von detection and clamping current limiting circuit.

6. The high-side MOSFET switch chip with short circuit protection according to claim 5, characterized in that: The second Von detection and clamping current limiting circuit comprises a third current source I3, a current mirror composed of an eleventh PMOS tube P11 and a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a fourteenth PMOS tube P14, a fifteenth PMOS tube P15, a sixteenth PMOS tube P16, a seventeenth PMOS tube P17, a ninth NMOS tube N9, a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12, a third resistor R3, a fourth resistor R4 and a fifth resistor R5. The input end of the third current source I3 is connected with a high-side power supply voltage Vs, the output end is connected with the drain and gate of an eleventh PMOS tube P11 and the gate of a twelfth PMOS tube P12; the source of the eleventh PMOS tube P11 and the source of the twelfth PMOS tube P12 are connected with a VBB pin; the drain of the twelfth PMOS tube P12 is connected with the source of a thirteenth PMOS tube P13 and the source of a fifteenth PMOS tube P15; the gate and drain of the thirteenth PMOS tube P13 are connected with the source of a fourteenth PMOS tube P14, the gate and drain of the fourteenth PMOS tube P14 and the drain of the fifteenth PMOS tube P15 are connected with the source of a sixteenth PMOS tube P16; the drain of the sixteenth PMOS tube P16 is connected with the drain and gate of a ninth NMOS tube N9, the gate of a tenth NMOS tube N10 and the gate of an eleventh NMOS tube N11; the drain of the tenth NMOS tube N10 is connected with the gate of a power MOS tube, the source of a seventeenth PMOS tube P17 and the drain of a twelfth NMOS tube N12 through a fourth resistor R4 and a third resistor R3 in sequence; the gate of the seventeenth PMOS tube P17 is connected with the connection point of the fourth resistor R4 and the third resistor R3, the drain is connected with the drain of the eleventh NMOS tube N11, one end of a fifth resistor R5 and the gate of the twelfth NMOS tube N12; the source of the ninth NMOS tube N9, the source of the tenth NMOS tube N10, the source of the eleventh NMOS tube N11, the other end of the fifth resistor and the source of the twelfth NMOS tube N12 are connected with an OUT pin; the gate of the fifteenth PMOS tube P15 is used for receiving a second delay time signal Tdelay2.

7. The high-side MOSFET switch chip with short circuit protection according to claim 6, characterized in that: The enable signal generating circuit comprises an enable opening unit, a first stage hysteresis unit, a shaping and second stage hysteresis unit and a delay unit; the enable opening unit comprises a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, an eighteenth PMOS tube P18 and a ninth resistor R9; the first stage hysteresis unit comprises a seventeenth NMOS tube N17; the shaping and second stage hysteresis unit comprises a nineteenth PMOS tube P19, a thirteenth NMOS tube N13, a fourteenth NMOS tube N14, a fifteenth NMOS tube N15, an eighth non-inverter inv8 and a ninth non-inverter inv9. The sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 are connected in series, one end of the sixth resistor R6, the source of the eighteenth PMOS P18 and the source of the nineteenth PMOS P19 are connected to the VBB pin; the drain of the eighteenth PMOS P18 is connected to one end of the ninth resistor R9, the gate of the nineteenth PMOS P19 and the gate of the thirteenth NMOS N13; the gate of the eighteenth PMOS P18 is connected to the connection point of the sixth resistor R6 and the seventh resistor R7; the connection point of the seventh resistor R7 and the eighth resistor R8 is connected to the drain of the seventeenth NMOS N17, the gate of the seventeenth NMOS N17 is connected to the output end of the eighth inverter inv8; the drain of the nineteenth PMOS P19 and the drain of the thirteenth NMOS N13 are both connected to the input end of the eighth inverter inv8; the source of the thirteenth NMOS N13 and the drain of the fifteenth NMOS N15 are both connected to the drain and the gate of the fourteenth NMOS N14; the gate of the fifteenth NMOS N15 and the output end of the eighth inverter inv8 are both connected to the input end of the ninth inverter inv9; the output end of the ninth inverter inv9 is connected to the input end of the delay unit; the delay unit is used for delaying the output enable signal EN; The source of the seventeenth NMOS N17, the other end of the eighth resistor R8, the other end of the ninth resistor R9, the source of the fourteenth NMOS N14 and the source of the fifteenth NMOS N15 are all connected to the high-side power supply voltage Vs.

8. The high-side MOSFET switch chip with short circuit protection according to claim 7, characterized in that: The delay unit comprises a fourth current source I4, a twentieth PMOS P20, a sixteenth NMOS N16, a fourth capacitor C4, a tenth inverter inv10 and an eleventh inverter inv11. The input end of the fourth current source I4 is connected to the VBB pin, and the output end is connected to the source of the twentieth PMOS P20; the gate of the twentieth PMOS P20 and the gate of the sixteenth NMOS N16 are both connected to the output end of the ninth inverter inv9; the drain of the twentieth PMOS P20 and the drain of the sixteenth NMOS N16 are connected to one end of the fourth capacitor C4, and the output enable signal EN is output after passing through the tenth inverter inv10 and the eleventh inverter inv11 in sequence; the source of the sixteenth NMOS N16 and the other end of the fourth capacitor C4 are both connected to the high-side power supply voltage Vs.

9. The high-side MOSFET switch chip with short circuit protection according to claim 8, characterized in that: The linear voltage stabilizer is a low dropout linear voltage stabilizer, comprising a first voltage stabilizing tube Dz1, a first field effect tube N1, a first PMOS tube P1 and a first capacitor C1; wherein: the negative electrode of the first voltage stabilizing tube Dz1 is connected with a VBB pin and one end of the first capacitor C1, the other end of the first capacitor C1 is connected with the source electrode of the first PMOS tube P1, the gate electrode of the first PMOS tube P1 is connected with the positive electrode of the first voltage stabilizing tube Dz1 and the drain electrode of the first field effect tube N1, the gate electrode and the source electrode of the first field effect tube N1 are both connected with an IN pin and the drain electrode of the first PMOS tube P1; the source electrode of the first PMOS tube P1 is used for outputting a high-side power supply voltage Vs; The first field effect tube N1, the second field effect tube N2 and the third field effect tube N3 are high-voltage depletion-mode or JEFT field effect tubes; The first PMOS tube P1, the second PMOS tube P2 and the third PMOS tube P3 are high-voltage PMOS tubes; The fourth PMOS tube P4, the fifth PMOS tube P5, the sixth PMOS tube P6, the seventh PMOS tube P7 and the eighth PMOS tube P8 are low-voltage PMOS tubes; The sixteenth PMOS tube P16 is a high-voltage PMOS tube; The reference resistor R1 and the detection resistor R2 are resistors of the same type, consistent width-length ratio and high matching.

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