Three-dimensional AND flash memory device and manufacturing method thereof

Abstract

The present disclosure provides a three-dimensional AND flash memory (3D AND Flash) element, comprising: a gate stack structure disposed on a dielectric substrate and comprising a plurality of gate layers and a plurality of insulating layers alternately stacked with each other; a channel pillar penetrating through the gate stack structure; a first conductor pillar and a second conductor pillar disposed in the channel pillar and penetrating through the gate stack structure, wherein the first conductor pillar and the second conductor pillar are separated from each other and each connected with the channel pillar; a charge storage structure disposed between the plurality of gate layers and sidewalls of the channel pillar; and a protective cap covering at least a top surface of the channel pillar, isolating the first conductor pillar from a top gate layer of the plurality of gate layers, and isolating the second conductor pillar from the top gate layer of the plurality of gate layers.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory device and a manufacturing method thereof, and more particularly to a three-dimensional AND flash memory device and a manufacturing method thereof. Background Art

[0002] Non-volatile memory (eg, flash memory) has become a widely used memory in personal computers and other electronic devices because it has the advantage that stored data will not disappear after power is turned off.

[0003] Currently, the most commonly used three-dimensional flash memories include NOR flash memory and NAND flash memory. Another type of three-dimensional flash memory is 3D AND flash memory, which can be used in multi-dimensional flash memory arrays and offers high integration, high area utilization, and fast operation speeds. Therefore, the development of three-dimensional flash memory has gradually become a trend.

[0004] Public content

[0005] An embodiment of the present invention provides a three-dimensional AND flash memory element and a manufacturing method thereof, which can avoid short circuit or leakage current between a conductive column and a topmost word line layer.

[0006] According to an embodiment of the present invention, a three-dimensional AND flash memory device includes: a gate stack structure disposed on a dielectric substrate and comprising multiple gate layers and multiple insulating layers alternately stacked; a channel pillar disposed on the dielectric substrate and extending through the gate stack structure; a first conductive pillar and a second conductive pillar disposed within the channel pillar and extending through the gate stack structure, wherein the first conductive pillar and the second conductive pillar are separated from each other and each is connected to the channel pillar; a charge storage structure disposed between the multiple gate layers and sidewalls of the channel pillar; and a protective cap covering the channel pillar, isolating the first conductive pillar from a top gate layer of the multiple gate layers, and isolating the second conductive pillar from the top gate layer of the multiple gate layers.

[0007] According to an embodiment of the present invention, a method for manufacturing a three-dimensional AND flash memory device includes: forming a stacked structure on a dielectric substrate, the stacked structure including multiple sacrificial layers and multiple insulating layers alternately stacked; forming an opening in the stacked structure; forming a channel column in the opening; forming a protective cap on the channel column; forming an insulating filling layer on the stacked structure and the protective cap and filling the opening; protecting the channel column with the protective cap and patterning the insulating filling layer to form a first hole and a second hole in the channel column; forming a first conductive column and a second conductive column connected to the channel column in the first hole and the second hole, respectively; performing a replacement process to replace the multiple sacrificial layers with multiple gate layers; and forming a charge storage structure between the multiple gate layers and the sidewalls of the channel column.

[0008] In the embodiment of the present invention, covering the channel pillar with a protective cover can prevent the channel pillar from being damaged during a subsequent etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A A circuit diagram of a 3D AND flash memory array according to an embodiment is shown.

[0010] Figure 1B A circuit diagram of a 3D AND flash memory array according to another embodiment is shown.

[0011] Figure 1B A simplified perspective diagram illustrating a 3D AND flash memory array in accordance with some embodiments is shown.

[0012] Figure 1C and 1D A cross-sectional view of a 3D AND flash memory array is shown in accordance with some embodiments.

[0013] Figure 1E A top view of a 3D AND flash memory cell is shown.

[0014] Figures 2A to 2I 1 is a cross-sectional schematic diagram and a top view of a manufacturing process of a 3D AND flash memory device according to an embodiment of the present invention.

[0015] Figures 3A to 3I 1 is a cross-sectional schematic diagram and a top view illustrating a manufacturing process of a 3D AND flash memory device according to another embodiment of the present invention.

[0016] Description of Reference Numerals

[0017] 10: Storage Array

[0018] 12: Storage unit

[0019] 16, 116: Channel column

[0020] 24b, 124, 124: Insulation filling layer

[0021] 28, 128: Insulation column

[0022] 32a, 32b: Drain column

[0023] 38, 138: Gate layer

[0024] 40, 140: Charge storage structure

[0025] 50, 100: dielectric substrate

[0026] 102, 102': stacked structure

[0027] 54, 104: Insulation layer

[0028] 60: Arrow

[0029] 106: Sacrificial layer

[0030] 108: Opening

[0031] 110: Oxide layer

[0032] 112: Storage layer

[0033] 112': Storage layer material

[0034] 114: Tunneling material layer

[0035] 114': Tunneling material layer

[0036] 116': Channel material layer

[0037] 118: Gap wall

[0038] 118': Spacer material layer

[0039] 120: Groove

[0040] 122: Protective cover

[0041] 122S1: inner wall

[0042] 122S2: Outer wall

[0043] 122': Protective material layer

[0044] 126, 130a, 130b: holes

[0045] 132L: lower part

[0046] 132M: Central

[0047] 132U: Upper

[0048] 132a, 132b: Conductor columns

[0049] 134: Horizontal opening

[0050] 136: Barrier layer

[0051] 137: Barrier layer

[0052] 52, 150: Gate stack structure

[0053] A (i) j 、A (i+1) j : Storage Array

[0054] BLOCK (i) 、BLOCK (i+1) : Block

[0055] WL (i) (j，m) 、WL (i) (j，m+1) 、WL (i+1) (j，m) 、WL (i+1) (j，m+1) :Word line

[0056] SL n , SL n+1 : Source line

[0057] BL n BL n+1 : Bit line

[0058] SP (i) (j，n) 、SP (i) (j，n+1) 、SP (i+1) (j，n) 、SP (i+1) (j，n+1) :First conductor column

[0059] DP (i) (j，n) , DP (i) (j，n+1) , DP (i+1) (j，n) , DP (i+1) (j，n+1) :Second conductor column

[0060] I-I', II-II': Tangent line DETAILED DESCRIPTION

[0061] Figure 1A A circuit diagram illustrating a 3D AND flash memory array according to some embodiments is shown. Figure 1B Show Figure 1A FIG. 1 is a partial three-dimensional view of a simplified portion of the memory array 10 . Figure 1C and Figure 1D Show Figure 1B Cross-sectional view of the tangent line I-I'. Figure 1E Show Figure 1B 、 Figure 1C and Figure 1D Top view of the tangent line II-II'.

[0062] Figure 1A The vertical AND memory array 10 includes two blocks arranged in rows and columns. (i) With BLOCK (i+1) Schematic diagram of the block. (i) Including storage array A (i) Storage Array A (i) A row (for example, the m+1th row) has a common word line (for example, WL (i) m+1 ) of AND storage cells 20. Storage array A (i) Each column (eg, the m+1th column) of AND memory cells 20 corresponds to a common word line (eg, WL (i) m+1 ) and coupled to different source columns (eg SP (i) n With SP (i) n+1 ) and the drain column (eg DP (i) n With DP (i) n+1 ), so that the AND memory cell 20 is along a common word line (eg WL (i) m+1 ) are logically arranged into a column.

[0063] Storage array A (i) A row (eg, the nth row) has a common source column (eg, SP (i) n ) and a common drain column (such as DP (i) n ) of AND storage cells 20. Storage array A (i) Each row (eg, the nth row) of AND storage cells 20 corresponds to a different word line (eg, WL (i) m+1 With WL (i) m ) and coupled to a common source column (eg SP (i) n ) with a common drain column (e.g. DP (i)n ). Therefore, storage array A (i) AND memory cell 20 along a common source column (eg SP (i) n ) and a common drain column (such as DP (i) n ) are logically arranged in a row. In the physical layout, depending on the fabrication method used, the rows or columns may be twisted, arranged in a honeycomb pattern or otherwise for high density or other reasons.

[0064] exist Figure 1A In the block BLOCK (i) In the storage array A (i) The AND memory cells 20 in the nth row share a common source column (eg SP (i) n ) with a common drain column (e.g. DP (i) n ). The AND storage cells 20 in the n+1th row share a common source column (eg SP (i) n+1 ) with a common drain column (e.g. DP (i) n+1 ). Source column (eg SP (i) n ) is coupled to a common source line (eg, SL n ); a common drain column (eg DP (i) n ) is coupled to a common bit line (eg, BL n ). Source column (eg SP (i) n+1 ) is coupled to a common source line (eg, SL n+1 ); a common drain column (eg DP (i) n+1 ) is coupled to a common bit line (eg, BL n+ 1).

[0065] Similarly, BLOCK (i+1) Including storage array A (i+1) , which is the same as in the block BLOCK (i) Storage array A in (i) Storage array A (i+1) A row (for example, the m+1th row) has a common word line (for example, WL (i+1) m+1 ) of AND storage cells 20. Storage array A (i+1) Each column (eg, the m+1th column) of AND memory cells 20 corresponds to a common word line (eg, WL (i+1) m+1) and coupled to different source columns (eg SP (i+1) n With SP (i+1) n+1 ) and the drain column (eg DP (i+1) n With DP (i +1) n+1 Storage array A (i+1) A row (eg, the nth row) has a common source column (eg, SP (i+1) n ) and a common drain column (such as DP (i+1) n ) of AND storage cells 20. Storage array A (i+1) Each row (eg, the nth row) of AND storage cells 20 corresponds to a different word line (eg, WL (i+1) m+1 With WL (i+1) m ) and coupled to a common source column (eg SP (i+1) n ) with a common drain column (e.g. DP (i+1) n ). Therefore, storage array A (i+1) AND memory cell 20 along a common source column (eg SP (i +1) n ) and a common drain column (such as DP (i+1) n ) are logically configured into one row.

[0066] BLOCK (i+1) With BLOCK (i) Common source line (eg SL n With SL n+1 ) and bit lines (such as BL n With BL n+1 ). Therefore, the source line SL n and bit line BL n Coupled to block BLOCK (i) AND storage array A (i) The nth row of AND memory cells 20 is coupled to the block BLOCK (i+1) AND storage array A in (i+1) Similarly, the source line SL n+1 and bit line BL n+1 Coupled to block BLOCK (i) AND storage array A (i)The AND memory cell 20 in the n+1th row is coupled to the block BLOCK (i+1) AND storage array A in (i+1) The AND storage unit 20 in the n+1th row.

[0067] Reference Figure 1B The memory array 10 may be disposed in the back end of line (BEOL) of a semiconductor die. For example, the memory array 10 may be disposed in an interconnect structure of the semiconductor die, such as above one or more active devices (e.g., transistors) formed on a semiconductor substrate.

[0068] Reference Figure 1B The memory array 10 includes a gate stack structure 52. The gate stack structure 52 includes a plurality of gate layers (also called word lines) 38 and a plurality of insulating layers 54 vertically stacked on the surface of a dielectric substrate 50. These gate layers 38 are electrically isolated by the insulating layers 54 disposed therebetween. The gate layers 38 are electrically isolated from the dielectric substrate 50 (shown in FIG. 1 ). Figure 1C ) extends in a direction parallel to the surface of the substrate. Gate layer 38 may have a stepped structure (not shown) such that the lower gate layer 38 is longer than the upper gate layer 38, and the end of the lower gate layer 38 extends laterally beyond the end of the upper gate layer 38. Contact windows for connecting gate layers 38 may land at the ends of gate layers 38, thereby connecting each gate layer 38 to each conductive line.

[0069] Reference Figures 1B to 1D The memory array 10 further includes a plurality of channel pillars 16. The channel pillars 16 continuously extend through the gate stack structure 52. In some embodiments, the channel pillars 16 may have a ring-shaped profile when viewed from above.

[0070] Reference Figures 1B to 1D The memory array 10 further includes a plurality of first conductive pillars 32a and a plurality of second conductive pillars 32b. In this example, the first conductive pillars 32a serve as source pillars, and the second conductive pillars 32b serve as drain pillars. The first and second conductive pillars 32a and 32b, as well as the insulating pillar 28, are disposed within the channel pillar 16 and extend perpendicularly to the gate layer 38. The first and second conductive pillars 32a and 32b are separated by the insulating pillar 28 and electrically coupled to the channel pillar 16.

[0071] Reference Figure 1D, the charge storage structure 40 is disposed between the channel pillar 16 and the multi-layer gate layer 38. The charge storage structure 40 may include a tunneling layer (or called a bandgap engineered tunneling oxide layer) 14, a charge storage layer 12, and a blocking layer 36. The charge storage layer 12 is located between the tunneling layer 14 and the blocking layer 36. In some embodiments, the tunneling layer 14, the charge storage layer 12, and the blocking layer 36 are, for example, silicon oxide, silicon nitride, and silicon oxide. In some embodiments, a portion of the charge storage structure 40 (the tunneling layer 14 and the charge storage layer 12) extends continuously in a direction perpendicular to the gate layer 38, while another portion of the charge storage structure 40 (the blocking layer 36) surrounds the gate layer 38, as shown in FIG. Figure 1C In other embodiments, the charge storage structure 40 (tunneling layer 14, charge storage layer 12 and blocking layer 36) surrounds the gate layer 38, as shown in FIG. Figure 1D As shown. Figure 1E The gate layer 38 and the charge storage structure 40, the channel pillar 16, the first conductive pillar 32a and the second conductive pillar 32b define the memory cell 20. When operating, a voltage is applied to the selected word line (gate layer) 38, for example, a voltage higher than the corresponding starting voltage (V th ), the channel region of the channel column 16 intersecting the selected word line 38 is turned on, allowing current to flow from the bit line BL n or BL n+1 (Shown in Figure 1B ) enters the second conductor post 32b and flows through the conductive channel region to the first conductor post 32a (eg, in the direction indicated by arrow 60), and finally flows to the source line SL n or SL n+1 (Shown in Figure 1B ).

[0072] Reference Figures 1D to 1E The first conductive pillar 32a and the second conductive pillar 32b are formed by etching holes in the insulating filler layer 24b and then backfilling the holes with a conductive layer. However, during the etching process to form the holes, the top surface of the channel pillar 16 may be damaged. If the height of the top surface of the channel pillar 16 is not controlled properly, a short circuit may occur between the top of the channel pillar 16 and the topmost gate layer 38, or leakage current may result.

[0073] Reference Figure 1C and Figure 1DThe present invention forms a protective cap 22 on the channel pillar 16 to prevent the channel pillar 16 from being damaged by etching. Therefore, the top surface of the channel pillar 16 can be controlled to be flush or substantially flush with the top surface of the charge storage structure 40 on the top surface of the top gate layer 38, so that the device has good reliability. In addition, the protective cap 22 on the channel pillar 16 can prevent short circuits and leakage currents between the top corners of the conductor pillar 32a or 32b and the top gate layer 38. Figures 2A to 2I Please explain in detail.

[0074] Figures 2A to 2I 1 is a cross-sectional schematic diagram and a top view of a manufacturing process of a 3D AND flash memory device according to an embodiment of the present invention.

[0075] Reference Figure 2A , a stacked structure 102' is formed on the dielectric substrate 100. The dielectric substrate 100 is, for example, a dielectric layer of a metal interconnect structure formed on a silicon substrate, such as a silicon oxide layer. The stacked structure 102' may also be referred to as an insulating stacked structure 102'. In the present embodiment, the stacked structure 102' may be composed of a sacrificial layer 106 and an insulating layer 104 stacked in sequence and alternately on the dielectric substrate 100. In addition, in the present embodiment, the top layer of the stacked structure 102' is the insulating layer 104. In other embodiments, the sacrificial layer 106 or the insulating layer 104 may be used as the bottom layer. The insulating layer 104 is, for example, a silicon oxide layer. The sacrificial layer 106 is, for example, a silicon nitride layer. In the present embodiment, the stacked structure 102' has two layers of insulating layers 104 and two layers of sacrificial layers 106, but the present invention is not limited thereto. In other embodiments, more layers of insulating layers 104 and more layers of sacrificial layers 106 may be formed depending on actual needs.

[0076] A plurality of openings 108 are formed in the stacked structure 102'. However, for simplicity, only the openings 108 are shown in the figure. In the present embodiment, the bottom surface of the opening 108 exposes the dielectric substrate 100, but the present invention is not limited thereto. In other embodiments, when the bottommost layer of the stacked structure 102' is the insulating layer 104, the bottom of the opening 108 may be located in the bottommost insulating layer 104, that is, the bottom surface of the opening 108 exposes the bottommost insulating layer 104 without exposing the dielectric substrate 100. Alternatively, in other embodiments, the bottom of the opening 108 further extends into the dielectric substrate 100. In the present embodiment, the opening 108 has a circular outline when viewed from above, but the present invention is not limited thereto. In other embodiments, the opening 108 may have an outline of other shapes, such as a polygon (not shown).

[0077] Reference Figure 2BA thermal oxidation process is performed to oxidize the sidewalls of the sacrificial layer 106 exposed by the opening 108 to form an oxide layer 110. Next, a storage material layer 112', a tunneling material layer 114', and a channel material layer 116' are formed on the stacked structure 102' and within the opening 108. The storage material layer 112' can be, for example, a silicon oxide layer. The tunneling material layer 114' can be, for example, a silicon nitride layer. The channel material layer 116' can be made of a semiconductor material, such as undoped polysilicon.

[0078] In an embodiment of the present invention, after forming the channel material layer 116', a spacer material layer 118' is further formed on the channel material layer 116'. The material of the spacer material layer 118' is different from that of the channel material layer 116' and has a different etching rate. The material of the spacer material layer 118' is, for example, silicon oxide.

[0079] Reference Figure 2C , an etch-back process is performed to partially remove the storage material layer 112', the tunneling material layer 114', the channel material layer 116', and the spacer material layer 118', thereby forming the storage layer 112, the tunneling layer 114, the channel pillar 116, and the spacer 118. The storage layer 112, the tunneling layer 114, and the channel pillar 116 cover the sidewalls of the opening 108, exposing the bottom of the opening 108. The storage layer 112, the tunneling layer 114, and the channel pillar 116 may extend through the stacked structure 102' and into the dielectric substrate 100. The channel pillar 116 may be annular in a top view, for example. In a cross-sectional view, it may be continuous in its extension direction (e.g., in a direction perpendicular to the dielectric substrate 100). In other words, the channel pillar 116 is integral in its extension direction and is not divided into multiple disconnected portions. In some embodiments, the channel pillar 116 may have a circular profile when viewed from above, but the present invention is not limited thereto. In other embodiments, the channel column 116 may also have a profile of other shapes (e.g., polygonal) when viewed from above. Furthermore, when performing this etch-back process, the top surface of the channel column 116 can be controlled to be at a suitable height. For example, the top surface of the channel column 116 can be controlled to be coplanar or approximately coplanar with the top surface of the charge storage structure 140 on the top surface of the subsequently formed topmost gate layer 138. Since the etching rate of the storage material layer 112', the tunneling material layer 114', and the channel material layer 116' is higher than the etching rate of the spacer material layer 118', a groove 120 is formed between the stacked structure 102' and the spacer 118. The bottom of the groove 120 exposes the top surface of the channel column 116.

[0080] Reference Figure 2DA protective material layer 122' is formed on the stack structure 102', in the recess 120, and in the opening 108. The material of the protective material layer 122' is different from the material of the spacer 118, and is different from the material of the via pillar 116. The material of the protective material layer 122' can be nitride, such as silicon nitride.

[0081] Referring to Figure 2E An etch-back process is performed to partially remove the protective material layer 122' to form a protective cap 122 in the recess 120. The protective cap 122 covers less of the top surface of the via pillar 116. In this embodiment, the protective cap 122 covers the memory layer 112, the tunneling layer 114, and the via pillar 116. In some embodiments, the protective cap 122 is annular. The top surface of the protective cap 122 is lower than the top surface of the stack structure 102'.

[0082] Referring to Figure 2F and 2G An etch process, such as a wet etch process, is performed to remove the spacer 118. Then, an insulating fill layer 124 is formed over the upper surface of the stack structure 102' and the dielectric base 100. The insulating fill layer 124 covers over the stack structure 102' and the protective cap 122, and fills in the opening 108. Since the insulating fill layer 124 is over the stack structure 102', it can also be referred to as an insulating cap layer. The material of the insulating fill layer 124 is different from the material of the protective cap 122. The material of the insulating fill layer 124 is, for example, silicon oxide. When the insulating fill layer 124 fills in the opening 108, the opening 108 is not completely filled and leaves a hole in the center region. Then, an insulating material, such as silicon nitride, different from the insulating fill layer 124 is filled in the opening 108 to completely seal the opening 108. The insulating material in the center region of the opening 108 is etched back to the surface of the insulating fill layer 124 via a dry etch or a wet etch process, and forms an insulating pillar 128.

[0083] Referring to Figure 2H, a patterning process is performed to form holes 130a and 130b in the insulating filling layer 124. The holes 130a and 130b extend from the top surface of the insulating filling layer 124 to the dielectric substrate 100. The outlines of the holes 130a and 130b defined by the patterning process exceed the outlines of the insulating pillars 128. Since the etching rate of the insulating pillars 128 is lower than the etching rate of the insulating filling layer 124, the insulating pillars 128 are hardly damaged by the etching and remain. In addition, the outlines of the holes 130a and 130b defined by the patterning process exceed the outline of the opening 108, so that the holes 130a and 130b expose the protective cover 122 and a portion of the top insulating layer 104 of the stacked structure 102. During the patterning process, the protective cap 122 can serve as a hard mask layer to protect the underlying storage layer 112, tunneling layer 114, and channel pillar 116 from etching damage. Therefore, the upper and lower portions of the formed holes 130a and 130b have different radial dimensions. The radial dimension of the upper portions of the holes 130a and 130b is greater than the radial dimension of the lower portions of the holes 130a and 130b.

[0084] Reference Figure 2H as well as Figure 2I , conductive pillars 132a and 132b are formed in the holes 130a and 130b. The conductive pillars 132a and 132b can serve as a source pillar and a drain pillar, respectively, and are electrically connected to the channel pillar 116. The conductive pillars 132a and 132b can each include an upper portion 132U, a middle portion 132M, and a lower portion 132L. The radial dimension of the upper portion 132U is larger than the radial dimensions of the middle portion 132M and the lower portion 132L. The sidewalls of the upper portion 132U are covered by the insulating filling layer 124, a portion of the top insulating layer 104, and the insulating pillars 128. The bottom of the upper portion 132U is lower than the top surface of the protective cover 122. The upper portion 132U covers the top surface of the protective cover 122, and covers a portion of the inner sidewall 122S1 and a portion of the outer sidewall 122S2 of the protective cover 122. The sidewalls of the middle portion 132M are protected by the protective cover 122, the insulating filling layer 124 (shown in FIG. Figure 2I The sidewalls of the lower portion 132L are covered by the channel pillars 116, the insulating fill layer 124 (shown in FIG. Figure 2I ) and covered by insulating pillars 128.

[0085] The top surface of the protective cap 122 is lower than the top surface of the gate stack structure 150. The top surface of the protective cap 122 is covered by the upper portions 132U of the conductor pillars 132a and 132b. The top surface of the protective cap 122 is also covered by the insulating filling layer 124 filled in the channel pillar 116. The protective cap 122 is laterally sandwiched between the conductor pillar 132a and the insulating layer 124, and laterally sandwiched between the conductor pillar 132b and the insulating layer 124. The protective cap 122 is laterally sandwiched between the conductor pillar 132b and the insulating layer 124, and laterally sandwiched between the conductor pillar 132b and the insulating layer 124. The inner sidewall 122S1 of the protective cap 122 is covered by and in contact with the middle portions 132M of the conductor pillars 132a and 132b and the insulating filling layer 124. The outer sidewall 122S2 of the protection cap 122 is covered by the upper portions 132U of the conductive pillars 132a and 132b and the (top) insulating layer 104 of the gate stack structure 150. The bottom surface of the protection cap 122 covers and lands on the tunneling layer 114 and the storage layer 112 of the channel pillar 116 and the charge storage structure 140.

[0086] Afterwards, refer to Figure 2I A replacement process is performed. In some embodiments, the replacement process replaces the multi-layer sacrificial layer 106 with a multi-layer gate layer 138. First, a patterning process is performed on the stacked structure 102 to form a plurality of separation channels (not shown) therein, so that the stacked structure 102 is divided into a plurality of blocks. Next, an etching process, such as a wet etching process, is performed to inject an etching solution into the separation channels to remove the multi-layer sacrificial layer 106 in sequence to form a plurality of horizontal openings 134. Thereafter, a gate material layer is formed in sequence in the plurality of separation channels and the plurality of horizontal openings 134. Thereafter, a back etching process is performed to remove the gate material layer in the plurality of separation channels to form a multi-layer gate layer 138 in the plurality of horizontal openings 134. In addition, in other embodiments, before forming the multi-layer gate layer 138, the oxide layer 110 (shown in FIG. 1 ) is also formed. Figure 2H) is removed, and a blocking material layer and a barrier material layer are sequentially formed in the separation channel and the horizontal opening 134. The material of the blocking material layer is, for example, a high dielectric constant material with a dielectric constant greater than 7, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxides, lanthanide oxides, or a combination thereof. The material of the barrier material layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. After the blocking material layer and the barrier material layer are etched back, a multi-layer blocking layer 136 and a multi-layer barrier layer 137 are formed in the multiple horizontal openings 134. The barrier layer 137 is located between the blocking layer 136 and the gate layer 138. The multi-layer blocking layer 136, the storage layer 112, and the tunneling layer 114 are collectively referred to as the charge storage structure 140. At this point, the gate stack structure 150 is formed. The gate stack structure 150 is disposed on the dielectric substrate 100 and includes multiple gate layers 138 and multiple insulation layers 104 alternately stacked.

[0087] In the above embodiment, the storage material layer 112' and the tunneling material layer 114' are formed immediately after the opening 108 is formed (as shown in FIG. Figure 2B However, the embodiment of the present invention is not limited thereto. In other embodiments, the tunneling material layer and the storage material layer may also be formed during subsequent processes, such as Figures 3A to 3I shown.

[0088] In the following embodiments, the gate stack structure is formed by other embodiments. Figures 3A to 3B After the opening 108 is formed, a channel material layer 116' and a spacer material layer 118' are formed. Then, a method similar to the above embodiment is used (eg, Figures 2C to 2F As shown), forming the protective cover 122 ( Figures 3C to 3F In addition, an insulating filling layer 124, an insulating column 128, and conductive columns 132a and 132b are formed (as shown in FIG. Figures 3G to 3I shown). Figures 3G to 3I The process is similar to the above embodiment (such as Figures 2G to 2I shown)

[0089] Reference Figure 3H and 3I , a replacement process is performed, which is different from FIG. Figures 2H to 2IThe replacement process is shown. In this embodiment, the replacement process replaces the multi-layer sacrificial layer 106 with a storage layer 112, a tunneling layer 114, and a multi-layer gate layer 138. After forming the separation channel according to the method of the above embodiment, the sacrificial layer 106 and the oxide layer 110 are removed and a horizontal opening 134 is formed. Thereafter, a tunneling material layer, a storage material layer, a blocking material layer, and a barrier material layer are sequentially formed in the separation channel and the horizontal opening 134, and then a gate material layer is formed in the separation channel and the horizontal opening 134. Thereafter, an etch-back process is performed to remove the multi-layers in the plurality of separation channels. The multi-layers include a tunneling material layer, a storage material layer, a blocking material layer, a barrier material layer, and a gate material layer. A tunneling layer 114, a storage layer 112, a blocking layer 136, and a barrier layer 137 are formed on the inner surface of each horizontal opening 134. The gate layer 138 is filled in the remaining space of the horizontal opening 134. At this point, a gate stack structure 150 is formed. The blocking layer 136, the storage layer 112, and the tunneling layer 114 are collectively referred to as a charge storage structure 140. The gate stack structure 150 is disposed on the dielectric substrate 100 and includes a plurality of gate layers 138 and a plurality of insulating layers 104 alternately stacked.

[0090] In this embodiment, the top surface of the protective cap 122 is lower than the top surface of the gate stack structure 150. The top surface of the protective cap 122 is covered by the upper portions 132U of the conductor pillars 132a and 132b. The top surface of the protective cap 122 is also covered by the insulating filling layer 124 filled in the channel pillar 116. The protective cap 122 is laterally sandwiched between the conductor pillar 132a and the insulating layer 124, and laterally sandwiched between the conductor pillar 132b and the insulating layer 124. The protective cap 122 is laterally sandwiched between the conductor pillar 132b and the insulating layer 124, and laterally sandwiched between the conductor pillar 132b and the insulating layer 124. The inner sidewall 122S1 of the protective cap 122 is covered by and in contact with the middle portions 132M of the conductor pillars 132a and 132b and the insulating filling layer 124. The outer sidewall 122S2 of the protection cap 122 is covered by the upper portions 132U of the conductive pillars 132a and 132b and the (top) insulating layer 104 of the gate stack 150. The bottom surface of the protection cap 122 covers and lands on the channel pillar 116 and contacts the tunneling layer 114 of the charge storage structure 140.

[0091] In summary, the present invention can protect the channel column by forming a protective cover to prevent the channel column from being damaged by etching. Therefore, the top surface of the channel column can be controlled to be flush or approximately flush with the top surface of the charge storage structure on the top surface of the topmost gate layer, so that the component has good reliability.

Claims

1. A three-dimensional AND flash memory device, characterized in that: include: A gate stack structure is provided on a dielectric substrate and includes multiple gate layers and multiple insulating layers alternately stacked on each other; A channel column is disposed on the dielectric substrate and passes through the gate stack structure; A first conductive post and a second conductive post are disposed in the channel post and penetrate the gate stack structure, wherein the first conductive post and the second conductive post are separated from each other and are respectively connected to the channel post; a charge storage structure disposed between the multi-layer gate layer and the sidewall of the channel pillar; as well as A protective cover at least covers the top surface of the channel column, isolates the first conductive column from the top gate layer of the multi-layer gate layer, and isolates the second conductive column from the top gate layer of the multi-layer gate layer.

2. The three-dimensional AND flash memory device according to claim 1, wherein: The tunneling layer and the storage layer of the charge storage structure surround the outer sidewall of the channel column, and the top surface thereof is covered by the protection cover.

3. The three-dimensional AND flash memory device according to claim 1, wherein: The charge storage structure surrounds the multi-layer gate layer.

4. The three-dimensional AND flash memory device according to claim 1, wherein: The protective cover is sandwiched between the first conductor post and the first insulating layer of the multi-layer insulating layer in a lateral direction, and is sandwiched between the second conductor post and the first insulating layer in a lateral direction.

5. The three-dimensional AND flash memory device according to claim 1, wherein: A top surface of the protection cover is lower than a top surface of the gate stack structure.

6. The three-dimensional AND flash memory device according to claim 5, wherein: The top surface of the protection cover is covered by the first conductive post and the second conductive post.

7. The three-dimensional AND flash memory device according to claim 5, wherein: The top surface of the protection cover is also covered by an insulating filling layer filled in the channel column.

8. A method for manufacturing a three-dimensional AND flash memory device, characterized in that: include: forming a stacked structure on a dielectric substrate, wherein the stacked structure includes multiple sacrificial layers and multiple insulating layers alternately stacked on each other; forming an opening in the stacked structure; forming a channel pillar in the opening; forming a protective cover on the channel pillar; forming an insulating filling layer on the stacked structure and the protective cover, and filling the insulating filling layer into the opening; Covering the channel pillar with the protective cover for protection, and patterning the insulating filling layer to form a first hole and a second hole in the channel pillar; forming a first conductive post and a second conductive post connected to the channel post in the first hole and the second hole respectively; performing a replacement process to replace the multi-layer sacrificial layer with a multi-layer gate layer; and A charge storage structure is formed between the multi-layer gate layer and the sidewall of the channel column.

9. The method for manufacturing a three-dimensional AND flash memory device according to claim 8, wherein: The method for forming the channel pillar and the protective cover includes: forming a channel material layer on the stacked structure and in the opening; forming a spacer material layer on the channel material layer; Performing a first etch-back process to partially remove the channel material layer and the spacer material layer to form the channel pillars and the spacers, and forming a groove between the stacked structure and the spacers; forming a protective material layer on the stacked structure, in the groove, and in the opening; performing a second etch-back process to partially remove the protective material layer to form the protective cap in the groove, wherein the protective cap covers the channel pillar; and The spacers are removed.

10. The method for manufacturing a three-dimensional AND flash memory device according to claim 9, wherein: Before forming the channel material layer, a tunneling material layer and a storage material layer are further formed in the opening, and the tunneling material layer and the storage material layer are further removed during the first etch-back process to form the tunneling layer and the storage layer of the charge storage structure and the recess; and The protection cover formed in the groove also covers the tunneling layer and the storage layer.

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