A scan test method

Abstract

The application provides a scan test method, comprising: constructing a single stuck-at fault scan forest, the scan forest comprising a plurality of scan inputs and a plurality of scan trees, each scan input being driven by an ATE; each pin of the ATE driving a plurality of demodulators, each demodulator driving a plurality of scan trees, each scan tree corresponding to each demodulator being controlled by different clock signals of a gate logic, each scan tree comprising a plurality of scan chains, and each scan chain comprising a plurality of scan flip-flops; and based on the constructed single stuck-at fault scan forest, placing a test. The method can effectively reduce the calculation time and memory overhead.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit testing, and in particular to a scan test method. BACKGROUND

[0002] Scan forest as an efficient scan structure can effectively compress test data capacity, but the construction time and storage overhead must be strictly controlled when processing digital VLSI (Very Large Scale Integration) industry design.

[0003] In the circuit structure, the input signal line of a combinational gate is the combinational predecessor of the output signal line of the combinational gate, and vice versa, the output signal line of the combinational gate is the combinational successor of the input signal line of the combinational gate. The relationship between the combinational predecessor and the combinational successor can be iterated. The adjacent combinational predecessor is called a direct combinational predecessor, and the adjacent combinational successor is called a direct combinational successor.

[0004] In the past, two two-dimensional arrays were used to record the predecessor relationship and the successor relationship of the scan flip-flop. For two scan flip-flops i and j, pred[i][j] = 1 indicates that there is the same combinational predecessor in the combinational logic circuit of the same frame; for two scan flip-flops i and j, conv[i][j] = 1 indicates that there is the same successor in the combinational logic circuit of the same frame.

[0005] In order to construct the above two two-dimensional arrays, for each scan flip-flop i, IN[i] represents the set of PPI (pseudo-primary inputs) and PI (primary inputs) that can reach i; OUT[i] represents the set of PPO (pseudo-primary outputs) and PO (primary outputs) that can be reached by the scan flip-flop i.

[0006] Any two scan flip-flops i and j, if IN[i]∩IN[j]≠Ф, then pred[i][j] = 1; otherwise pred[i][j] = 0, there is no same combinational predecessor. Any two scan flip-flops i and j, if OUT[i]∩OUT[j]≠Ф, then conv[i][j] = 1; otherwise conv[i][j] = 0, there is no same combinational successor.

[0007] To realize the above idea, two two-dimensional arrays need to be defined to calculate the predecessor and successor associated conditions. For a design containing 1 million flip-flops, a memory of more than 1000G bits is consumed for one array. If a parallel algorithm is used to construct the two two-dimensional arrays, it is difficult to realize. Thus, the previous strategy for constructing the scan forest is difficult to deal with the actual industrial design. The construction of the scan forest also consumes a lot of time. SUMMARY

[0008] In order to reduce the calculation time and memory consumption, an embodiment of the present application provides a scan test method.

[0009] The scan test method provided by the embodiment of the present application comprises:

[0010] Constructing a single stuck-at fault scan forest, the scan forest comprising a plurality of scan inputs and a plurality of scan trees, each scan input being driven by an ATE; each pin of the ATE drives a demultiplexer, each demultiplexer drives a plurality of scan trees, each scan tree corresponding to each demultiplexer being controlled by different clock signals of a gate logic, each scan tree comprising a plurality of scan chains, and each scan chain comprising a plurality of scan flip-flops.

[0011] Based on the constructed single stuck-at fault scan forest, testing is performed.

[0012] In an embodiment, before the testing based on the constructed single stuck-at fault scan forest, the method further comprises:

[0013] Constructing a test response compressor, comprising at least one test response compression sub-network constructed for a subset of scan trees controlled by the same clock signal, each test response compression sub-network being constructed based on an XOR gate, and the number of outputs of the test response compressor being the maximum number of outputs in all test response compression sub-networks.

[0014] The condition that the scan chains in the same subset of scan trees are connected to the same XOR gate comprises: in the first group of scan flip-flops corresponding to the scan chains connected to the same XOR gate, any pair of scan flip-flops does not have the same predecessor.

[0015] In an embodiment, the method of constructing a single stuck-at fault scan forest comprises:

[0016] (1) setting a parameter g representing the number of scan chains driven by one output of the demultiplexer;

[0017] (2) in the case that the current scan flip-flop set Q and the unprocessed scan flip-flop set U are not empty, performing (2a) to (2d) until the current scan flip-flop set Q is empty, to group the scan flip-flops in the current scan flip-flop set Q and obtain a scan flip-flop group.

[0018] (2a) randomly pick a scan flip-flop f from the current scan flip-flop set Q and place it in the scan flip-flop group set Q1, calculate the PPO and OUT(f) of the scan flip-flop f which is reachable by combining the paths of the scan flip-flops in the scan flip-flop group set Q1;

[0019] (2b) if the number of scan flip-flops in the scan flip-flop group set Q1 |Q1| < g, execute (2c) to (2d) until |Q1| = g;

[0020] (2c) randomly pick a scan flip-flop f1 from the unprocessed scan flip-flop set U, determine whether the scan flip-flop f1 converges with any element in the scan flip-flop group set Q1, if not, place the scan flip-flop f1 in the scan flip-flop group set Q1; otherwise, place the scan flip-flop f1 back in the unprocessed scan flip-flop set U;

[0021] (2d) randomly pick a scan flip-flop f1 from the current scan flip-flop set Q, determine whether the scan flip-flop f1 converges with any element in the scan flip-flop group set Q1, if not, place the scan flip-flop f1 in the scan flip-flop group set Q1; otherwise, record the PPO and OUT(f1) of the scan flip-flop f1 which is reachable, and place the scan flip-flop f1 in the unprocessed scan flip-flop set U;

[0022] (3) construct single fixed pattern fault scan forest based on the scan flip-flop groups, comprising:

[0023] (3a) determine the number of internal scan chains c e , the number of external scan chains c i and the parameter k of the gated logic; if the number of internal scan chains c e and the number of external scan chains c i directly driven by ATE are equal, determine the depth d of the scan tree according to the number of scan flip-flops, the number of internal scan chains c e , the number of external scan chains c i and the parameter k;

[0024] (3b) construct the scan tree from left to right: randomly pick a scan flip-flop group G1, and sequentially place the g scan flip-flops in it as the first scan flip-flops of the scan chains in the same scan tree;

[0025] (3c) randomly pick a scan flip-flop group G2, and sequentially connect the g scan flip-flops in it to the g scan chains; repeat this operation until the depth of the current scan tree reaches d;

[0026] Repeat (2) and (3) until all k groups of scan trees are constructed to obtain the single fixed pattern fault scan forest.

[0027] In one embodiment, the constructed single stuck-at fault scan forest placement test comprises:

[0028] (1) ~ (4) are performed until the test set T is empty, provided that the test set T is not empty:

[0029] (1) move a test t in the test set T into the front end buffer of the ATE, place the k-bit binary number 00...01 into the additional shift register of the gated logic using the repeater function r of the ATE, and activate the first group of scan trees;

[0030] (2) move the test data into the activated first group of scan trees using the repeater function of the ATE, while moving the test response of the previous test of the group of scan trees out;

[0031] (3) move the test data into the activated current group of scan trees using the repeater function of the ATE, while moving the test response of the previous test of the group of scan trees out; repeat this step (3) until all k groups of scan trees have received the moved-in test data;

[0032] (4) place all scan flip-flops into functional state and receive the test response using the repeater function of the ATE;

[0033] (5) move the test response of the last test out using the repeater function of the ATE and transfer to the ATE.

[0034] In one embodiment, the constructed single stuck-at fault scan forest placement test comprises:

[0035] (1) ~ (5) are performed until the test set T is empty, provided that the test set T is not empty:

[0036] (1) move a test t in the test set T into the front end buffer of the ATE, place the k-bit binary number 00...01 into the additional shift register of the gated logic using the repeater function of the ATE, and activate the first group of scan trees;

[0037] (2) move the test data into the activated first group of scan trees using the repeater function of the ATE;

[0038] (3) using the repeater function of the ATE to shift the additional shift register one bit to the left, to move the test data into the activated current group of scan trees, and to move the test response of the previous test out; repeating this step (3) until all k groups of scan trees are shifted in with test data; when the test data of the last group of scan trees is shifted in, the test response of the previous test of the group of scan trees is moved out;

[0039] (4) using the repeater function of the ATE to set the additional shift register to the k-bit binary number 00…01, to set all the first group of scan trees to the functional state and to receive the test response; when the first group of scan trees is activated, the test data of the group is re-shifted into the group of scan trees, and the test response of the current test is moved out to the ATE;

[0040] (5) using the repeater function of the ATE to set the additional shift register to 00…10, the second group of scan trees is activated and receives the test response; when the second group of scan trees is activated, the test data of the group is re-shifted into the group of scan trees; repeating this step (5) until the last group of scan trees receives the test response;

[0041] (6) using the repeater function of the ATE to move out the test response of the last test for the last group of scan trees to the ATE.

[0042] In an embodiment, the scan input is provided by the ATE through a time linear decoder, each output of the time linear decoder drives an input of a demultiplexer; the control signal of the clock signal is the output of a two-input AND gate, one input of the two-input AND gate is the original test enable signal, and the other input is the control signal x of the test phase, x = 1 is the test phase, and x = 0 is the normal working phase.

[0043] The time linear decoder includes one of a linear feedback shift register, a ring generator, and a software-defined linear feedback shift register.

[0044] In some implementations, the test is set based on the constructed single stuck-at fault scan forest, including:

[0045] In the case that the test set T is not empty, (1)-(5) are executed until the test set T is empty:

[0046] (1) moving the test t in the test set T into the front-end buffer of the ATE, and moving the seed of the test t into the time linear decoder;

[0047] (2) using the repeater function of the ATE to set the k-bit binary number 00…01 into the additional shift register of the gated logic, to activate the first group of scan trees;

[0048] (3) using the repeater function of the ATE to move the test data into the first set of activated scan trees while moving the test responses of the previous test of the set of scan trees out;

[0049] (4) using the repeater function of the ATE to shift the additional shift register one bit to the left, moving the test data into the current set of activated scan trees while moving the test responses of the previous test of the set of scan trees out; repeat this step (4) until all k sets of scan trees are moved in with test data;

[0050] (5) using the repeater function of the ATE to set all scan flops to functional state and receive the test responses;

[0051] (6) using the repeater function of the ATE to move the test responses of the last test out and go to the ATE.

[0052] In one embodiment, the test is placed based on the constructed single stuck-at fault scan forest, including:

[0053] If the test set T is not empty, perform (1) - (7) until the test set T is empty:

[0054] (1) move the test t in the test set T into the front end buffer of the ATE and move the seed of the test t into the temporal linear decoder;

[0055] (2) using the repeater function of the ATE to place the k-bit binary data 00...01 into the additional shift register of the gated logic, activating the first set of scan trees;

[0056] (3) using the repeater function of the ATE to move the test data into the first set of activated scan trees while placing the data of the external scan chain into the temporal linear decoder;

[0057] (4) using the repeater function of the ATE to shift the additional shift register one bit to the left, moving the test data into the current set of activated scan trees while moving the test responses of the previous test of the set of scan trees out; repeat this step (4) until all k sets of scan trees are moved in with test data; when placing the test data of the last set of scan trees, move the test responses of the previous test of the set of scan trees out;

[0058] (5) using the repeater function of the ATE to freeze the clock signal of all scan flops, re-mov ing the seed of the test t into the decompressor in the next l clock cycles;

[0059] (6) Using the repeater function of the ATE to put additional shift registers into the k-bit binary number 00...01, put all scan flip-flops of the first group of scan trees into functional state and receive test responses; when activating the first group of scan trees, re-migrate the test data of the group of scan trees into the group of scan trees, while the external scan chain pins migrate corresponding test data;

[0060] (7) Using the repeater function of the ATE to put additional shift registers into the k-bit binary number 00...10, the second group of scan trees is activated and receives test responses; when activating the second group of scan trees, re-migrate the test data of the group of scan trees into the group of scan trees, while the external scan chain pins migrate corresponding test data; repeat this step (7) until the last group of scan trees receives test responses;

[0061] (8) Using the repeater function of the ATE to migrate the test responses of the last group of scan trees to the ATE.

[0062] Compared with the prior art, one or more embodiments of the present application can bring at least the following beneficial effects:

[0063] The scan forest construction process of the method of the present application can control CPU time and memory overhead very low, and the test migration technology is also efficient and low in power consumption, which can greatly reduce test power consumption without increasing test time, and the low power consumption test technology can effectively reduce test data capacity. On this basis, the test migration technology of the present application can also reduce capture power consumption and capture cycle power consumption under the condition of increasing test time by about one time. The present application can quickly calculate and greatly reduce memory overhead, and quickly realize scan forest construction to adapt to the needs of large-scale digital VLSI industry design. BRIEF DESCRIPTION OF DRAWINGS

[0064] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope.

[0065] Figure 1 is a scan test method flowchart provided by an embodiment of the present application;

[0066] Figure 2 is a low power consumption scan forest structure schematic diagram of ATE direct driving scan input provided by an embodiment of the present application;

[0067] Figure 3 is a scan forest structure schematic diagram for reducing migration and capture power consumption provided by an embodiment of the present application;

[0068] Figure 4 is a low power scan forest structure with response compressor provided by an embodiment of the present application;

[0069] Figure 5 is a low power scan forest structure with sequential linear decompressor provided by an embodiment of the present application;

[0070] Figure 6 is a structure with (or without) sequential linear decompressor provided by an embodiment of the present application, wherein (a) is a structure without decompressor, (b) is an LFSR, (c) is a ring generator, and (d) is a software defined LFSR;

[0071] Figure 7 is a low power scan forest structure with reduced shift-in and capture power provided by an embodiment of the present application. DETAILED DESCRIPTION

[0072] The technical solutions in the embodiments of the present application will be clearly and completely described in connection with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0073] Example One

[0074] The present embodiment provides a scan test method, as shown in Figure 1 , comprising:

[0075] Step 100, constructing a low power single stuck-at fault scan forest as shown in Figure 2 , the scan forest comprising a plurality of scan inputs and a plurality of scan trees, each scan input being driven by an ATE ((Automatic Test Equipment, integrated circuit automatic test machine); each pin of the ATE drives a demultiplexer (dmux), each demultiplexer drives a plurality of scan trees, realizing that the scan input end of the scan tree is directly driven by the ATE, each scan tree corresponding to each demultiplexer is controlled by different clock signals of the gating logic, each scan tree comprises a plurality of scan chains, and each scan chain comprises a plurality of scan flip-flops; and

[0076] Step 200, placing a test based on the constructed single stuck-at fault scan forest.

[0077] The key components of the single fixed pattern fault scan forest scan test are: each multi-demultiplexer drives multiple outputs, each output of the multi-demultiplexer drives multiple scan chains (c 1,1 ,c 1,2 ,…,c 1,d ), (c 2,1 ,c 2,2 ,…,c 2,d ), …, (c g,1 ,c g,2 ,…,c g,d ), which form a scan tree, wherein d and g are the depth of the scan chain and the size of the scan flip-flop group, respectively; it is required that there is no same combination successor (in the combinational circuit of a single frame) between any two scan flip-flops in any scan flip-flop group (c 1,1 ,c 2,1 ,…,c g,1 ),(c 1,2 ,c 2,2 ,…,c g,2 ),…,(c 1,d ,c 2,d ,…,c g,d ).

[0078] Each scan input of the embodiment is driven by the ATE, each pin of the ATE drives a multi-demultiplexer (dmux), each multi-demultiplexer drives multiple scan trees, which can realize that the ATE directly drives the scan input end of the scan tree, and each multi-demultiplexer controls each scan tree corresponding to it through different clock signals of the gate logic, which reduces the calculation time and storage overhead without affecting the fault coverage, and further realizes the low-power scan test.

[0079] Example Two

[0080] On the basis of the first embodiment, in order to reduce power consumption, the single fixed pattern fault scan forest is constructed in the following way to obtain multiple scan flip-flop groups, including:

[0081] (1) Set the parameter g, which represents the number of scan chains driven by one output of the multi-demultiplexer, and also represents the size of the scan flip-flop group;

[0082] (2) In the case that the current scan flip-flop set Q and the unprocessed scan flip-flop set U are not empty, (2a) to (2d) are executed until the current scan flip-flop set Q is empty, so as to group the scan flip-flops in the current scan flip-flop set Q and obtain multiple scan flip-flop groups;

[0083] (2a) randomly pick a scan flip-flop f from the current scan flip-flop set Q and place it in the scan flip-flop group set Q1, calculate the PPO and OUT(f) of the scan flip-flop f which is reachable by combining the paths of the scan flip-flops in the scan flip-flop group set Q1;

[0084] (2b) if the number of scan flip-flops in the scan flip-flop group set Q1 |Q1| < g, perform (2c) to (2d) until |Q1| = g;

[0085] (2c) randomly pick a scan flip-flop f1 from the unprocessed scan flip-flop set U, determine whether the scan flip-flop f1 converges with any element in the scan flip-flop group set Q1, if not, place the scan flip-flop f1 in the scan flip-flop group set Q1; otherwise, place the scan flip-flop f1 back in the unprocessed scan flip-flop set U;

[0086] (2d) randomly pick a scan flip-flop f1 from the current scan flip-flop set Q, determine whether the scan flip-flop f1 converges with any element in the scan flip-flop group set Q1, if not, place the scan flip-flop f1 in the scan flip-flop group set Q1; otherwise, record the PPO and OUT(f1) of the scan flip-flop f1 which is reachable, and place the scan flip-flop f1 in the unprocessed scan flip-flop set U; perform (3) if the current scan flip-flop set Q is empty:

[0087] (3) construct a single fixed pattern fault scan forest based on the scan flip-flop groups, including:

[0088] (3a) determine the number of internal scan chains c e , the number of external scan chains c i and the parameter k (demultiplexer fan-out factor) of the gated logic; if the number of internal scan chains c e and the number of external scan chains c i directly driven by ATE are equal, determine the depth d of the scan tree according to the number of scan flip-flops, the number of internal scan chains c e , the number of external scan chains c i and the parameter k;

[0089] (3b) construct the scan tree from left to right: randomly pick a scan flip-flop group G1, and sequentially place the g scan flip-flops in it as the first scan flip-flops of the scan chains in the same scan tree;

[0090] (3c) randomly pick a scan flip-flop group G2, and sequentially connect the g scan flip-flops in it to the g scan chains; repeat this operation until the depth of the current scan tree reaches d;

[0091] Repeat (2) and (3) until all k groups of scan tree are constructed, and a single fixed pattern fault scan forest is obtained.

[0092] The method for constructing the single fixed pattern fault scan forest in the embodiment does not need to store a large two-dimensional array, and the memory overhead can be reduced to almost linear. Meanwhile, it is not necessary to repeatedly collect the set of PO and PPO reachable by each scan flip-flop in the single frame combinational circuit, so the CPU time can also be controlled very well. When calculating the set of PO and PPO reachable by each scan flip-flop i, only the sub-circuit in the single frame combinational circuit reachable from the scan flip-flop needs to be searched, so the calculation CPU time can be controlled to be very low, and the fault coverage is not affected.

[0093] The worst case memory overhead of the construction method needs to store the OUT[i] function of all scan flip-flops i at the same time, and the size of the OUT[i] function should be much smaller than the number of all scan flip-flops, regardless of the size of the circuit. Therefore, the memory overhead of the OUT[i] function is still not in the same order of magnitude as the two-dimensional array of scan flip-flops. In fact, in most cases, the memory overhead is much lower than the memory required to record the set of PPO and PO reachable by all scan flip-flops.

[0094] The method for constructing the scan forest in the embodiment is applied to an actual design, which contains about 1.1 million scan flip-flops and 11 million gates. The scan forest designed based on the embodiment costs about 10 hours of calculation time and about 20G of memory overhead. Compared with the scan forest in the prior art, the calculation time and memory overhead are significantly reduced.

[0095] Example Three

[0096] In the method of the embodiment, before being placed into test based on the constructed single fixed pattern fault scan forest, the method further includes:

[0097] Constructing Figure 2 or Figure 3 The test response compactor XOR Network includes at least one test response compression sub-network XOR network 1, XOR network 2, …, XOR network k-1, XOR network k constructed for a group of scan trees controlled by the same clock signal, as shown in Figure 4 Each test response compression sub-network is constructed based on an XOR gate, and the number of outputs of the test response compactor is the maximum number of outputs in all test response compression sub-networks; wherein the condition that the scan chains in the same group of scan trees are connected to the same XOR gate includes that in the first group of scan flip-flops corresponding to the scan chains connected to the same XOR gate, any pair of scan flip-flops does not have the same predecessor.

[0098] In this embodiment, each group of scan trees constructs a test response compression subnetwork. Each group of scan trees is controlled by a different clock signal, and each test response compression subnetwork is composed of XOR gates. The test response compression is constructed as follows: the scan chain (c) in the same group of scan trees 1,1 ,c 1,2 ,…,c 1,d ),(c 2,1 ,c 2,2 ,…,c 2,d ),…,(c g,1 ,c g,2 ,…,c g,d The condition for all of them to be connected to the same XOR gate is: the first group of scan flip-flops (c 1,1 ,c 2,1 ,…,c g,1 In a single frame, no pair of scan flip-flops can have the same predecessor in the combinational circuit section; similarly, scan flip-flop groups (c 1,2 ,c 2,2 ,…,c g,2 ),..., and (c 1,d ,c 2,d ,…,c g,d Similar conditions must also be met, so that single fixed-type fault scan forests can efficiently achieve test compression.

[0099] When constructing the test response compressor, each scan trigger i needs to compute IN[i] to reach the set of PI and PPI of each scan trigger; if a scan chain fails to connect to an XOR gate input, the IN[] table of all triggers in the relevant scan chain is retained until the scan chain is connected to the test response compressor. This strategy avoids redundant computation of the IN[] table, thus saving CPU time.

[0100] Similar to calculating the OUT[] function, the IN[] function, in the worst case, requires storing the IN[] functions of all scan flip-flops. Since the number of PPIs and PIs for each scan flip-flop is very limited, the size of the IN[] function for each scan flip-flop is far less than the total number of scan flip-flops, even far less than 1%. For example... Figure 4 As shown, in the gated logic, each clock line-driven scan chain constructs an independent test response compressor. The outputs of the k test response compression sub-networks (XOR networks) corresponding to the response compressor are connected to k multiplexers (MUX). Assume the outputs of the k test response compression sub-networks are O1, O2, ..., O... k The outputs O1, O2, ..., O of the k test response compression subnetworks k correspond Figure 4 SO1, SO2, ... SOm-1 , SO m .

[0101] The final output number m required by the entire test response compressor is:

[0102] m = max (O1, O2, …, O k ),

[0103] The additional pin corresponding to the multiplexer MUX of the test response compressor and the additional pin of DMUX can be realized by an additional shift register, so the number is reduced to 1.

[0104] Example Four

[0105] In the case that the single stuck-at fault scan forest is constructed and the corresponding test set T is also generated, the following low-power test insertion process can be performed to realize low-power scan testing.

[0106] Based on the constructed single stuck-at fault scan forest, the test insertion includes:

[0107] In the case that the test set T is not empty, (1) ~ (4) are performed until the test set T is empty:

[0108] (1) Move the test t in the test set T to the front-end cache of the ATE, use the repeater function of the ATE to insert the k-bit binary number 00…01 into the additional shift register of the gated logic, and activate the first group of scan trees; for example, each dmux is connected to k scan trees, each scan tree includes a plurality of scan chains, the first group of scan trees can include the leftmost one of the scan trees connected by each dmux, and these scan trees form a group, and a total of k groups of scan trees can be obtained; Figure 2

[0109] (2) Use the repeater function of the ATE to move the test data into the activated first group of scan trees, and move the test response of the previous test of the group of scan trees out;

[0110] (3) Use the repeater function of the ATE to move the additional shift register left by one bit, move the test data into the activated current group of scan trees, and move the test response of the previous test of the group of scan trees out; repeat this step (3) until all k groups of scan trees receive the moved-in test data;

[0111] (4) Use the repeater function of the ATE to set all scan flip-flops to functional state and receive the test response;

[0112] (5) Use the repeater function of the ATE to move the test response of the last test out and to the ATE.​

[0113] The low-power test placement procedure of the embodiment is based on Figure 2 The DFT structure of the scan forest is shown in Fig. 1. The employed gating logic is that only part of the scan chains is active in any shift cycle. The low-power test technique with the gating logic is implemented by an additional shift register. By shifting 00...01 into the additional shift register, only 1 / k of the scan flops are active at any time. After shifting the test data into the active 1 / k of the scan flops, the data in the additional shift register is left shifted to 00...10, and the test data is re-shifted into the second part of the active scan flops by using the repeater function of the ATE. In this process, the first part of the scan flops transmitting the test data are in frozen state. The above operation is repeated until all the scan flops receive the test data (shifted in). All the scan flops are set to functional state and receive the test response data of the test. The rest of the tests are placed into the circuit and the test responses are received by using similar strategy. With this strategy, all the scan flops receive the test response at the same time, and thus the power consumption of the capture cycle cannot be reduced. The test time TA required by the current test strategy is:

[0114] TA = (k - d + 1) - vec + k - d

[0115] where k is the parameter of the gating logic, d is the depth of the scan forest, vec is the number of tests, and k - d is the number of clock cycles required for the test response of the last test.

[0116] Example Five

[0117] In the case that the single stuck-at fault scan forest is constructed and the corresponding test set T is generated, the following low-power test placement procedure for reducing the power consumption of the capture can also be performed to implement the low-power scan test.

[0118] The test placement based on the constructed single stuck-at fault scan forest includes:

[0119] In the case that the test set T is not empty, (1) to (5) are performed until the test set T is empty:

[0120] (1) Shift the test t in the test set T into the front-end buffer of the ATE, and place the k-bit binary number 00...01 into the additional shift register of the gating logic by using the repeater function of the ATE to activate the first group of scan trees;

[0121] (2) Shift the test data into the activated first group of scan trees by using the repeater function of the ATE;

[0122] (3) Use the repeater function of the ATE to shift the additional shift register one bit to the left, moving the test data into the currently activated set of scan trees, while moving the test response from the previous test out; repeat this step (3) until all k sets of scan trees have been shifted in with test data; when the last set of scan trees has been shifted in with test data, move the test response from the previous test on this set of scan trees out;

[0123] (4) Use the repeater function of the ATE to place the additional shift register into the k-bit binary number 00...01, placing all first set of scan trees into the functional state and receiving the test response; when the first set of scan trees is activated, re-shift the test data for this set into the set of scan trees, while moving the test response from the current test out to the ATE;

[0124] (5) Use the repeater function of the ATE to place the additional shift register into 00...10, activating the second set of scan trees and receiving the test response; when the second set of scan trees is activated, re-shift the test data for this set into the set of scan trees, while moving the test response from the current test out to the ATE; repeat this step (5) until the last set of scan trees receives the test response;

[0125] (6) Use the repeater function of the ATE to move the test response from the last test for the last set of scan trees out to the ATE.

[0126] The low power test placement flow of this embodiment is based on Figure 2 or Figure 3The DFT structure of the scan forest is shown. The gating logic employed ensures that only a portion of the scan chain is active during any shift cycle. The low-power testing technique using this gating logic is implemented through an additional register. By shifting 00…01 into the additional shift register, only 1 / k of the scan triggers are active at any given time. After shifting the test data into the active 1 / k scan triggers, the data in the additional shift register is left-shifted to 00…10, and the test data is re-shifted into the second set of active scan triggers using the ATE's repeater function. During this process, the first set of scan triggers transmitting test data is frozen. This process is repeated until all scan triggers have received the test data. The strategy for receiving test responses differs from the previous embodiment: the first group of scan triggers is set to the functional state and receives the test response data, while the other scan triggers are frozen. The test data placed in the ATE front-end buffer is re-placed into the active scan tree. The additional shift register is shifted left to 00…10, the second scan tree is activated and receives test response data; the test placed in the ATE front-end buffer is re-placed into the activated scan tree. A similar strategy is used to make each scan tree receive test responses. Each test is placed into each scan tree twice, and each test has k capture cycles, so the total test time required for the entire test process is approximately twice that required in Example 4.

[0127] The test time TA required to use the test strategy described in this embodiment is:

[0128] TA=[(2k-1)·d+k]·vec+d

[0129] Where k is a parameter of the gating logic, d is the depth of the scan forest, and vec is the number of tests. The low-power test insertion technique of this embodiment can reduce the power consumption of the capture cycle to approximately 1 / k, and the required test time is approximately twice that of the previous embodiment. The rightmost term d represents the number of clock cycles required to remove the last test in response to the last set of scan tree tests.

[0130] Example Six

[0131] like Figure 5 As shown, in this embodiment, the scan input is provided by the ATE through a temporal linear decoder decompresor, and each output of the temporal linear decoder decompresor drives the input of a multiplexer; further, as Figure 7 As shown, the control signal test' of the clock signal can be the output of a two-input AND gate. One input of the two-input AND gate is the original test enable signal test, and the other input is the control signal x for the test phase. When x = 1, it is the test phase, and when x = 0, it is the normal operation phase.

[0132] The timing linear decoder includes one of a linear feedback shift register, a ring generator, and a software defined linear feedback shift register.

[0133] The scan inputs can be passed through a timing linear decoder decompresor as shown in Figure 5 or Figure 7 The timing linear decoder decompresor drives the inputs of a plurality of demultiplexers, and each of the plurality of demultiplexers outputs drives a scan tree. Figure 6 (a) in FIG. 1 shows a conventional structure without a decompresor, the timing linear decoder used in the embodiment can be a linear feedback shift register (LFSR) as shown in Figure 6 (b) in FIG. 1, Figure 6 a ring generator as shown in (c) in FIG. 1, and Figure 6 a software defined linear feedback shift register (SLFSR) as shown in (d) in FIG. 1, and the same plurality of demultiplexers drive k scan trees.

[0134] The control signal connected to the clock signal is changed to test', where test' is the output of a two-input AND gate, and the inputs are the original test enable signal (scan enable) test and the test phase control signal x (x = 1 is the test phase, and x = 0 is the normal working phase).

[0135] The number of internal scan chains mentioned in the foregoing embodiments can refer to the number of pins of the ATE connected to the decompresor, and the number of external scan chains can refer to the number of outputs of the decompresor.

[0136] In the case where the single stuck-at fault scan forest is constructed and the corresponding test set T is also generated, the following low-power test insertion process for reducing capture power consumption can also be performed to achieve low-power scan testing.

[0137] Based on the DFT structure with a timing linear decoder provided in the embodiment, in the case where the single stuck-at fault scan forest is constructed and the corresponding test set T is also generated, the following low-power test insertion process can also be performed to achieve low-power scan testing.

[0138] The test insertion based on the constructed single stuck-at fault scan forest includes:

[0139] In the case where the test set T is not empty, (1) to (5) are performed until the test set T is empty:

[0140] (1) move test t in test set T into the front end buffer of the ATE, and move the seed of test t into the sequential linear decoder;

[0141] (2) use the repeater function of the ATE to move the k-bit binary number 00...01 into the additional shift register of the gated logic, and activate the first group of scan trees;

[0142] (3) use the repeater function of the ATE to move the test data into the activated first group of scan trees, and move the test response of the previous test of the group of scan trees out;

[0143] (4) use the repeater function of the ATE to move the test data into the activated current group of scan trees and move the test response of the previous test of the group of scan trees out by moving the additional shift register one bit to the left; repeat step (4) until all k groups of scan trees are moved into the test data;

[0144] (5) use the repeater function of the ATE to set all scan flip-flops to the functional state and receive the test response;

[0145] (6) use the repeater function of the ATE to move the test response of the last test out and go to the ATE.

[0146] The low-power test placement of the embodiment is realized based on the DFT structure with a sequential linear decoder. The adopted gated logic is that only part of the scan chains is activated in any shift cycle. The low-power test technique using the gated logic is realized by an additional shift register. By moving 00...01 into the additional shift register, only 1 / k of the scan flip-flops is activated at any time. After the test data is moved into the activated 1 / k of the scan flip-flops, the data of the additional shift register is moved one bit to the left as 00...10, and the test data is moved into the second part of the activated scan flip-flops by using the repeater function of the ATE. In this process, the first part of the scan flip-flops transmitting the test data is in the frozen state. Repeat the above operation until all scan flip-flops receive the test excitation data. Set all scan flip-flops to the functional state and receive the test response data of the test. Use a similar strategy to place the remaining tests into the circuit and receive the test responses. Using this strategy, all scan flip-flops receive the test response at the same time, so the power consumption of the capture cycle cannot be reduced. The test time TA required by the test strategy described in the embodiment is:

[0147] TA = (k - d + 1) - vec + k - d

[0148] where k is the parameter of the gated logic, d is the depth of the scan forest, vec is the number of tests, l is the number of clock cycles required to place the test seed, and d represents the time required to shift out the test response of the last test at the last group of scan trees.

[0149] Example Seven

[0150] based on Figure 5 or Figure 7 The DFT structure of the timing linear decoder shown in the foregoing single stuck-at fault scan forest construction is completed and the corresponding test set T is also generated, the following low-power test placement process can be performed to realize low-power scan testing.

[0151] Based on the constructed single stuck-at fault scan forest placement test, comprising:

[0152] In the case where the test set T is not empty, (1) to (7) are performed until the test set T is empty:

[0153] (1) The test t in the test set T is moved to the front-end buffer of the ATE, and the seed of the test t is moved to the timing linear decoder;

[0154] (2) The repeater function of the ATE is used to place the k-bit binary data 00…01 into the additional shift register of the gated logic to activate the first group of scan trees;

[0155] (3) When the data of the external scan chain is placed into the timing linear decoder, the repeater function of the ATE is used to move the test data into the activated first group of scan trees;

[0156] (4) The repeater function of the ATE is used to shift the additional shift register left by one bit to move the test data into the activated current group of scan trees while shifting out the test response of the previous test of the group of scan trees; this step (4) is repeated until all k groups of scan trees are moved into the test data; when the test data of the last group of scan trees is placed, the test response of the previous test of the group of scan trees is shifted out;

[0157] (5) The repeater function of the ATE is used to freeze the clock signal of all scan flip-flops, and the seed of the test t is re-moved into the decompressor in the next l clock cycles;

[0158] (6) Using the repeater function of the ATE to put an additional shift register into the k-bit binary number 00...01, put all the scan flip-flops of the first group of scan trees into functional state and receive the test response; when activating the first group of scan trees, re-shift the test data of the group of scan trees into the group of scan trees, while the external scan chain pins shift in the corresponding test data;

[0159] (7) Using the repeater function of the ATE to put an additional shift register into the k-bit binary number 00...10, the second group of scan trees is activated and receives the test response; when activating the second group of scan trees, re-shift the test data of the group of scan trees into the group of scan trees, while the external scan chain pins shift in the corresponding test data; repeat this step (7) until the last group of scan trees receives the test response;

[0160] (8) Using the repeater function of the ATE to shift out the test response of the last group of scan trees to the ATE.

[0161] The low-power test insertion in the embodiment is implemented based on the DFT structure shown in Figure 5 or Figure 7 The adopted gating logic is that only part of the scan chains is activated in any shift cycle. The low-power test technique using the gating logic connected to the clock line of the scan flip-flop is implemented by an additional shift register. By shifting 00...01 into the additional shift register, only 1 / k of the scan flip-flops is activated at any time. After shifting the test data into the activated 1 / k of the scan flip-flops, the data of the additional shift register is left-shifted into 00...10, and the test data is re-shifted into the second part of the activated scan flip-flops by using the repeater function of the ATE. In this process, the first part of the scan flip-flops transmitting the test data is in a frozen state. Repeat the above operation until all the scan flip-flops receive the test data. After all the scan flip-flops receive the test excitation data, the test seed is re-shifted into the sequential linear decoder. At this time, the clock signal controlling all the scan flip-flops is all inactive, and the whole process needs 1 clock cycle.

[0162] The strategy for receiving test responses differs from that of Embodiment Six: the additional shift register is set to 00...01, the scan flops of the first set of scan trees are set to the functional state and receive the test responses for that test, while the other scan flops are set to the freeze state. The test stimulus data is reloaded into the active scan trees from the ATE front end buffer. The test stimulus data is reloaded into the first set of scan trees, and the external scan chain data is concurrently shifted into the circuit and the sequential linear decoders. The second set of scan trees is activated and receives the test response data; the test is reloaded into the active second set of scan trees as the test stimulus data is shifted into the external scan chain pins. A similar strategy is used to receive test responses for each set of scan trees. Each test is loaded into each set of scan trees twice, and there are k capture cycles for each test, so the test time required for the entire test is approximately twice that required for the embodiment.

[0163] The test time TA required for the test strategy described in this embodiment is:

[0164] TA = [(2k - 1) - d + k + 2 - 1] - vec + d

[0165] where k is the parameter of the gated logic, d is the depth of the scan forest, vec is the number of tests, and 1 is the width of the LFSR, ring generator, or software defined linear feedback shift register. The rightmost term d in the above expression indicates the time period required to shift out the test response for the last set of scan trees for the last test. The term 2 / indicates the time period required to shift the seed of the test into the LFSR, ring generator, or software defined linear feedback shift register twice. The test time expression contains (2k - 1) - d + k, where (2k - 1) - d is the test shift-in period, the first k - d cycles are the first phase of test loading, and the test is loaded k - 1 times during the test response collection period. The last set of scan trees does not require test data to be reloaded. The rightmost term d is the clock period required to shift out the test response for the last set of scan trees for the last test.

[0166] Although the present application has been described in terms of the embodiments set forth above, the content described is merely illustrative of the embodiments adopted for the purpose of facilitating the understanding of the present application and is not intended to limit the present application. Any person skilled in the art to which the present application pertains can make any modification and change in the form and details thereof without departing from the spirit and scope of the present application, and the patent protection scope of the present application shall be defined by the scope of the appended claims.

Claims

1. A scanning test method, characterized in that, Comprising: Constructing a single stuck - fault scan forest, which includes multiple scan inputs and multiple scan trees, and each scan input is driven by an ATE; Each pin driven by the ATE drives a demultiplexer, each demultiplexer drives multiple scan trees, each scan tree corresponding to each demultiplexer is controlled by different clock signals of the gating logic, each scan tree includes multiple scan chains, and each scan chain includes multiple scan flip - flops; Performing a test based on the constructed single stuck - fault scan forest; The constructed single stuck - fault scan forest includes: (1) When the set Q of current scan flip - flops and the set U of unprocessed scan flip - flops are non - empty, grouping the scan flip - flops in the set Q of current scan flip - flops to obtain scan flip - flop groups; (2) Constructing a single stuck - fault scan forest based on the scan flip - flop groups; repeating (1) and (2) until all k groups of scan trees are constructed to obtain a single stuck - fault scan forest.

2. The scanning test method according to claim 1, characterized in that, Before performing the test based on the constructed single stuck - fault scan forest, it further includes: Constructing a test response compressor, including at least one test response compression sub - network constructed for a group of scan trees controlled by the same clock signal, each test response compression sub - network is constructed based on exclusive - OR gates, and the number of outputs of the test response compressor is the maximum number of outputs among all test response compression sub - networks; Among them, the condition that the scan chains in the same scan tree subset are connected to the same exclusive - OR gate includes: among the first - group scan flip - flops corresponding to the scan chains connected to the same exclusive - OR gate, any pair of scan flip - flops has no same predecessor.

3. The scanning test method according to claim 1, characterized in that, The constructed single stuck - fault scan forest further includes: Setting a parameter g, representing the number of scan chains driven by one output of the demultiplexer; Step (1) includes: when the set Q of current scan flip - flops and the set U of unprocessed scan flip - flops are non - empty, performing (1a) to (1d) until the set Q of current scan flip - flops is empty to group the scan flip - flops in the set Q of current scan flip - flops to obtain scan flip - flop groups; (1a) Randomly taking out a scan flip - flop f from the set Q of current scan flip - flops and placing it in the scan flip - flop grouping set Q1, and calculating the PPO of the scan flip - flops reachable by the scan flip - flop f through the combinational path and the OUT(f) of the set of original outputs PO; (1b) If the number of scan flip - flops in the scan flip - flop grouping set Q1, |Q1| < g, perform (1c) to (1d) until |Q1| = g; (1c) Randomly taking out a scan flip - flop f1 from the set U of unprocessed scan flip - flops, and determining whether the scan flip - flop f1 converges with any element in the scan flip - flop grouping set Q1. If none of them converge, place the scan flip - flop f1 in the scan flip - flop grouping set Q1; otherwise, place the scan flip - flop f1 back into the set U of unprocessed scan flip - flops; (1d) Randomly select scan trigger f1 from the current scan trigger set Q, and determine whether scan trigger f1 converges with any element in the scan trigger group set Q1. If they do not converge, place scan trigger f1 in the scan trigger group set Q1; otherwise, record the PO of the scan triggers that scan trigger f1 can reach and the OUT(f1) of the PPO set, and place scan trigger f1 in the unprocessed scan trigger set U. Step (2) includes: (2a) Determine the number of internal scan chains c e Number of external scan chains c i and the gating logic parameter k; if the number of internal scan chains directly driven by the ATE is c e and the number of external scan chains c i If they are equal, then the number of scan triggers and the number of internal scan chains (c) are considered equal. e Number of external scan chains c i And the parameter k, determine the depth d of the scan tree; (2b) Constructing a scan tree from left to right: Randomly select a scan trigger group G1, and place the g scan triggers in it sequentially into the first scan trigger of the scan chain in the same scan tree; (2c) Randomly select scan trigger group G2 and connect the g scan triggers in it to the g scan chains in sequence; repeat this operation until the depth of the current scan tree reaches d.

4. The scanning test method according to claim 1, characterized in that, The constructed single-fixed fault scan forest placement test includes: If the test set T is not empty, execute (1) to (4) until the test set T is empty: (1) Move test t in test set T into the front-end buffer of ATE, and use the repeater function of ATE to set the k-bit binary number 00…01 into the additional shift register of the door control logic to activate the first group of scan trees; (2) Use the repeater function of ATE to move the test data into the first active scan tree, and at the same time move the test response of the previous test in the scan tree out; (3) Use the repeater function of ATE to shift the additional shift register one bit to the left, shift the test data into the currently active scan tree, and shift out the test response of the previous test of the scan tree; repeat this step (3) until all k scan trees have received the shifted test data. (4) Use the repeater function of ATE to set all scan triggers to the functional state and receive test responses; (5) Use the repeater function of ATE to remove the test response of the last test and transfer it to ATE.

5. The scanning test method according to claim 1, characterized in that, The constructed single-fixed fault scan forest placement test includes: If the test set T is not empty, execute (1) to (5) until the test set T is empty: (1) Move test t in test set T into the front-end buffer of ATE, and use the repeater function of ATE to set the k-bit binary number 00…01 into the additional shift register of the door control logic to activate the first group of scan trees; (2) Use the repeater function of ATE to move the test data into the first set of active scan trees; (3) Use the repeater function of ATE to shift the additional shift register one bit to the left, shift the test data into the currently active scan tree, and shift the test response of the previous test out; repeat this step (3) until all k scan trees have been shifted into the test data; when shifting the test data into the last scan tree, shift the test response of the previous test into the scan tree. (4) Use the repeater function of ATE to load the additional shift register with k bits of binary number 00…01, set all first group scan trees to the functional state and receive test responses; when the first group scan tree is activated, the test data of the group is shifted back into the group scan tree, and the test response of the current test is shifted out to ATE. (5) Use the repeater function of ATE to set the additional shift register to 00…10, the second group of scan trees is activated and receives the test response; when the second group of scan trees is activated, the test data of the group is shifted back into the group of scan trees; repeat this step (5) until the last group of scan trees receives the test response. (6) Use the repeater function of ATE to remove the last test for the last set of scan tree test responses to ATE.

6. The scanning test method according to claim 1, characterized in that, The scan input is provided by the ATE through a timing linear decoder. Each output of the timing linear decoder drives the input of a multiplexer. The control signal of the clock signal is the output of a two-input AND gate. One input of the two-input AND gate is the original test enable signal, and the other input is the control signal x for the test phase. When x=1, it is the test phase, and when x=0, it is the normal operation phase.

7. The scanning test method according to claim 6, characterized in that, The time-series linear decoder includes one of the following: a linear feedback shift register, a ring generator, and a software-defined linear feedback shift register.

8. The scanning test method according to claim 6, characterized in that, The constructed single-fixed fault scan forest placement test includes: If the test set T is not empty, execute (1) to (5) until the test set T is empty: (1) Move test t in test set T into the front-end buffer of ATE and move the seed of test t into the temporal linear decoder; (2) Use the repeater function of ATE to set the k-bit binary number 00…01 into the additional shift register of the door control logic to activate the first group of scan trees; (3) Use the repeater function of ATE to move the test data into the first active scan tree, and at the same time move the test response of the previous test in the scan tree out; (4) Use the repeater function of ATE to shift the additional shift register one bit to the left, shift the test data into the active current group of scan trees and shift out the test response of the previous test in the group of scan trees; repeat this step (4) until all k groups of scan trees have shifted in the test data. (5) Use the repeater function of ATE to set all scan triggers to the functional state and receive test responses; (6) Use the repeater function of ATE to remove the test response of the last test and transfer it to ATE.

9. The scanning test method according to claim 6, characterized in that, The constructed single-fixed fault scan forest placement test includes: If the test set T is not empty, execute (1) to (7) until the test set T is empty: (1) Move test t in test set T into the front-end buffer of ATE and move the seed of test t into the temporal linear decoder; (2) Use the repeater function of ATE to put the k-bit binary data 00…01 into the additional shift register of the door control logic to activate the first group of scan trees; (3) When putting the data of the external scan chain into the temporal linear decoder, the test data is moved into the first set of scan trees that are activated by using the repeater function of ATE; (4) Use the repeater function of ATE to shift the additional shift register one bit to the left, shift the test data into the active current group of scan trees and shift out the test response of the previous test of the group of scan trees; repeat this step (4) until all k groups of scan trees have shifted in the test data; shift out the test response of the previous test of the group of scan trees when putting in the test data of the last group of scan trees. (5) Use the repeater function of ATE to freeze the clock signals of all scan triggers, and then move the seed of test t back into the decompressor in the next l clock cycles; (6) Use the repeater function of ATE to load the additional shift register with k bits of binary number 00…01, set all the scan triggers of the first group of scan trees to the functional state and receive the test response; when the first group of scan trees is activated, the test data of the scan trees in the first group of scan trees is shifted back into the scan trees in the first group of scan trees, and the corresponding test data is shifted into the external scan chain pins. (7) Use the repeater function of ATE to set the additional shift register to k-bit binary number 00…10, the second group of scan trees is activated and receives the test response; when the second group of scan trees is activated, the test data of the scan tree is shifted back into the scan tree, and the corresponding test data is shifted into the external scan chain pin; repeat this step (7) until the last group of scan trees receives the test response. (8) Use the repeater function of ATE to remove the test response of the last test for the last group of scan trees to ATE.

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