A programmable bias generation circuit with a large dynamic range

Abstract

The present invention discloses a programmable bias generation circuit with a large dynamic range, which includes a 1-bit switch configuration word circuit for determining whether the generated bias voltage is above or below the reference voltage, an m-bit coarse adjustment configuration word circuit for coarsely adjusting the generated bias voltage, an n-bit fine adjustment configuration word circuit for finely adjusting the generated bias voltage, and an operational amplifier. The output end of the 1-bit switch configuration word circuit is connected to the inverting end of the operational amplifier and the input end of the n-bit fine adjustment configuration word circuit. The m-bit coarse adjustment configuration word circuit is connected to the non-inverting end of the operational amplifier. The output end of the operational amplifier is connected to the output end of the n-bit fine adjustment configuration word circuit and outputs the bias voltage. The advantage of the present invention is that it realizes the adjustment of the bias voltage with a large dynamic range.

Description

Technical Field

[0001] The present invention relates to the field of mixed-signal integrated circuits, and more particularly to a programmable bias generation circuit with a large dynamic range. Background Art

[0002] In mixed-signal integrated circuits, almost all chips require a bias circuit to provide corresponding bias voltages to supply each module to operate normally. The bias circuit is often made inside the chip to reduce the number of chip pins and facilitate testing and use. Most of the existing bias circuits are mainly based on a reference module to generate a fixed bias voltage value. However, due to process deviations, device mismatches, etc., it is often impossible to accurately ensure that the bias voltage value is exactly equal to the ideal value after the chip is actually produced. At the same time, in some special application scenarios, it is often necessary to generate a configurable bias voltage to debug the chip.

[0003] Chinese Patent Grant Publication No. CN216434790U discloses a device for adjusting voltage value and voltage temperature coefficient and a voltage bias circuit, which are provided with a reference current conversion module and a current adjustment module. Since the reference current conversion module converts the reference voltage with a voltage temperature coefficient of 0 output by the bandgap reference circuit into a reference current, the current adjustment module can output a current with an adjustable magnitude and / or direction and a voltage temperature coefficient of 0 based on the reference current. The non-inverting input terminal of the low-dropout voltage regulator circuit is connected to the output terminal of the current adjustment module to achieve the purpose of independently adjusting the voltage value, and the inverting input terminal of the low-dropout voltage regulator circuit is connected to the voltage output terminal with a non-zero voltage temperature coefficient of the bandgap reference circuit to achieve the purpose of independently adjusting the voltage temperature coefficient. Finally, the voltage bias circuit can independently adjust the voltage value and the voltage temperature coefficient. However, it mainly adjusts the output voltage temperature coefficient by adjusting the voltage at the inverting input terminal of the operational amplifier, and adjusts the output voltage of the entire circuit, that is, the bias voltage, by adjusting the output current of the current adjustment module. Therefore, the adjustment range of the bias voltage is limited by the output current range of the current adjustment module, and it is impossible to achieve a large dynamic range of bias voltage adjustment. Summary of the Invention

[0004] The technical problem to be solved by the present invention is the problem that the existing bias circuit cannot achieve a large dynamic range of bias voltage adjustment.

[0005] The present invention realizes the solution to the above technical problems through the following technical means: A programmable bias generation circuit with a large dynamic range, including a 1-bit switch configuration word circuit for determining whether the generated bias voltage is above or below the reference voltage, an m-bit coarse adjustment configuration word circuit for coarsely adjusting the generated bias voltage, an n-bit fine adjustment configuration word circuit for finely adjusting the generated bias voltage, and an operational amplifier. The output end of the 1-bit switch configuration word circuit is connected to the inverting end of the operational amplifier and the input end of the n-bit fine adjustment configuration word circuit. The m-bit coarse adjustment configuration word circuit is connected to the non-inverting end of the operational amplifier. The output end of the operational amplifier is connected to the output end of the n-bit fine adjustment configuration word circuit and outputs a bias voltage. The adjustment range of the bias voltage is the product of the adjustment range of the m-bit coarse adjustment configuration word circuit and the adjustment range of the n-bit fine adjustment configuration word circuit, where m and n are both positive integers.

[0006] Beneficial effects: The present invention determines whether the generated bias voltage is above or below the reference voltage through the 1-bit switch configuration word circuit, coarsely adjusts the generated bias voltage through the m-bit coarse adjustment configuration word circuit to make the bias power supply adjustable, and also finely adjusts the bias voltage through the n-bit fine adjustment configuration word circuit. After two adjustments, the adjustment range of the bias voltage is the product of the adjustment range of the m-bit coarse adjustment configuration word circuit and the adjustment range of the n-bit fine adjustment configuration word circuit, greatly expanding the adjustment range of the bias voltage and realizing the adjustment of the bias voltage with a large dynamic range.

[0007] Further, the 1-bit switch configuration word circuit includes a current source I0, a current source I1, and a switch S1. The switch S1 is a two-way selection switch. The switch S1 includes a selection end and two contacts. The power supply is connected to one contact through the current source I0, and the other contact is grounded through the current source I1. The selection end is respectively connected to the inverting end of the operational amplifier and the input end of the n-bit fine adjustment configuration word circuit, and the connection node is X.

[0008] Furthermore, if the 1-bit switch configuration word is 0, the switch S1 switches to the current source I0, the current flows from the power supply to the node X, and then flows into the n-bit fine adjustment configuration word circuit, generating a bias voltage V BIAS below the reference voltage V REF ; if the 1-bit switch configuration word is 1, the switch S1 switches to the current source I1, the current flows out from the n-bit fine adjustment configuration word circuit, passes through the node X and flows to the ground, generating a bias voltage V BIAS above the reference voltage V REF above.

[0009] Further, the m-bit coarse adjustment configuration word circuit includes m current sources I 1+x 、I 2+x,,, I m+x , PMOS transistor PM0 and m switches S 1+x , S 1+x ,,, S m+x , the source of the PMOS transistor PM0 is connected to the power supply, and the gate of the PMOS transistor PM0 is connected to its drain and outputs a reference voltage V REF to the non-inverting input of the operational amplifier. The drain of the PMOS transistor PM0 is respectively connected to m current sources I 1+x , I 2+x ,,, I m+x of one end. The other ends of the m current sources I 1+x , I 2+x ,,, I m+x are respectively grounded through switches S 1+x , S 1+x ,,, S m+x .

[0010] Furthermore, the current magnitude relationship of the m current sources in the m-bit coarse adjustment configuration word circuit is I 1+x = 2 × I 2+x = 4 × I 3+x =,,, = 2 m-1 × I m+x .

[0011] Furthermore, the m switches S 1+x , S 1+x ,,, S m+x are respectively controlled by the coarse adjustment configuration word coarse <m-1>Control <2>, <1>, <0>. When the coarse adjustment configuration word is 1, the corresponding switch is closed; when the coarse adjustment configuration word is 0, the corresponding switch is open.

[0012] Further, the m-bit coarse adjustment configuration word circuit is a 3-bit coarse adjustment configuration word circuit. The 3-bit coarse adjustment configuration word circuit includes three current sources I2, I3, I4, a PMOS transistor PM0, and three switches S2, S3, S4. The source of the PMOS transistor PM0 is connected to the power supply. The gate of the PMOS transistor PM0 is connected to its drain and outputs a reference voltage V REF To the non-inverting terminal of the operational amplifier. The drain of the PMOS transistor PM0 is respectively connected to one end of the three current sources I2, I3, I4. The other ends of the three current sources I2, I3, I4 are respectively grounded through the switches S2, S3, S4. The current magnitude relationship of the 3 current sources is I2 = 2×I3 = 4×I4. The switches S2, S3, S4 are respectively controlled by the coarse adjustment configuration words <2>, <1>, <0>. When the coarse adjustment configuration word is 1, the corresponding switch is closed; when the coarse adjustment configuration word is 0, the corresponding switch is open.

[0013] Further, the n-bit fine adjustment configuration word circuit includes n resistors connected in series in sequence. Each resistor is paralleled with a switch, for a total of n switches. The n switches are connected in series. The head end of the n-bit fine adjustment configuration word circuit is connected to the node X, and the tail end of the n-bit fine adjustment configuration word circuit is connected to the output terminal of the operational amplifier.

[0014] Further, the resistances of the n resistors connected in series in sequence are respectively (2 n-1 )R, (2 n-2 )R,..., 4R, 2R, R. The n switches are respectively controlled by the n-bit fine adjustment configuration word fine <n-1>, fine<4>, fine<3>, fine<2>, fine<1>, fine<0> control the corresponding switches to open and close. When the fine-tuning configuration word is 1, the corresponding switch closes; when the fine-tuning configuration word is 0, the corresponding switch opens.

[0015] Further, the n-bit fine-tuning configuration word circuit is a 6-bit fine-tuning configuration word circuit. The 6-bit fine-tuning configuration word circuit includes 6 resistors connected in series in sequence. Each resistor is in parallel with a switch, with a total of 6 switches. The 6 switches are connected in series. The head end of the 6-bit fine-tuning configuration word circuit is connected to node X, and the tail end of the 6-bit fine-tuning configuration word circuit is connected to the output end of the operational amplifier; the resistance values of the 6 resistors connected in series in sequence are 32R, 16R, 8R, 4R, 2R, and R respectively. The six switches are respectively controlled by the 6-bit fine-tuning configuration word fine<5>, fine<4>, fine<3>, fine<2>, fine<1>, fine<0> to open and close the corresponding switches. When the fine-tuning configuration word is 1, the corresponding switch closes; when the fine-tuning configuration word is 0, the corresponding switch opens.

[0016] The advantages of the present invention are as follows:

[0017] (1) The present invention determines whether the generated bias voltage is above or below the reference voltage through the 1-bit switch configuration word circuit, coarsely adjusts the generated bias voltage through the m-bit coarse-tuning configuration word circuit to make the bias power supply adjustable, and also finely adjusts the bias voltage through the n-bit fine-tuning configuration word circuit. After two adjustments, the adjustment range of the bias voltage is the product of the adjustment range of the m-bit coarse-tuning configuration word circuit and the adjustment range of the n-bit fine-tuning configuration word circuit, greatly expanding the adjustment range of the bias voltage and realizing the adjustment of the bias voltage with a large dynamic range.

[0018] (2) The present invention can generate 2 m levels of reference voltage V REF through the m-bit coarse-tuning configuration word. Through the 1-bit switch configuration word and the n-bit fine-tuning configuration word, 2 n+1 - 1 levels of bias voltage V BIAS can be generated. The range is from V REF - I×(2 n - 1)R to V REF + I×(2 n - 1)R, with a step of I×R. I is the current magnitude of the current sources I0 and I1. Thus, 2 m × (2 n+1 - 1) levels of bias voltage can be generated, realizing the configuration with a large dynamic range, high precision, and programmability. Description of the Drawings

[0019] Figure 1 The principle block diagram of a programmable bias generation circuit with a large dynamic range provided by an embodiment of the present invention;

[0020] Figure 2 The schematic diagram of the m-bit coarse adjustment configuration word circuit in a programmable bias generation circuit with a large dynamic range provided by an embodiment of the present invention;

[0021] Figure 3 The schematic diagram of the n-bit fine adjustment configuration word circuit in a programmable bias generation circuit with a large dynamic range provided by an embodiment of the present invention;

[0022] Figure 4 The schematic diagram of the bias voltage range in a programmable bias generation circuit with a large dynamic range provided by an embodiment of the present invention. Detailed implementation manners

[0023] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts fall within the protection scope of the present invention.

[0024] As Figures 1 - 4 shown, the present invention provides a programmable bias generation circuit with a large dynamic range, including a 1-bit switch configuration word circuit 1 that determines whether the generated bias voltage is above or below the reference voltage, an m-bit coarse adjustment configuration word circuit 2 that coarsely adjusts the generated bias voltage, an n-bit fine adjustment configuration word circuit 3 that finely adjusts the generated bias voltage, and an operational amplifier 4.

[0025] The output end of the 1-bit switch configuration word circuit 1 is connected to the inverting end of the operational amplifier 4 and the input end of the n-bit fine adjustment configuration word circuit 3. The m-bit coarse adjustment configuration word circuit 2 is connected to the non-inverting end of the operational amplifier 4. The output end of the operational amplifier 4 is connected to the output end of the n-bit fine adjustment configuration word circuit 3 and outputs a bias voltage. The adjustment range of the bias voltage is the product of the adjustment range of the m-bit coarse adjustment configuration word circuit 2 and the adjustment range of the n-bit fine adjustment configuration word circuit 3, where m and n are both positive integers. The programmable bias circuit of the present invention is controlled by an x-bit configuration word, where the 1-bit switch configuration word controls the voltage range; the m-bit coarse adjustment configuration word controls the reference voltage, thereby coarsely adjusting the bias voltage; and the n-bit fine adjustment configuration word controls the resistive digital-to-analog converter, thereby finely adjusting the bias voltage.

[0026] The 1-bit switch configuration word circuit 1 includes a current source I0, a current source I1, and a switch S1. The switch S1 is a two-way selection switch, which includes a selection terminal and two contacts. The power supply is connected to one of the contacts through the current source I0, and the other contact is grounded through the current source I1. The selection terminal is respectively connected to the inverting terminal of the operational amplifier 4 and the input terminal of the n-bit fine-tuning configuration word circuit 3, and the connection node is X.

[0027] If the 1-bit switch configuration word is 0, the switch S1 switches to the current source I0, and the current flows from the power supply to the node X, and then flows into the n-bit fine-tuning configuration word circuit 3, generating a bias voltage V BIAS below the reference voltage V REF ; if the 1-bit switch configuration word is 1, the switch S1 switches to the current source I1, and the current flows out from the n-bit fine-tuning configuration word circuit 3, through the node X to the ground, generating a bias voltage V BIAS above the reference voltage V REF .

[0028] The m-bit coarse-tuning configuration word circuit 2 includes m current sources I 1+x , I 2+x ,..., I m+x , a PMOS transistor PM0, and m switches S 1+x , S 1+x ,..., S m+x . The source of the PMOS transistor PM0 is connected to the power supply. The gate of the PMOS transistor PM0 is connected to its drain and outputs the reference voltage V REF to the non-inverting terminal of the operational amplifier 4. The drain of the PMOS transistor PM0 is respectively connected to one ends of the m current sources I 1+x , I 2+x ,..., I m+x . The other ends of the m current sources I 1+x , I 2+x ,..., I m+x are respectively grounded through the switches S 1+x , S 1+x ,..., S m+x .

[0029] In the m-bit coarse-tuning configuration word circuit 2, the current magnitude relationship of the m current sources is I 1+x = 2 × I 2+x = 4 × I 3+x =... = 2 m-1 × I m+x . The m switches S 1+x , S 1+x ,..., S m+x are respectively controlled by the coarse-tuning configuration word coarse <m-1>Control is performed on coarse<2>, coarse<1>, and coarse<0>. When the coarse adjustment configuration word is 1, the corresponding switch is closed; when the coarse adjustment configuration word is 0, the corresponding switch is open.

[0030] The n-bit fine adjustment configuration word circuit 3 includes n resistors connected in series in sequence. Each resistor is connected in parallel with a switch, for a total of n switches. The n switches are connected in series. The head end of the n-bit fine adjustment configuration word circuit 3 is connected to node X, and the tail end of the n-bit fine adjustment configuration word circuit 3 is connected to the output end of the operational amplifier 4.

[0031] The resistance values of the n resistors connected in series in sequence are (2 n-1 )R, (2 n-2 )R,..., 4R, 2R, R. The n switches are respectively controlled by the n-bit fine adjustment configuration word fine <n-1>, fine<4>, fine<3>, fine<2>, fine<1>, fine<0> control the corresponding switches to open and close. When the fine-tuning configuration word is 1, the corresponding switch closes; when the fine-tuning configuration word is 0, the corresponding switch opens.

[0032] The following takes the 10-bit programmable bias circuit as an example for illustration. The overall circuit diagram is as Figure 1 shown, including two switched current sources (I0, I1), an operational amplifier 4, a coarse-tuning circuit, a fine-tuning DAC, etc. The 10-bit configuration word is split into a 1-bit switch configuration word, a 3-bit coarse-tuning configuration word, and a 6-bit fine-tuning configuration word.

[0033] The 1-bit switch configuration word circuit 1 determines whether the generated bias voltage is above or below the reference voltage V REF . There are two current paths in the circuit. The current source I0 flows from the power supply into the node X, and the current source I1 flows from the node X into the ground. The one-way switch is switched through the 1-bit switch configuration word. If the 1-bit switch configuration word switch is 0, the switch is switched to the current source I0, and the current flows from the power supply to the node X and then into the DAC. Therefore, the generated bias voltage V BIAS is below the reference voltage V REF ; if the 1-bit switch configuration word switch is 1, the switch is switched to the current source I1, the current flows from the node X to the ground, and the current flows out of the DAC. Therefore, the generated bias voltage V BIAS is above the reference voltage V REF .

[0034] The 3-bit coarse-tuning configuration word circuit controls the reference voltage V REF , and coarsely tunes the generated bias voltage. The schematic diagram is as Figure 2 shown. The coarse-tuning circuit consists of three current sources (I2, I3, I4), a PMOS transistor (PM0), and three switches. The source of the PMOS transistor PM0 is connected to the power supply, and the gate of the PMOS transistor PM0 is connected to its drain and outputs the reference voltage V REF The non-inverting terminal of the operational amplifier 4 and the drain of the PMOS transistor PM0 are respectively connected to one end of three current sources I2, I3, and I4, and the other ends of the three current sources I2, I3, and I4 are respectively grounded through switches S2, S3, and S4. The current magnitudes of the three current sources satisfy the relationship I2 = 2×I3 = 4×I4. The three switches are respectively controlled by the coarse adjustment configuration words coarse<2>, coarse<1>, and coarse<0>. By using the 3-bit coarse adjustment configuration words coarse<2>, coarse<1>, and coarse<0> to control the corresponding switches to open and close, when the configuration word is 1, the corresponding switch closes; when the configuration word is 0, the corresponding switch opens. For example, if coarse<2:0> = 3’b101, the current sources I2 and I4 are connected to the circuit, and the total current I = I2 + I4 = 5×I4; if coarse<2:0> = 3’b011, the current sources I3 and I4 are connected to the circuit, and the total current I = I3 + I4 = 3×I4. By controlling the total current connected to the circuit, the reference voltage V REF .

[0035] With the 3-bit coarse adjustment configuration word, 8 different reference voltages V REF can be generated.

[0036] Through Figure 1 the "virtual short characteristic" of the operational amplifier 4, the voltage of the X node is also the reference voltage V REF .

[0037] The 6-bit fine adjustment configuration word circuit controls the resistor-type DAC to finely adjust the generated bias voltage. Its schematic diagram is as shown in Figure 3 . It consists of six resistors and six switches. Each resistor is in parallel with a switch, with a total of 6 switches. The 6 switches are connected in series. The head end of the 6-bit fine adjustment configuration word circuit is connected to the node X, and the tail end of the 6-bit fine adjustment configuration word circuit is connected to the output terminal of the operational amplifier 4; the resistance values of the 6 resistors connected in series in sequence are designed in binary, which are 32R, 16R, 8R, 4R, 2R, and R respectively. The six switches are respectively controlled by the 6-bit fine adjustment configuration words fine<5>, fine<4>, fine<3>, fine<2>, fine<1>, and fine<0> to open and close. When the configuration word is 1, the corresponding switch closes; when the configuration word is 0, the corresponding switch opens. For example, if switch = 1 and fine<5:0> = 6’b101101, the current source I1 is connected to the circuit, the resistors 32R, 8R, 4R, and R are short-circuited, and the total resistance connected to the circuit is 18R, and then the bias voltage V BIAS = V REF +I1×18R; If switch = 0 and fine<5:0> = 6’b000111, then current source I0 is connected to the circuit, resistors 4R, 2R, and R are short-circuited, and the total resistance in the circuit is 56R, and then the bias voltage V BIAS = V REF - I0×56R.

[0038] Combining the 1-bit switch configuration word and the 6-bit fine-tuning configuration word, based on the reference voltage V REF , 127 different bias voltages V BIAS can be generated. In this embodiment, I0 and I1 are defined as two currents with equal magnitudes and opposite directions, then the range of the bias voltage V BIAS is from V REF - I×63R to V REF + I×63R, with a step of I×R, as shown in Figure 4 .

[0039] In summary, through the 1-bit switch configuration word, 3-bit coarse-tuning configuration word, and 6-bit fine-tuning configuration word, a total of 8×127 = 1016 bias voltages can be generated, thus achieving a large dynamic range and intelligent configuration.

[0040] Similarly, for the bias circuit with an x-bit configuration word, 2 m levels of reference voltage V REF can be generated through the m-bit coarse-tuning configuration word, and 2 n+1 - 1 levels of bias voltage V BIAS can be generated through the 1-bit switch configuration word and the n-bit fine-tuning configuration word. The range is from V REF - I×(2 n - 1)R to V REF + I×(2 n - 1)R, with a step of I×R. Thus, 2 m ×(2 n+1 - 1) levels of bias voltage can be generated, achieving a large dynamic range, high precision, and programmable configuration.

[0041] Through the above technical solutions, the present invention can perform intelligent configuration of the bias voltage with a large dynamic range through the x-bit configuration word. Among them, the 1-bit configuration word controls the voltage range; the m-bit configuration word controls the reference voltage, thereby coarsely adjusting the bias voltage; the n-bit configuration word controls the resistor digital-to-analog converter, thereby finely adjusting the bias voltage. 2 m ×(2 n+1 - 1) levels of bias voltage can be generated, which can provide a large dynamic range, high precision, and configurable bias voltage for each module of the chip, thereby performing intelligent control and debugging of the chip.

[0042] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A programmable bias generation circuit with a large dynamic range, characterized in that It includes a 1-bit switch configuration word circuit for determining whether the generated bias voltage is above or below the reference voltage, an m-bit coarse adjustment configuration word circuit for coarsely adjusting the generated bias voltage, an n-bit fine adjustment configuration word circuit for finely adjusting the generated bias voltage, and an operational amplifier. The output terminal of the 1-bit switch configuration word circuit is connected to the inverting terminal of the operational amplifier and the input terminal of the n-bit fine adjustment configuration word circuit. The m-bit coarse adjustment configuration word circuit is connected to the non-inverting terminal of the operational amplifier. The output terminal of the operational amplifier is connected to the output terminal of the n-bit fine adjustment configuration word circuit and outputs the bias voltage. The adjustment range of the bias voltage is the product of the adjustment range of the m-bit coarse adjustment configuration word circuit and the adjustment range of the n-bit fine adjustment configuration word circuit, where m and n are both positive integers.

2. The programmable bias generation circuit with a large dynamic range according to claim 1, characterized in that The 1-bit switch configuration word circuit includes a current source I0, a current source I1, and a switch S1. The switch S1 is a two-way selection switch, which includes a selection terminal and two contacts. The power supply is connected to one of the contacts through the current source I0, and the other contact is grounded through the current source I1. The selection terminal is respectively connected to the inverting terminal of the operational amplifier and the input terminal of the n-bit fine adjustment configuration word circuit, and the connection node is X.

3. The programmable bias generation circuit with a large dynamic range according to claim 2, characterized in that If the 1-bit switch configuration word is 0, the switch S1 is switched to the current source I0, and the current flows from the power supply to the node X, and then flows into the n-bit fine-tuning configuration word circuit, generating a bias voltage V BIAS below the reference voltage V REF ; if the 1-bit switch configuration word is 1, the switch S1 is switched to the current source I1, and the current flows out of the n-bit fine-tuning configuration word circuit through the node X to the ground, generating a bias voltage V BIAS above the reference voltage V REF above.

4. The programmable bias generation circuit with a large dynamic range according to claim 2, characterized in that The m-bit coarse adjustment configuration word circuit includes m current sources I 1+x , I 2+x ,..., I m+x , a PMOS transistor PM0, and m switches S 1+x , S 1+x ,..., S m+x . The source of the PMOS transistor PM0 is connected to the power supply. The gate of the PMOS transistor PM0 is connected to its drain and outputs a reference voltage V REF to the non-inverting input of the operational amplifier. The drain of the PMOS transistor PM0 is respectively connected to one ends of the m current sources I 1+x , I 2+x ,..., I m+x . The other ends of the m current sources I 1+x , I 2+x ,..., I m+x are respectively grounded through the switches S 1+x , S 1+x ,..., S m+x .

5. The programmable bias generation circuit with a large dynamic range according to claim 4, characterized in that The current magnitude relationship of the m current sources in the m-bit coarse adjustment configuration word circuit is I 1+x = 2 × I 2+x = 4 × I 3+x =... = 2 m-1 × I m+x .

6. The programmable bias generation circuit with a large dynamic range according to claim 5, characterized in that The m switches S 1+x , S 1+x ,..., S m+x are respectively configured by the coarse adjustment configuration word coarse <m-1>...coarse<2>, coarse<1>, coarse<0> for control. When the coarse adjustment configuration word is 1, the corresponding switch is closed; < / m-1> When the coarse adjustment configuration word is 0, the corresponding switch is open.

7. The programmable bias generation circuit with a large dynamic range according to claim 6, characterized in that The m-bit coarse adjustment configuration word circuit is a 3-bit coarse adjustment configuration word circuit. The 3-bit coarse adjustment configuration word circuit includes three current sources I2, I3, I4, a PMOS transistor PM0, and three switches S2, S3, S4. The source of the PMOS transistor PM0 is connected to the power supply. The gate of the PMOS transistor PM0 is connected to its drain and outputs a reference voltage V REF to the non-inverting terminal of the operational amplifier. The drain of the PMOS transistor PM0 is respectively connected to one end of the three current sources I2, I3, I4. The other ends of the three current sources I2, I3, I4 are respectively grounded through the switches S2, S3, S4. The current magnitude relationship of the 3 current sources is I2 = 2×I3 = 4×I4. The switches S2, S3, S4 are respectively controlled by the coarse adjustment configuration words coarse<2>, coarse<1>, coarse<0>. When the coarse adjustment configuration word is 1, the corresponding switch is closed; When the coarse adjustment configuration word is 0, the corresponding switch is open.

8. The programmable bias generation circuit with a large dynamic range according to claim 2, characterized in that The n-bit fine adjustment configuration word circuit includes n resistors connected in series in sequence. Each resistor is in parallel with a switch, with a total of n switches. The n switches are connected in series. The head end of the n-bit fine adjustment configuration word circuit is connected to the node X, and the tail end of the n-bit fine adjustment configuration word circuit is connected to the output terminal of the operational amplifier.

9. The programmable bias generation circuit with a large dynamic range according to claim 8, characterized in that The resistances of the n resistors connected in series in sequence are respectively (2 n-1 )R, (2 n-2 )R,..., 4R, 2R, R. The n switches are respectively controlled by an n-bit fine tuning configuration word fine <n-1>...fine<4>, fine<3>, fine<2>, fine<1>, fine<0> control the corresponding switches to open and close. When the fine adjustment configuration word is 1, the corresponding switch is closed; < / n-1> When the fine adjustment configuration word is 0, the corresponding switch is open.

10. The programmable bias generation circuit with a large dynamic range according to claim 9, characterized in that The n-bit fine adjustment configuration word circuit is a 6-bit fine adjustment configuration word circuit. The 6-bit fine adjustment configuration word circuit includes 6 resistors connected in series in sequence. Each resistor is in parallel with a switch, with a total of 6 switches. The 6 switches are connected in series. The head end of the 6-bit fine adjustment configuration word circuit is connected to the node X, and the tail end of the 6-bit fine adjustment configuration word circuit is connected to the output terminal of the operational amplifier. The resistance values of the 6 resistors connected in series in sequence are 32R, 16R, 8R, 4R, 2R, and R respectively. The six switches are respectively controlled by the 6-bit fine adjustment configuration word fine<5>, fine<4>, fine<3>, fine<2>, fine<1>, fine<0> to open and close. When the fine adjustment configuration word is 1, the corresponding switch is closed; When the fine adjustment configuration word is 0, the corresponding switch is open.

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