Power consumption control device, method and high-speed interconnection interface

Abstract

The embodiment of the present invention discloses a power consumption control device, method and high-speed interconnection interface, wherein the device arranged on the transmitting end side of the high-speed interconnection interface includes: an interface power consumption management state machine, which is used to control the transmitting end to enter or exit the low power consumption state when the high-speed interconnection interface needs to enter or exit the low power consumption state, and input different enable signals to the clock gating unit; the clock gating unit is used to control the closing and opening of the transmission of the local clock signal of the transmitting end through the enable signal of the interface power consumption management state machine, so that the transmitting end: sends the local clock signal of the transmitting end after being controlled by the clock gating unit to the receiving end through the clock transmission channel, and sends data to the receiving end through the data transmission channel based on the local clock signal of the transmitting end after being controlled by the clock gating unit. The embodiment of the present invention can be applied to the scenario of power consumption state management of the high-speed interconnection interface, and can realize the rapid switching of the low power consumption state of the high-speed interconnection interface.

Description

Technical Field

[0001] The present invention relates to the field of high-speed interconnection, and in particular to a power consumption control device, method and a high-speed interconnection interface. Background Art

[0002] Traditional high-speed interconnect interfaces (such as Chiplet) divide states into PD (Power Down), PQ (Power Quiesce), PA (Power Active) and other states according to power consumption. These states are switched cyclically according to the requirements of the upper layer protocol, which is the so-called power management.

[0003] PA is the state of the high-speed interconnect interface during data transmission. In this state, power consumption is relatively high. If no data is transmitted for a long time, the high-speed interconnect interface needs to enter the PQ or PD state from the PA state to reduce power consumption, and then enter the PA state from the PQ state again during the next data transmission. Among them, the high-speed interconnect interface must be fast when switching states, otherwise the average power consumption of the entire system will be relatively large.

[0004] However, in the prior art, the switching time of the high-speed interconnect interface state is relatively long, and in particular, it is impossible to achieve fast switching of the low power consumption state. Summary of the invention

[0005] In view of this, the embodiments of the present invention provide a power consumption control device, method and high-speed interconnection interface to achieve fast switching of the high-speed interconnection interface to a low power consumption state.

[0006] In a first aspect, an embodiment of the present invention provides a power consumption control device, which is arranged at a transmitting end side of a high-speed interconnect interface, and the device includes:

[0007] The interface power consumption management state machine is used to: when the high-speed interconnect interface needs to enter a low-power consumption state, control the transmitting end of the high-speed interconnect interface to enter a low-power consumption state, and input a first enable signal to the clock gating unit; when the high-speed interconnect interface needs to exit the low-power consumption state, control the transmitting end of the high-speed interconnect interface to exit the low-power consumption state, and input a second enable signal to the clock gating unit;

[0008] The clock gating unit is used to control the closing and opening of the transmission of the local clock signal of the sending end of the high-speed interconnection interface through the first enable signal and the second enable signal, so that the sending end of the high-speed interconnection interface performs the following operations: sending the local clock signal of the sending end controlled by the clock gating unit to the receiving end through the clock transmission channel, and sending data to the receiving end through the data transmission channel based on the local clock signal of the sending end controlled by the clock gating unit.

[0009] Furthermore, the interface power consumption management state machine is also used to determine whether the high-speed interconnect interface needs to enter or exit a low power consumption state according to the power consumption requirement of the upper layer protocol.

[0010] Furthermore, the interface power management state machine is used to control the transmitter of the high-speed interconnect interface to enter a low power state, including:

[0011] After the first enable signal is input to the clock gating unit, a preset time period is waited, and after the waiting period is over, the sending end of the high-speed interconnect interface is controlled to enter a low power consumption state.

[0012] In a second aspect, an embodiment of the present invention provides another power consumption control device, which is arranged at a receiving side of a high-speed interconnect interface, and the device includes a receiving end power consumption control unit, which is used to:

[0013] Detecting the presence or absence of a clock signal from a transmitting end received by a receiving end of a high-speed interconnect interface through a clock transmission channel;

[0014] The receiving end of the high-speed interconnect interface is controlled to enter or exit a low power consumption state according to the detection result, wherein the receiving end of the high-speed interconnect interface processes the transmitting end data received through the data transmission channel based on the transmitting end clock signal.

[0015] Furthermore, the receiving end power consumption control unit is used to control the receiving end of the high-speed interconnect interface to enter or exit a low power consumption state according to the detection result, including:

[0016] After detecting that the received sending end clock signal changes from being present to being absent, outputting a first control signal to control the data receiving enable end of the receiving end of the high-speed interconnect interface to be invalid;

[0017] After detecting that the received sending end clock signal changes from non-existence to existence, a second control signal is output to control the data receiving enable end of the receiving end of the high-speed interconnect interface to be effective.

[0018] Furthermore, the receiving end power consumption control unit includes: a write clock signal terminal, which inputs the received sending end clock signal; a read clock signal terminal, which inputs the receiving end local clock control signal; and an empty signal terminal, which outputs an empty signal as the first control signal or the second control signal; wherein,

[0019] After the received sending end clock signal changes from being present to being absent, the write pointer stops counting, and the read pointer continues to increase under the drive of the read clock until the read and write pointers are equal, the receiving end power consumption control unit is read empty, and the output signal is used as the empty signal of the first control signal, and the empty signal is synchronized to the read clock domain by the synchronizer for read pointer control;

[0020] After the received sending end clock signal increases from zero to one, the write pointer starts counting, and the read pointer starts counting when the control signal output by the synchronizer becomes valid. If the read and write pointers are not equal, a null signal is output as the second control signal.

[0021] Furthermore, the receiving end power consumption control unit also includes a synchronizer for synchronizing the empty signal output by the receiving end power consumption control unit to the read clock domain to control the read pointer. The read pointer can only change when the synchronizer output signal is high.

[0022] Further, the synchronizer includes at least one stage of D flip-flop, wherein when the D flip-flops are cascaded in multiple stages, at the signal end of the cascaded D flip-flops:

[0023] The input terminal D of the first-stage D flip-flop is connected to a high level; the input terminal D of the next-stage D flip-flop is connected to the output terminal Q of the previous-stage D flip-flop; the output terminal Q of the last-stage D flip-flop is connected to the read enable terminal of the receiving-end power consumption control unit;

[0024] The signal inputted by the clock terminal Clk of each level of trigger is obtained according to the local clock signal of the receiving end, and the reset terminal Reset is connected to the empty signal terminal of the power consumption control unit of the receiving end.

[0025] In a third aspect, an embodiment of the present invention provides a power consumption control device, comprising: the power consumption control device as described in the first aspect above; and the power consumption control device as described in the second aspect above.

[0026] In a fourth aspect, an embodiment of the present invention provides a high-speed interconnection interface, including: a transmitting end, a receiving end, a data transmission channel and a clock transmission channel connecting the transmitting and receiving ends; and the power consumption control device described in the third aspect above.

[0027] Furthermore, the transmitting end includes:

[0028] A first asynchronous FIFO memory, used for storing data from the transmitting end, wherein a write clock signal terminal of the first asynchronous FIFO memory inputs a local clock signal from the transmitting end, and a read clock signal terminal inputs a clock signal output by a data serial-to-parallel converter;

[0029] A data serial-to-parallel converter is connected to the first asynchronous FIFO memory, the data transmitter and the clock gating unit respectively, and is used to: read the transmitting end data in the first asynchronous FIFO memory, and perform serial-to-parallel conversion on the data and then output it to the data transmitter; perform serial-to-parallel conversion on the clock signal output by the clock gating unit and then output it to the first asynchronous FIFO memory;

[0030] A data transmitter is connected to the data transmission channel and is used to drive the data transmission channel to send the serial-to-parallel converted data from the transmitting end to the receiving end of the high-speed interconnection interface through the data transmission channel;

[0031] The adjustment unit is connected to the clock gating unit and is used to perform frequency multiplication and phase modulation on the local clock signal of the sending end and then output it to the clock gating unit;

[0032] A clock serial-to-parallel converter, connected to the clock gating unit and the clock transmitter respectively, for performing serial-to-parallel conversion on the clock signal output by the clock gating unit and outputting the converted signal to the clock transmitter;

[0033] The clock transmitter is used to drive the clock transmission channel and send the serial-to-parallel converted clock signal to the receiving end of the high-speed interconnect interface through the clock transmission channel.

[0034] Furthermore, the receiving end includes:

[0035] A data receiver, used to drive the data transmission channel and receive the data from the sender;

[0036] A data clock serial-to-parallel converter is connected to the clock receiver, the data receiver and the second asynchronous FIFO memory respectively, and is used to: perform serial-to-parallel conversion on the sending end clock signal received by the clock receiver and the sending end data received by the data receiver, and output them to the second asynchronous FIFO memory;

[0037] A second asynchronous FIFO memory is used to synchronize the data of the transmitting end after the serial-to-parallel conversion by the data clock data serial-to-parallel converter to the local clock of the receiving end to complete the clock domain conversion, wherein the write clock signal terminal of the second asynchronous FIFO memory inputs the clock signal output by the serial-to-parallel converter, and the read clock signal terminal inputs the local clock signal of the receiving end;

[0038] The clock receiver is connected to the receiving end power consumption control unit and the data clock serial-to-parallel converter, and is used to drive the clock transmission channel, receive the clock signal sent by the transmitting end, and output it to the receiving end power consumption control unit and the data clock serial-to-parallel converter.

[0039] Furthermore, the interface is a chiplet interconnection interface.

[0040] In a fifth aspect, an embodiment of the present invention provides a power consumption control method, which is applied to the power consumption control device described in the first aspect, and the method includes:

[0041] When the high-speed interconnect interface needs to enter a low-power state, the interface power management state machine controls the transmitting end of the high-speed interconnect interface to enter a low-power state and inputs a first enable signal to the clock gating unit; when the high-speed interconnect interface needs to exit the low-power state, the interface power management state machine controls the transmitting end of the high-speed interconnect interface to exit the low-power state and inputs a second enable signal to the clock gating unit;

[0042] The clock gating unit controls the closing and opening of the transmission of the local clock signal of the sending end through the first enable signal and the second enable signal, so that the sending end of the high-speed interconnection interface performs the following operations: the local clock signal of the sending end controlled by the clock gating unit is sent to the receiving end of the high-speed interconnection interface through the clock transmission channel, and based on the local clock signal of the sending end controlled by the clock gating unit, the data is sent to the receiving end of the high-speed interconnection interface through the data transmission channel.

[0043] Furthermore, the method further comprises:

[0044] The interface power management state machine determines whether the high-speed interconnect interface needs to enter or exit a low power state according to the power consumption requirements of the upper layer protocol.

[0045] Furthermore, the interface power management state machine controls the transmitter of the high-speed interconnect interface to enter a low power state, including:

[0046] After the first enable signal is input to the clock gating unit, a preset time period is waited, and after the waiting period is over, the sending end of the high-speed interconnect interface is controlled to enter a low power consumption state.

[0047] In a sixth aspect, an embodiment of the present invention provides another power consumption control method, which is applied to the power consumption control device described in the second aspect, and the method includes:

[0048] Detecting the presence or absence of a clock signal from a transmitting end received by a receiving end of a high-speed interconnect interface through a clock transmission channel;

[0049] The receiving end of the high-speed interconnect interface is controlled to enter or exit a low power consumption state according to the detection result, wherein the receiving end of the high-speed interconnect interface processes the transmitting end data received through the data transmission channel based on the transmitting end clock signal.

[0050] Further, controlling the receiving end of the high-speed interconnect interface to enter or exit a low power consumption state according to the detection result includes:

[0051] After detecting that the received sending end clock signal changes from being present to being absent, outputting a first control signal to control the data receiving enable end of the receiving end of the high-speed interconnect interface to be invalid;

[0052] After detecting that the received sending end clock signal changes from non-existence to existence, a second control signal is output to control the data receiving enable end of the receiving end of the high-speed interconnect interface to be effective.

[0053] The technical solution provided by the embodiment of the present invention carries power consumption requirement information by controlling the presence or absence of a local clock signal at the sending end without adding additional costs to other data transmission channels, thereby controlling both the sending and receiving ends to enter or exit a low power consumption state, thereby achieving rapid switching of the low power consumption state of the high-speed interconnection interface, reducing the average power consumption of the high-speed interface, and is particularly suitable for low power consumption, high bandwidth, and low latency interconnection requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0055] Figure 1 A schematic diagram of the structure of a high-speed interconnect interface sending end side device provided in Embodiment 1 of the present invention;

[0056] Figure 2a A schematic diagram of the structure of a high-speed interconnect interface receiving end device provided in Embodiment 2 of the present invention;

[0057] Figure 2b A schematic diagram of a synchronizer structure provided in Embodiment 2 of the present invention;

[0058] Figure 2c A schematic diagram of the timing relationship between signals of a power consumption control device at a high-speed interconnect interface receiving end provided in Embodiment 2 of the present invention.

[0059] Figure 3 A schematic diagram of a high-speed interconnection interface structure provided in Embodiment 3 of the present invention;

[0060] Figure 4 A schematic diagram of the timing relationship between high-speed interconnect interface signals provided in Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0061] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0062] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0063] Embodiment 1

[0064] The embodiment of the present invention provides a high-speed interconnect interface sending end side device, see Figure 1The transmitting end side device includes a power consumption control device 10 and a transmitting end (including a data transmitting module 11 and a clock transmitting module 12) arranged on the transmitting end side of the high-speed interconnect interface. The power consumption control device 10 includes:

[0065] The interface power consumption management state machine 101 is used to: when the high-speed interconnect interface needs to enter a low-power consumption state, control the sending end of the high-speed interconnect interface (specifically, the data sending module 11) to enter a low-power consumption state, and input a first enable signal to the clock gating unit 102; when the high-speed interconnect interface needs to exit the low-power consumption state, control the sending end of the high-speed interconnect interface (specifically, the data sending module 11) to exit the low-power consumption state, and input a second enable signal to the clock gating unit 102;

[0066] The clock gating unit 102 is used to control the closing and opening of the transmission of the local clock signal of the sending end through the first enable signal and the second enable signal, so that the sending end of the high-speed interconnection interface (specifically the clock sending module 12) performs the following operations: the local clock signal of the sending end controlled by the clock gating unit 102 is sent to the receiving end of the high-speed interconnection interface through the clock transmission channel, and based on the local clock signal of the sending end controlled by the clock gating unit 102, the data is sent to the receiving end of the high-speed interconnection interface through the data transmission channel.

[0067] Among them, the two enable signals input by the interface power management state machine 101 to the clock gating unit 102 can be distinguished by the level of the signal voltage, for example, a high level signal is input to the clock gating unit 102 as the first enable signal, and a low level signal is input as the second enable signal. After receiving the first enable signal, the clock gating unit 102 controls the transmission of the local clock signal of the sending end to be turned off, and after receiving the second enable signal, controls the transmission of the local clock signal of the sending end to be turned on. As a result, the clock signal transmitted from the sending end of the high-speed interconnect interface to the receiving end through the clock transmission channel is no longer continuous but a local clock signal of the sending end that is sometimes absent. The receiving end of the high-speed interconnect interface can identify the power consumption requirement information carried therein by the presence or absence of the clock signal received: whether to exit the low power consumption state or enter the low power consumption state, and then switch the power consumption state of the receiving end according to the power consumption requirement. It should be noted that, during the period when the clock gating unit 102 controls the transmission of the local clock signal of the sending end to be turned off, it can also control the clock transmission channel to transmit other non-clock signals. As long as the receiving end of the high-speed interconnection interface receives other non-clock signals sent by the sending end through the clock transmission channel, it can determine that this signal is no longer the local clock signal of the sending end. For example, the clock gating unit 102 controls the transmission of the local clock signal of the sending end to maintain the transmission of a low-level signal.

[0068] In the embodiment of the present invention, the gated clock of the clock gating unit 102 has two input clock signals: one is Figure 1 The local clock signal of the transmitting end shown in the figure can be generated by the local clock of the transmitting end and then input to the clock gating unit 102 after frequency multiplication and phase modulation, and the clock gating unit 102 controls the opening and closing of its transmission; the other is the clock signal for the normal operation of the clock gating unit 102 ( Figure 1 ), which can be directly input to the clock gating unit 102 after being generated by the local clock of the sending end.

[0069] Furthermore, the interface power consumption management state machine 101 is also used to determine whether the high-speed interconnect interface needs to enter or exit a low power consumption state according to the power consumption requirement of the upper layer protocol.

[0070] As a preferred implementation, in order to ensure the correctness of data transmission, when it is necessary to enter a low power consumption state, it should be ensured that the receiving end of the high-speed interconnect interface stops receiving data from the sending end first, and then the sending end of the high-speed interconnect interface stops sending data to the receiving end of the high-speed interconnect interface. Correspondingly, the interface power consumption management state machine 101 is used to control the sending end of the high-speed interconnect interface to enter a low power consumption state, including: waiting for a preset time after inputting a first enable signal to the clock gating unit 102, and controlling the sending end of the high-speed interconnect interface (specifically the data sending module 11) to exit the low power consumption state after the waiting ends. Among them, the preset time should be greater than the following time: from the interface power consumption management state machine 101 inputting the first enable signal to the clock gating unit 102, until the receiving end of the high-speed interconnect interface completes the switching of the receiving end power consumption state according to the clock signal sent by the sending end under the control of the first enable signal, which can be specifically set by those skilled in the art according to needs and actual conditions.

[0071] It should be noted that, in the present embodiment, the power consumption control device 10 can be arranged inside the transmitting end of the high-speed interconnection interface as a part of the transmitting end of the high-speed interconnection interface. Of course, part or all of the components of the power consumption control device 10 can also be arranged separately outside the transmitting end of the high-speed interconnection interface, and there is no specific limitation on this.

[0072] Accordingly, this embodiment further provides a power consumption control method, which is applied to the power consumption control device described in this embodiment. The method includes:

[0073] When the high-speed interconnect interface needs to enter a low-power state, the interface power management state machine controls the transmitting end to enter a low-power state and inputs a first enable signal to the clock gating unit; when the high-speed interconnect interface needs to exit the low-power state, the interface power management state machine controls the transmitting end to exit the low-power state and inputs a second enable signal to the clock gating unit;

[0074] The clock gating unit controls the closing and opening of the transmission of the local clock signal of the sending end through the first enable signal and the second enable signal, so that the sending end performs the following operations: sends the local clock signal of the sending end controlled by the clock gating unit to the receiving end through the clock transmission channel, and sends data to the receiving end through the data transmission channel based on the local clock signal of the sending end controlled by the clock gating unit.

[0075] As a preferred implementation, the method further includes: the interface power consumption management state machine determines that the high-speed interconnect interface needs to enter or exit a low power consumption state according to the power consumption requirement of the upper layer protocol.

[0076] Exemplarily, the interface power consumption management state machine controls the transmitting end of the high-speed interconnect interface to enter a low power consumption state, including: waiting for a preset time after inputting a first enable signal to the clock gating unit, and controlling the transmitting end of the high-speed interconnect interface to enter a low power consumption state after the waiting ends.

[0077] The power consumption control device and the power consumption control method provided in this embodiment belong to the same inventive concept. For technical details not described in the power consumption control method of this embodiment, reference can be made to the relevant description in the aforementioned power consumption control device, which will not be repeated here.

[0078] Embodiment 2

[0079] The embodiment of the present invention provides a high-speed interconnect interface receiving end side device, see Figure 2a The receiving end side device includes a power consumption control device 20 and a receiving end (including a data receiving module 21 and a clock receiving module 22) arranged at the receiving end side of the high-speed interconnect interface. The power consumption control device 20 includes a receiving end power consumption control unit 201, which is used to:

[0080] Detecting the presence or absence of a sending end clock signal received by a receiving end (specifically, a clock receiving module 22) of the high-speed interconnect interface through a clock transmission channel;

[0081] According to the detection results, the receiving end of the high-speed interconnection interface (specifically the data receiving module 21) is controlled to enter or exit the low power consumption state, wherein the receiving end of the high-speed interconnection interface (specifically the data receiving module 21) processes the sending end data received through the data transmission channel based on the sending end clock signal.

[0082] Exemplarily, the receiving end power consumption control unit 201 is used to control the receiving end of the high-speed interconnect interface to enter or exit a low power consumption state according to the detection result, including:

[0083] After detecting that the received sending end clock signal changes from being present to being absent, outputting a first control signal to control the data receiving enable end of the receiving end of the high-speed interconnect interface to be invalid;

[0084] After detecting that the received sending end clock signal changes from non-existence to existence, a second control signal is output to control the data receiving enable end of the receiving end of the high-speed interconnect interface to be effective.

[0085] Among them, the two control signals output by the receiving end power consumption control unit 201 can be distinguished by the level of the level signal voltage, which depends on the requirements for the level signal voltage when the data receiving enable end is valid or invalid. For example: when the data receiving enable end is a low level signal and is invalid, the receiving end power consumption control unit 201 outputs a low level signal as the first control signal to the data receiving enable end; when the data receiving enable end has a high level signal and is valid, the receiving end power consumption control unit 201 outputs a high level signal as the second control signal to the data receiving enable end. The data receiving enable end can be set in the receiving end (specifically the data receiving module 21). When the enable end is valid, the receiving end (specifically the data receiving module 21) performs the data reception of the sending end. Otherwise, when the enable end is invalid, the receiving end (specifically the data receiving module 21) stops the data reception of the sending end.

[0086] For the above-mentioned receiving end power consumption control unit 201, the empty signal output principle of the existing asynchronous FIFO memory can be reused to realize the function of the unit. Specifically, the receiving end power consumption control unit 201 includes: a write clock signal terminal, which inputs the received sender clock signal; a read clock signal terminal, which inputs the receiving end local clock control signal; an empty signal terminal, which outputs an empty signal as the first control signal or the second control signal; wherein,

[0087] After the received sending end clock signal changes from being present to being absent, the write pointer stops counting, and the read pointer continues to increase under the drive of the read clock until the read and write pointers are equal, and the receiving end power consumption control unit 201 is read empty, and the output signal is used as the empty signal of the first control signal, and the empty signal is synchronized to the read clock domain by the synchronizer for read pointer control;

[0088] After the received sending end clock signal increases from zero to one, the write pointer starts counting, and the read pointer starts counting when the control signal output by the synchronizer becomes valid. If the read and write pointers are not equal, a null signal is output as the second control signal.

[0089] It should be noted that the principle of outputting an empty signal under the action of the read clock, write clock, read pointer and write pointer in the above-mentioned receiving end power consumption control unit 201 is similar to the principle of outputting an empty signal under the action of the read clock, write clock, read pointer and write pointer in the existing asynchronous FIFO memory, and will not be described in detail here.

[0090] In the above description, the power consumption control device 20 provided in this embodiment also includes a synchronizer 202, which is used to synchronize the empty signal output by the receiving end power consumption control unit 201 to the read clock domain to control the read pointer. Specifically, the synchronizer 202 can be designed by a delay circuit. Preferably, the synchronizer 202 includes at least one level of D flip-flop, wherein when the D flip-flop is cascaded in multiple stages, in the signal end of the cascaded D flip-flop:

[0091] The input terminal D of the first-stage D flip-flop is connected to a high level; the input terminal D of the next-stage D flip-flop is connected to the output terminal Q of the previous-stage D flip-flop; the output terminal Q of the last-stage D flip-flop is connected to the read enable terminal of the receiving-end power consumption control unit 201;

[0092] The signal input to the clock terminal Clk of each level of trigger is obtained according to the local clock signal of the receiving end, and the reset terminal Reset is connected to the empty signal terminal of the power consumption control unit 201 of the receiving end.

[0093] The number of cascaded D flip-flops in the synchronizer can be designed by a person skilled in the art according to a compromise between the depth of the receiving-end power consumption control unit 201 , the clock frequency difference, and the switching time. Figure 2b The synchronizer provided in the second embodiment is composed of two stages of D flip-flops.

[0094] It should be noted that when the number of D flip-flops in the synchronizer 202 is multiple, the clock terminal Clk of each D flip-flop can be directly connected to the output terminal of the local clock of the receiving end, that is, the clock input signals of each D flip-flop are all the same-phase local clock signals of the receiving end. Of course, it can also be that the clock terminal Clk of the D flip-flop of the next stage is inverse to the clock terminal Clk of the D flip-flop of the previous stage. In addition, the clock signal input into the synchronizer 202 and the receiving end local clock control signal input into the receiving end power consumption control unit 201 are independent of each other. Although both are generated by the local clock of the receiving end, they can have different frequencies.

[0095] It should be noted that, in the present embodiment, the power consumption control device 20 can be arranged inside the receiving end of the high-speed interconnection interface as a part of the receiving end of the high-speed interconnection interface. Of course, part or all of the components of the power consumption control device 10 can also be separately arranged outside the receiving end of the high-speed interconnection interface, and there is no specific limitation on this.

[0096] The signal timing relationship of the power consumption control device at the receiving end in this embodiment is as follows: Figure 2c As shown, see Figure 2c :

[0097] The clock signal of the transmitting end received by the receiving end of the high-speed interconnect interface is used as the write clock input of the FIFO of the power consumption control device, and the clock control signal generated by the local clock is used as the read clock input of the power consumption control device;

[0098] When the clock signal of the transmitting end received by the receiving end of the high-speed interconnect interface changes from being present to being absent, writing stops, and the reading clock will read the power control device empty. Once the power control device is empty, the read and write pointers are equal, and the empty signal output end of the power control device will be pulled low, thereby controlling the receiving end to enter a low power consumption state;

[0099] When the receiving end of the high-speed interconnect interface receives the clock signal resent by the sending end, the write pointer of the power control device increases immediately, and the read pointer needs to wait for the read pointer enable signal to be valid before reading. When the read and write pointers are not equal, the empty signal output end of the power control device will be pulled high, thereby controlling the receiving end to exit the low power state;

[0100] The signal synchronized by the synchronizer at the receiving end of the high-speed interconnect interface is delayed for a period of time compared to the signal at the output end of the empty signal, and is used to enable the read pointer.

[0101] Accordingly, this embodiment further provides a power consumption control method, which is applied to the power consumption control device described in this embodiment. The method includes:

[0102] Detecting the presence or absence of a clock signal from a transmitting end received by a receiving end of a high-speed interconnect interface through a clock transmission channel;

[0103] According to the detection result, the receiving end of the high-speed interconnect interface is controlled to enter or exit the low power consumption state, wherein the receiving end of the high-speed interconnect interface processes the transmitting end data received through the data transmission channel based on the transmitting end clock signal. Exemplarily, according to the detection result, the receiving end of the high-speed interconnect interface is controlled to enter or exit the low power consumption state, including:

[0104] After detecting that the received sending end clock signal changes from being present to being absent, outputting a first control signal to control the data receiving enable end of the receiving end of the high-speed interconnect interface to be invalid;

[0105] After detecting that the received sending end clock signal changes from non-existence to existence, a second control signal is output to control the data receiving enable end of the receiving end of the high-speed interconnect interface to be effective.

[0106] On the basis of the above embodiment 1 and embodiment 2, the embodiment of the present invention further provides a power consumption control device, including: the power consumption control device provided at the transmitting end side of the high-speed interconnection interface in the above embodiment 1, and the power consumption control device provided at the receiving end side of the high-speed interconnection interface in the above embodiment 2. The power consumption control devices on both sides of the transmitting and receiving ends work together to complete the low power consumption state switching of the entire system of the high-speed interconnection interface.

[0107] Embodiment 3

[0108] The embodiment of the present invention provides a high-speed interconnection interface, which includes: a transmitting end, a receiving end, a data transmission channel and a clock transmission channel connecting the transmitting and receiving ends; and the power consumption control device provided in the above embodiment 1 and the power consumption control device provided in the above embodiment 2. Of course, the power consumption control device provided in the embodiment 1 can also be built in the transmitting end, and the power consumption control device provided in the embodiment 2 can also be built in the receiving end.

[0109] In specific implementation, the high-speed interconnect interface is a chiplet interconnect interface, and the interface structure is as follows: Figure 3 As shown, it specifically includes the following components.

[0110] 1. Transmitter side

[0111] (1) Data sending module, including:

[0112] A first asynchronous FIFO memory 301 is used to store the data of the transmitting end, wherein the write clock signal terminal of the first asynchronous FIFO memory 301 inputs the local clock signal of the transmitting end, and the read clock signal terminal inputs the clock signal output by the data serial-to-parallel converter 302;

[0113] The data serial-to-parallel converter 302 is connected to the first asynchronous FIFO memory 301, the data transmitter 303 and the clock gating unit 308 of the first power consumption control device, respectively, and is used to: read the transmitting end data in the first asynchronous FIFO memory 301, and output the data to the data transmitter 303 after performing serial-to-parallel conversion; and output the clock signal output by the clock gating unit 308 to the first asynchronous FIFO memory 301 after performing serial-to-parallel conversion;

[0114] The data transmitter 303 is connected to the data transmission channel and is used to drive the data transmission channel to send the serial-to-parallel converted data of the transmitting end to the receiving end of the high-speed interconnection interface through the data transmission channel;

[0115] (2) Clock sending module, including:

[0116] The adjustment unit 304 is connected to the clock gating unit 308 and is used to perform frequency multiplication and phase modulation on the local clock signal of the sending end and then output it to the clock gating unit 308;

[0117] The clock serial-to-parallel converter 305 is connected to the clock gating unit 308 and the clock transmitter 306 respectively, and is used to perform serial-to-parallel conversion on the clock signal output by the clock gating unit 308 and output it to the clock transmitter 306;

[0118] The clock transmitter 306 is used to drive the clock transmission channel to send the serial-to-parallel converted clock signal to the receiving end of the high-speed interconnect interface through the clock transmission channel.

[0119] (3) A first power consumption control device, comprising:

[0120] The interface power consumption management state machine 307 is used to: when the high-speed interconnect interface needs to enter a low power consumption state, control the data transmitter 303 at the transmitting end to enter a low power consumption state, and input a first enable signal to the clock gating unit 308; when the high-speed interconnect interface needs to exit the low power consumption state, control the data transmitter 303 at the transmitting end to exit the low power consumption state, and input a second enable signal to the clock gating unit 308;

[0121] The clock gating unit 308 is used to control the closing and opening of the transmission of the local clock signal of the sending end through the first enable signal and the second enable signal, so that the clock serial-to-parallel converter 305 of the sending end sends the local clock signal of the sending end controlled by the clock gating unit 308 to the receiving end of the high-speed interconnection interface through the clock transmission channel, and the data serial-to-parallel converter 302 of the sending end sends the data to the receiving end of the high-speed interconnection interface through the data transmission channel based on the local clock signal of the sending end controlled by the clock gating unit 308.

[0122] Among them, the first power consumption control device in this embodiment is the same as the power consumption control device provided in the first embodiment. For technical details not fully described in this embodiment, please refer to the relevant description in the first embodiment.

[0123] 2. Receiver Side

[0124] (1) Data receiving module

[0125] A data receiver 311 is used to drive the data transmission channel and receive the data from the sending end;

[0126] The data clock serial-to-parallel converter 312 is connected to the clock receiver 314, the data receiver 311 and the second asynchronous FIFO memory 313 respectively, and is used to perform serial-to-parallel conversion on the sending end clock signal received by the clock receiver 314 and the sending end data received by the data receiver 311, and output them to the second asynchronous FIFO memory 313;

[0127] The second asynchronous FIFO memory 313 is used to synchronize the data of the transmitting end after the serial-to-parallel conversion by the data clock serial-to-parallel converter 312 to the local clock of the receiving end to complete the clock domain conversion, wherein the write clock signal end inputs the clock signal output by the data clock serial-to-parallel converter 312, and the read clock signal end inputs the local clock signal of the receiving end;

[0128] (2) Clock receiving module

[0129] The clock receiver 314 is connected to the receiving end power consumption control unit 315 and the data clock serial-to-parallel converter 312, and is used to drive the clock transmission channel, receive the clock signal sent by the sending end of the high-speed interconnection interface, and output it to the receiving end power consumption control unit 315 and the data clock serial-to-parallel converter 312.

[0130] (3) Second power consumption control device

[0131] The receiving end power consumption control unit 315 is used to: detect the presence or absence of the sending end clock signal received by the receiving end of the high-speed interconnect interface through the clock transmission channel; and control the receiving end data receiver 311 to enter or exit the low power consumption state according to the detection result.

[0132] In specific implementation, the receiving end power consumption control unit 315 outputs a first control signal to control the enable end of the data receiver 311 of the receiving end to be invalid after detecting that the clock signal of the transmitting end received by the clock receiver 314 of the receiving end changes from presence to absence; and outputs a second control signal to control the enable end of the data receiver 311 of the receiving end to be valid after detecting that the clock signal of the transmitting end received changes from absence to presence.

[0133] Exemplarily, the receiving end power consumption control unit 315 includes: a write clock signal terminal, which inputs the sending end clock signal received by the clock receiver 314 of the receiving end; a read clock signal terminal, which inputs the receiving end local clock control signal; and an empty signal terminal, which outputs an empty signal as the first control signal or the second control signal; wherein,

[0134] After the received sending end clock signal changes from being present to being absent, the write pointer stops counting, and the read pointer continues to increase under the drive of the read clock until the read and write pointers are equal, and the receiving end power consumption control unit 201 is read empty, and the output signal is used as the empty signal of the first control signal, and the empty signal is synchronized to the read clock domain by the synchronizer for read pointer control;

[0135] After the received sending end clock signal increases from zero to one, the write pointer starts counting, and the read pointer starts counting when the control signal output by the synchronizer becomes valid. If the read and write pointers are not equal, a null signal is output as the second control signal.

[0136] Furthermore, the second power consumption control device also includes a synchronizer 316, which is used to synchronize the null signal output by the receiving end power consumption control unit 315 to the read clock domain to control the read pointer.

[0137] Among them, the second power consumption control device in this embodiment is the same as the power consumption control device provided in the second embodiment. For technical details not fully described in this embodiment, please refer to the relevant description in the second embodiment.

[0138] It should be noted that the data serial-to-parallel converter 302 on the transmitting end and the data clock serial-to-parallel converter 312 on the receiving end process the data as a pair of inverse operations. If the data serial-to-parallel converter 302 converts the data from serial to parallel, then the data clock serial-to-parallel converter 312 converts the data from parallel to serial. If the data serial-to-parallel converter 302 converts the data from parallel to serial, then the data clock serial-to-parallel converter 312 converts the data from serial to parallel. Similarly, the clock serial-to-parallel converter 305 on the transmitting end and the data clock serial-to-parallel converter 312 on the receiving end process the clock signal as a pair of inverse operations: one is the conversion from serial to parallel, and the other is the conversion from parallel to serial. Moreover, on the same side, the serial-to-parallel conversion operation of the data and clock signals is the same conversion operation, either the conversion from serial to parallel, or the conversion from parallel to serial.

[0139] The timing relationship between signals in high-speed interconnect interfaces is as follows: Figure 4 As shown, see Figure 4 :

[0140] When the local clock signal of the transmitting end changes from being present to being absent under the control of the clock gating unit, the data transmitter stops sending data after waiting for a preset period of time, and the transmitting end enters a low-power state. In this state, the clock transmission channel transmits differential zero, and the data transmission channel transmits zero; the power consumption control unit of the receiving end determines that the clock signal received from the transmitting end changes from being present to being absent, and immediately controls the data receiver to stop receiving data, and the receiving end enters a low-power state, and the synchronizer delays the empty signal output by the power consumption control unit of the receiving end for a period of time;

[0141] Subsequently, when the local clock signal of the transmitting end changes from none to present after being controlled by the clock gating unit, the data transmitter starts to prepare to send data, and the transmitting end immediately exits the low power state. In this state, the transmission differential of the clock transmission channel is no longer zero, and the data transmission channel transmission is no longer zero; the power consumption control unit of the receiving end determines that the clock signal received from the transmitting end changes from none to present, and immediately exits the low power state, and the synchronizer delays the empty signal output by the power consumption control unit of the receiving end for a period of time.

[0142] Among them, when it is necessary to enter the low-power state, the receiving end immediately enters the low-power state after detecting that the received clock signal of the sending end changes from being present to being absent, while the sending end needs to wait for a preset period of time before entering the low-power state to meet the requirement that the receiving end stops receiving data first and then the sending end stops sending data. When it is necessary to exit the low-power state, the sending end immediately enters the low-power state under the control of the clock gating unit, and because the clock signal of the sending end is transmitted on the clock transmission channel and processed inside the receiving end power control unit, it takes time, so the receiving end will exit the low-power state with a delay compared to the sending end. Therefore, the state switching is that the sending end starts preparing for data transmission first and then the receiving end starts preparing for receiving data.

[0143] Different from the traditional interconnection interface, in the high-speed interconnection interface proposed in the embodiment of the present invention, a clock gating unit and a power consumption control device are added on the transmitting end side, and another power consumption control device is added on the receiving end side. Under this structure, the transmitting and receiving ends transmit clock signals with power consumption requirement information based on the existing clock transmission channel, thereby performing corresponding power consumption state switching, which can achieve a power consumption state switching time of ns level.

[0144] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0145] In the embodiments of the present invention, the term "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0146] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0147] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A power consumption control device, characterized in that: The device is arranged at the transmitting end side of the high-speed interconnect interface, and comprises: The interface power consumption management state machine is used to: when the high-speed interconnect interface needs to enter a low-power consumption state, control the transmitting end of the high-speed interconnect interface to enter a low-power consumption state, and input a first enable signal to the clock gating unit; when the high-speed interconnect interface needs to exit the low-power consumption state, control the transmitting end of the high-speed interconnect interface to exit the low-power consumption state, and input a second enable signal to the clock gating unit; The clock gating unit is used to control the closing and opening of the transmission of the local clock signal of the sending end of the high-speed interconnection interface through the first enable signal and the second enable signal, so that the sending end of the high-speed interconnection interface performs the following operations: sending the local clock signal of the sending end controlled by the clock gating unit to the receiving end through the clock transmission channel, and sending data to the receiving end through the data transmission channel based on the local clock signal of the sending end controlled by the clock gating unit; The controlling the transmitting end of the high-speed interconnect interface to enter a low power consumption state comprises: waiting for a preset time after inputting a first enable signal to the clock gating unit, and controlling the transmitting end of the high-speed interconnect interface to enter a low power consumption state after the waiting ends.

2. The device according to claim 1, characterized in that The interface power consumption management state machine is also used to determine whether the high-speed interconnect interface needs to enter or exit a low power consumption state according to the power consumption requirements of the upper layer protocol.

3. A power consumption control device, characterized in that: Set at the receiving side of the high-speed interconnect interface, the device includes a receiving end power consumption control unit, which is used to: Detecting the presence or absence of a clock signal from a transmitting end received by a receiving end of a high-speed interconnect interface through a clock transmission channel; Controlling the receiving end of the high-speed interconnect interface to enter or exit a low power consumption state according to the detection result, wherein the receiving end of the high-speed interconnect interface processes the sending end data received through the data transmission channel based on the sending end clock signal; The receiving end power consumption control unit is specifically used for, after the received sending end clock signal changes from being present to being absent, the write pointer stops counting, and the read pointer continues to increase under the drive of the read clock until the read and write pointers are equal, the receiving end power consumption control unit is read empty, and the output signal is used as the empty signal of the first control signal, and the empty signal is synchronized by the synchronizer to the read clock domain for read pointer control; After the received sending end clock signal increases from zero to one, the write pointer starts counting, and the read pointer starts counting when the control signal output by the synchronizer becomes valid. If the read and write pointers are not equal, a null signal is output as the second control signal.

4. The device according to claim 3, characterized in that The receiving end power consumption control unit is used to control the receiving end of the high-speed interconnect interface to enter or exit a low power consumption state according to the detection result, including: After detecting that the received sending end clock signal changes from being present to being absent, outputting a first control signal to control the data receiving enable end of the receiving end of the high-speed interconnect interface to be invalid; After detecting that the received sending end clock signal changes from non-existence to existence, a second control signal is output to control the data receiving enable end of the receiving end of the high-speed interconnect interface to be effective.

5. The device according to claim 3, characterized in that The receiving end power consumption control unit also includes a synchronizer for synchronizing the empty signal output by the receiving end power consumption control unit to the read clock domain to control the read pointer. The read pointer can only change when the synchronizer output signal is high.

6. The device according to claim 5, characterized in that The synchronizer includes at least one stage of D flip-flops, wherein when the D flip-flops are cascaded in multiple stages, at the signal end of the cascaded D flip-flops: The input terminal D of the first-stage D flip-flop is connected to a high level; the input terminal D of the next-stage D flip-flop is connected to the output terminal Q of the previous-stage D flip-flop; the output terminal Q of the last-stage D flip-flop is connected to the read enable terminal of the receiving-end power consumption control unit; The signal inputted by the clock terminal Clk of each level of trigger is obtained according to the local clock signal of the receiving end, and the reset terminal Reset is connected to the empty signal terminal of the power consumption control unit of the receiving end.

7. A power consumption control device, characterized in that: include: The power consumption control device as described in any one of claims 1 to 2 above; as well as A power consumption control device as described in any one of claims 3 to 6 above.

8. A high-speed interconnect interface, characterized in that: include: Sending end; Receiver; A data transmission channel and a clock transmission channel connecting the transmitting end and the receiving end; And, the power consumption control device as described in claim 7.

9. The interface according to claim 8, characterized in that: The sending end comprises: A first asynchronous FIFO memory, used for storing data from the transmitting end, wherein a write clock signal terminal of the first asynchronous FIFO memory inputs a local clock signal from the transmitting end, and a read clock signal terminal inputs a clock signal output by a data serial-to-parallel converter; A data serial-to-parallel converter is connected to the first asynchronous FIFO memory, the data transmitter and the clock gating unit respectively, and is used to: read the transmitting end data in the first asynchronous FIFO memory, and perform serial-to-parallel conversion on the data and then output it to the data transmitter; perform serial-to-parallel conversion on the clock signal output by the clock gating unit and then output it to the first asynchronous FIFO memory; A data transmitter is connected to the data transmission channel and is used to drive the data transmission channel to send the serial-to-parallel converted data from the transmitting end to the receiving end of the high-speed interconnection interface through the data transmission channel; The adjustment unit is connected to the clock gating unit and is used to perform frequency multiplication and phase modulation on the local clock signal of the sending end and then output it to the clock gating unit; A clock serial-to-parallel converter, connected to the clock gating unit and the clock transmitter respectively, for performing serial-to-parallel conversion on the clock signal output by the clock gating unit and outputting the converted signal to the clock transmitter; The clock transmitter is used to drive the clock transmission channel and send the serial-to-parallel converted clock signal to the receiving end of the high-speed interconnect interface through the clock transmission channel.

10. The interface according to claim 8, characterized in that: The receiving end comprises: A data receiver, used to drive the data transmission channel and receive the data from the sender; A data clock serial-to-parallel converter is connected to the clock receiver, the data receiver and the second asynchronous FIFO memory respectively, and is used to: perform serial-to-parallel conversion on the sending end clock signal received by the clock receiver and the sending end data received by the data receiver, and output them to the second asynchronous FIFO memory; A second asynchronous FIFO memory is used to synchronize the data of the transmitting end after the serial-to-parallel conversion by the data clock serial-to-parallel converter to the local clock of the receiving end to complete the clock domain conversion, wherein the write clock signal terminal of the second asynchronous FIFO memory inputs the clock signal output by the serial-to-parallel converter, and the read clock signal terminal inputs the local clock signal of the receiving end; The clock receiver is connected to the receiving end power consumption control unit and the data clock serial-to-parallel converter, and is used to drive the clock transmission channel, receive the clock signal sent by the transmitting end of the high-speed interconnection interface, and output it to the receiving end power consumption control unit and the data clock serial-to-parallel converter.

11. The interface according to claim 8, characterized in that: The interface is a chiplet interconnection interface.

12. A power consumption control method, applied to the power consumption control device according to any one of claims 1 to 2, characterized in that: The method comprises: When the high-speed interconnect interface needs to enter a low-power state, the interface power management state machine controls the transmitting end of the high-speed interconnect interface to enter a low-power state and inputs a first enable signal to the clock gating unit; when the high-speed interconnect interface needs to exit the low-power state, the interface power management state machine controls the transmitting end of the high-speed interconnect interface to exit the low-power state and inputs a second enable signal to the clock gating unit; The clock gating unit controls the closing and opening of the transmission of the local clock signal of the sending end through the first enable signal and the second enable signal, so that the sending end of the high-speed interconnection interface performs the following operations: sending the local clock signal of the sending end controlled by the clock gating unit to the receiving end of the high-speed interconnection interface through the clock transmission channel, and sending data to the receiving end of the high-speed interconnection interface through the data transmission channel based on the local clock signal of the sending end controlled by the clock gating unit; The interface power management state machine controls the transmitter of the high-speed interconnect interface to enter a low power state, including: After the first enable signal is input to the clock gating unit, a preset time period is waited, and after the waiting period is over, the sending end of the high-speed interconnect interface is controlled to enter a low power consumption state.

13. The method according to claim 12, characterized in that The method further comprises: The interface power management state machine determines whether the high-speed interconnect interface needs to enter or exit a low power state according to the power consumption requirements of the upper layer protocol.

14. A power consumption control method, applied to the power consumption control device according to any one of claims 3 to 6, characterized in that: The method comprises: Detecting the presence or absence of a clock signal from a transmitting end received by a receiving end of a high-speed interconnect interface through a clock transmission channel; Controlling the receiving end of the high-speed interconnect interface to enter or exit a low power consumption state according to the detection result, wherein the receiving end of the high-speed interconnect interface processes the sending end data received through the data transmission channel based on the sending end clock signal; The detecting whether the sending end clock signal received by the receiving end of the high-speed interconnect interface through the clock transmission channel is present includes: after the received sending end clock signal changes from present to absent, the write pointer stops counting, and the read pointer continues to increase under the drive of the read clock until the read and write pointers are equal, the receiving end power consumption control unit is read empty, and the output signal is used as the empty signal of the first control signal, and the empty signal is synchronized by the synchronizer to the read clock domain for read pointer control; After the received sending end clock signal increases from zero to one, the write pointer starts counting, and the read pointer starts counting when the control signal output by the synchronizer becomes valid. If the read and write pointers are not equal, a null signal is output as the second control signal.

15. The method according to claim 14, characterized in that Controlling the receiving end of the high-speed interconnect interface to enter or exit a low power consumption state according to the detection result, including: After detecting that the received sending end clock signal changes from being present to being absent, outputting a first control signal to control the data receiving enable end of the receiving end of the high-speed interconnect interface to be invalid; After detecting that the received sending end clock signal changes from non-existence to existence, a second control signal is output to control the data receiving enable end of the receiving end of the high-speed interconnect interface to be effective.

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