Distributed processing methods and storage media for the layout

Abstract

This invention discloses a distributed processing method and storage medium for a layout. The distributed processing method includes: dividing the layout into multiple blocks and coloring them, and assigning priorities; processing the blocks according to their priorities from highest to lowest, with different blocks of the same priority assigned to different dynamic processing (DP) tasks for parallel processing; obtaining the processing time of each block; searching for mergeable blocks according to their priorities from highest to lowest, where a mergeable block is defined as one block where the sum of the processing times of two adjacent blocks and the lower-priority blocks between them is less than or equal to the maximum processing time of the current-priority block; and merging these three blocks into a single block of the current priority. After all priorities have been searched, the next iteration is performed until a preset termination condition is met. This invention allows for dynamic coloring, reducing CPU idle time during computation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a distributed processing method for a layout. Background Technology

[0002] To transfer a pattern from a photomask to the surface of a silicon wafer, the process typically involves an exposure step, a development step following the exposure step, and an etching step following the development step. In the exposure step, light passes through the light-transmitting areas of the photomask and shines onto the silicon wafer coated with photoresist, causing a chemical reaction in the photoresist. In the development step, the different solubility of the developer in the photoresist and the unphotoresisted photoresist creates a photolithographic pattern, transferring the pattern from the photomask to the photoresist. In the etching step, the silicon wafer is etched based on the photolithographic pattern formed by the photoresist layer, further transferring the pattern from the photomask onto the silicon wafer.

[0003] In semiconductor manufacturing, as design dimensions continue to shrink and approach the limits of photolithography imaging systems, the diffraction effect of light becomes increasingly pronounced, leading to optical image degradation of the final design pattern. The actual photolithographic pattern formed is severely distorted relative to the pattern on the mask, resulting in a difference between the actual pattern formed on the silicon wafer and the design pattern. This phenomenon is called the Optical Proximity Effect (OPE).

[0004] To correct for the optical proximity effect, Optical Proximity Correction (OPC) was developed. The core idea of ​​OPC is to establish an OPC model based on the consideration of counteracting the optical proximity effect. The photomask pattern is then designed according to this model. Although the lithographic pattern exhibits an optical proximity effect relative to the corresponding photomask pattern, this effect is already considered when designing the photomask pattern based on the OPC model. Therefore, the lithographic pattern is close to the target pattern actually desired by the user. Currently, mainstream technology nodes (65nm and below manufacturing processes) use model-based OPC correction.

[0005] The OPC correction first uses Hopkin's equation to perform an optical simulation of the photomask, obtaining an aerial image of the light intensity distribution in the air. Then, a compact model of the photoresist is used to transform this aerial light intensity distribution into a resist image of the photoresist. Since the photoresist is washed away by the developer, the simulated pattern (contour) of the layout can be directly obtained from the resist image. The size of the entire layout can sometimes reach the centimeter scale, consuming far more computational resources than a single CPU; therefore, distributed computing is required to process the entire layout.

[0006] Specifically, the entire map is first divided into tiles, and all tiles are colored with four different colors. Tiles are processed sequentially according to their priority to complete one iteration. This traditional distributed processing method suffers from inefficiency. Assuming color-0 has a higher priority than color-1, when processing a color-0 tile, all color-0 tiles are processed in parallel; however, color-1 tiles cannot be processed until all color-1 tiles are completed. Ideally, all color-0 tiles should complete almost simultaneously. However, in practice, the following situation may occur: the CPU time required for some color-0 tiles far exceeds the time required for most other tiles. Because color-1 tiles can only be processed after all color-0 tiles are completed, a large amount of CPU time is idle, resulting in a significant waste of computing resources. Summary of the Invention

[0007] To address the technical problem of wasted CPU resources encountered during OPC correction processing of layouts in existing technologies, this invention proposes a distributed processing method and storage medium for layouts.

[0008] The distributed processing method for layout proposed in this invention includes:

[0009] Step 1: Divide the map into multiple blocks;

[0010] Step 2: Color all blocks;

[0011] Step 3: Define different priorities based on the different colors of the blocks;

[0012] Step 4: Process the blocks in order of priority from high to low, and different blocks of the same priority are assigned to different DP tasks for parallel processing.

[0013] Step 5: Obtain the processing time required for each block;

[0014] Step 6: Search for mergeable blocks in descending order of priority. A mergeable block is one where the sum of the processing times of two adjacent blocks and the blocks between them with lower priorities is less than or equal to the maximum processing time of the current priority block. In this case, the priorities of the two adjacent blocks and the blocks between them are merged into one block of the current priority. After all priorities have been searched, return to step 4 until the preset termination condition is met.

[0015] Furthermore, the size range of the blocks is 15-50 micrometers.

[0016] Furthermore, the priority of the blocks is defined by varying from high to low based on the color values ​​from low to high.

[0017] Furthermore, the preset termination condition is reaching a preset number of iterations or reaching the convergence target of the layout.

[0018] Furthermore, when coloring all blocks, the color of the blocks surrounding each block is different from that of the block itself.

[0019] The present invention proposes a computer-readable storage medium for storing a computer program, wherein the computer program executes the distributed processing method of the layout described in the above technical solution when it runs.

[0020] In each iteration of the layout segmentation process, the present invention dynamically adjusts the CPU and priority allocated to the segment, so that OPC correction can be completed more efficiently in the next iteration, thereby improving the efficiency of the entire OPC correction process and reducing the OPC turnaround time. Attached Figure Description

[0021] The present invention will now be described in detail with reference to the embodiments and accompanying drawings, wherein:

[0022] Figure 1 This is a flowchart of an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram of the block merging process of the present invention.

[0024] Figure 3 Is Figure 2 This is a diagram illustrating further segmentation and merging based on the existing data. Detailed Implementation

[0025] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0026] Therefore, a feature pointed out in this specification is used to describe one feature of one embodiment of the invention, and does not imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes many features. Although certain features may be combined to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0027] like Figure 1 As shown, the distributed processing method of the layout of the present invention includes the following main steps.

[0028] Step 1: First, divide the layout into multiple blocks. The number and size of the blocks can be adjusted according to the size of the layout, with the block size ranging from 15 to 50 micrometers.

[0029] Step 2: Color all blocks. In one embodiment, the blocks are typically colored with four different colors; however, this invention does not limit the types or number of colors.

[0030] Step 3: Define different priorities based on the different colors of the blocks. In one embodiment, the priority of blocks can be defined from high to low according to the color value from low to high. In other embodiments, the priority of blocks with different color values ​​can be arbitrarily defined based on different color values.

[0031] Step 4: Process the blocks according to their priority from highest to lowest, with different blocks of the same priority assigned to different DP (Distributed Processing) tasks for parallel processing. Taking blocks colored with four colors as an example, the highest priority blocks are processed first, followed by the next highest priority blocks, and so on, until all four colors have been processed in four batches of parallel processing. At this point, one round of parallel processing is complete. However, the layout correction may not yet meet the requirements. To improve the efficiency of the next round of iteration, steps 5 and 6 are required.

[0032] Step 5: Obtain the processing time required for each block;

[0033] Step 6: Search for mergeable blocks in descending order of priority. A mergeable block is one where the sum of the processing times of two adjacent blocks and the blocks between them with lower priorities is less than or equal to the maximum processing time of the current priority block. In this case, the priorities of the two adjacent blocks and the blocks between them are merged into one block of the current priority. After all priorities have been searched, return to step 4 until the preset termination condition is met.

[0034] In one embodiment, the preset termination condition can be reaching a preset number of iterations or reaching the convergence target of the layout, at which point the iteration can be terminated.

[0035] In one embodiment, when coloring all blocks, it is necessary to ensure that the colors of the blocks surrounding each block are different from those of the block itself.

[0036] The inventive concept of this invention will be illustrated below with a detailed example.

[0037] The inventive point of this invention lies in the dynamic allocation of the blocks calculated for each parallel processing task.

[0038] In this invention, the two adjacent blocks that can be merged refer to two adjacent blocks of the same color, and adjacent means that there is a block with a different priority between these two blocks.

[0039] This invention merges three eligible blocks, meaning that the same CPU is then used to process the three blocks sequentially. This ensures that blocks with the same priority eventually have the same processing time, avoiding wasted CPU resources. The merged three blocks are referred to as superblocks in the following example. In the next iteration, a superblock is allocated a CPU and its processing time is calculated as a single block, with no difference in resource allocation compared to ordinary blocks. In some extreme embodiments, superblocks may be merged multiple times, containing more than three blocks.

[0040] First, the entire map is divided into tiles of 20-30 micrometers in size, and all tiles are colored with four colors. According to the coloring principles of this invention, Figure 2A block numbered 0 has no blocks numbered 0 in any of its eight surrounding directions, meaning the colors of the blocks surrounding this block are different from its own. Similarly, blocks numbered 1, 2, and 3 also have different numbers of blocks in their eight surrounding directions. The eight directions of a block are top, bottom, left, right, upper left, lower left, upper right, and lower right. When a block has other blocks in all eight directions, it is located in a non-edge region of the map. When a block is located at the edge of the map, it has fewer than eight surrounding blocks, and the colors of these surrounding blocks are different from the colors of the blocks at the edge.

[0041] The tasks processing the tile are assigned priority based on their color value. The smaller the color value, the higher the priority, i.e., color-0 has the highest priority, and the priorities decrease sequentially from color-1 to color-3. Tiles or super-tiles are processed sequentially according to their priority to complete one iteration. Tiles / super-tiles of the same type are processed in parallel, and the computation time required for each tile / super-tile is calculated. If the CPU time required for two adjacent tiles of the same type is so small that the following inequality (referred to as equation (1)) holds, then the corresponding tiles can be merged.

[0042] max(t′i,t″i)+tj≤max(ti) equation (1)

[0043] Here, t′i and t″i are the CPU times required for two adjacent color-I tiles, tj is the CPU time required for other types of tiles to connect two adjacent tiles, and max(ti) is the maximum CPU time required for the same type of color-I tile as the two adjacent tiles mentioned above.

[0044] If these three tiles satisfy the above inequality, the middle tile is colored the same as the two adjacent tiles of the same type / super-tiles, thus forming a super-tile. It is processed on a single CPU just like a regular tile, thereby reducing CPU idle time.

[0045] like Figure 2 As shown, the block labeled 0 is the highest priority block. If the processing time of the two adjacent blocks labeled 0 plus the block labeled 2 between them is less than or equal to the longest processing time of the block labeled 0, then the block labeled 2 can be changed to 0, so that these three blocks are merged into a single block (hereinafter, for distinction, this merged block will be called a superblock).

[0046] Then as Figure 3As shown, the processing time of the circled block labeled 0, plus the processing time of the block labeled 1, is less than or equal to the longest processing time of the block labeled 0. Therefore, the block labeled 1 can be changed to 0, further merging these five blocks into a single block. Assuming there is no further possibility of merging these five blocks, in the next iteration, these five blocks will be allocated to the same CPU for sequential processing, avoiding CPU idle time. Each iteration merges only one level of superblocks; a superblock will not be merged twice in a single iteration. Figure 2 The process shown merges the elements after one iteration, then continues with another iteration before finally merging them. Figure 3 .

[0047] This invention utilizes dynamic coloring and corresponding distributed processing based on the CPU time required for block division. This reduces CPU idle time during OPC operations, thereby saving CPU resources and lowering OPC turnaround time (optical proximity correction).

[0048] The present invention provides a computer-readable storage medium for storing a computer program, which, when executed, performs a distributed processing method based on the layout of the above-described technical solution.

[0049] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A distributed processing method for a map, characterized in that, include: Step 1: Divide the map into multiple blocks; Step 2: Color all blocks so that the color of the blocks surrounding each block is different from that of the block itself. Step 3: Define different priorities based on the different colors of the blocks; Step 4: Process the blocks in order of priority from high to low, and different blocks of the same priority are assigned to different DP tasks for parallel processing. Step 5: Obtain the processing time required for each block; Step 6: Search for mergeable blocks in descending order of priority. A mergeable block meets the following conditions: there are two adjacent blocks of the same color in the current priority block. Adjacent means that there is a block with a different priority between these two blocks. The priority of the block between the two adjacent blocks of the same color is lower than the current priority. Furthermore, the sum of the processing time of the two adjacent blocks and the block between them is less than or equal to the maximum processing time of the current priority block. In this case, the two adjacent blocks and the block between them are merged into a block of the current priority. After all priorities have been searched, return to step 4 until the preset termination condition is met.

2. The distributed processing method for the layout as described in claim 1, characterized in that, The size range of the blocks is 15-50 micrometers.

3. The distributed processing method for the layout as described in claim 1, characterized in that, The priority of the blocks is defined by color values ​​from low to high, and changes from high to low.

4. The distributed processing method for the layout as described in claim 1, characterized in that, The preset termination condition is reaching a preset number of iterations or reaching the convergence target of the layout.

5. A computer-readable storage medium for storing a computer program, characterized in that, When the computer program is executed, it performs the distributed processing method of the layout as described in any one of claims 1 to 4.

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