Trench-type insulated gate field effect transistor and manufacturing method thereof, and electronic component

Abstract

The present disclosure relates to a trench-type insulated gate field effect transistor and a manufacturing method thereof, and an electronic component. The method comprises: forming a patterned protective layer on a composite substrate, and obtaining a first channel and a stacked first dielectric layer and a second dielectric layer, wherein the first dielectric layer, the second dielectric layer and the first channel have a first doping type, the protective layer has a second doping type, the protective layer penetrates the second dielectric layer, and the first channel penetrates the protective layer; forming a third dielectric layer, a channel layer and a first source contact region sequentially arranged along the direction of the second dielectric layer away from the first dielectric layer, wherein the third dielectric layer and the first source contact region have a first doping type, and the channel layer has a second doping type; and forming a gate oxide structure, wherein the gate oxide structure penetrates the first source contact region and the channel layer, and at least extends into the third dielectric layer, and the gate oxide structure is stacked with the protective layer and with the first channel. The method can simply and easily manufacture a trench-type insulated gate field effect transistor, and realize a protective layer nested under the third dielectric layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor devices, and in particular to a trench-type insulated gate field effect transistor and a manufacturing method thereof, and an electronic component. Background Art

[0002] Insulated gate field effect transistors, also known as metal-oxide semiconductor field effect transistors (MOSFET), are used in many fields, such as electric vehicle onboard chargers and electric drive systems, charging piles, photovoltaic micro inverters, high-speed rail, smart grids, industrial-grade power supplies, etc.

[0003] Various planar MOSFET devices can already achieve performance such as high blocking voltage and high switching speed, but due to the existence of junction field effect transistors (JFETs), the specific on-resistance of planar MOSFET devices is not small enough.

[0004] Compared with planar MOSFET devices, trench MOSFET devices do not have a JFET region, so they can reduce both device size and specific on-resistance. However, in high electric field environments, the reliability of trench MOSFET devices is challenged. Summary of the invention

[0005] Based on this, the present disclosure provides a trench-type insulated gate field effect transistor to ensure reliability and reduce specific on-resistance.

[0006] The present disclosure also provides a method for manufacturing a trench-type insulated gate field effect transistor, which can easily and at low cost obtain a trench-type insulated gate field effect transistor with good reliability and low specific on-resistance.

[0007] The present disclosure provides a method for manufacturing a trench-type insulated gate field effect transistor, the method comprising: forming a patterned protective layer on a composite substrate, and obtaining a first channel and a stacked first dielectric layer and a second dielectric layer, wherein the first dielectric layer, the second dielectric layer and the first channel respectively have a first doping type, the protective layer has a second doping type, the protective layer penetrates the second dielectric layer, and the first channel penetrates the protective layer; forming a third dielectric layer, a channel layer and a first source contact region sequentially arranged along a direction of the second dielectric layer away from the first dielectric layer, wherein the third dielectric layer and the first source contact region have a first doping type, and the channel layer has a second doping type; and forming a gate oxide structure, wherein the gate oxide structure penetrates the first source contact region and the channel layer and at least extends into the third dielectric layer, and the gate oxide structure is stacked with the protective layer and with the first channel.

[0008] The method for manufacturing a trench-type insulated gate field effect transistor provided by the embodiment of the present disclosure has simple steps, easy formation of a hierarchical structure, and can obtain a protective layer nested under the third dielectric layer in the stacking direction, so that the protective layer and the first channel can be located on one side of the bottom surface of the gate oxide structure. In addition, the method has low cost and process flow.

[0009] In some embodiments, the method further includes: forming a first channel by ion implantation, wherein a doping concentration of the first channel is greater than or equal to a doping concentration of the first dielectric layer and a doping concentration of the third dielectric layer.

[0010] The method can form a first channel with a higher doping concentration, and then obtain a trench-type insulated gate field effect transistor with low on-resistance.

[0011] In some embodiments, the step of forming the third dielectric layer includes: forming the third dielectric layer by an epitaxial process.

[0012] With such arrangement, the method can form a protective layer first with a relatively simple process, and then form a third dielectric layer having the same lattice structure as the second dielectric layer. The formed third dielectric layer is well combined with the second dielectric layer and can ensure the formation of subsequent structures.

[0013] In some embodiments, the method further includes: forming a second dielectric layer and the first channel by an epitaxial process, wherein a doping concentration of the second dielectric layer is greater than a doping concentration of the first dielectric layer.

[0014] In the method, a current diffusion region wrapping the bottom of the gate oxide structure can be formed, and the formed second dielectric layer can be used as the current diffusion region.

[0015] The embodiment of the present disclosure also provides a trench-type insulated gate field effect transistor, which includes: a first dielectric layer, a second dielectric layer, a third dielectric layer, a channel layer and a first source contact region stacked in sequence, wherein the first dielectric layer, the second dielectric layer, the third dielectric layer and the first source contact region have a first doping type, and the channel layer has a second doping type; a gate oxide structure, which runs through the first source contact region and the channel layer and at least extends into the third dielectric layer; a protective layer, which runs through the second dielectric layer and is stacked with the gate oxide structure, and the protective layer has the second doping type; and at least one first channel, the first channel runs through the protective layer, the first channel has a first doping type and is electrically connected between the first dielectric layer and the third dielectric layer, and the first channel is stacked with the gate oxide structure.

[0016] The trench-type insulated gate field effect transistor provided by the present disclosure can be reliably applied to high voltage use environments and achieves a smaller specific on-resistance. The trench-type insulated gate field effect transistor has excellent comprehensive use performance.

[0017] In some embodiments, the gate oxide structure and the first source contact region are arranged in parallel along a first direction, and at least two first channels are evenly spaced apart along a second direction perpendicular to the stacking direction and perpendicular to the first direction.

[0018] The performance of the trench-type insulated gate field effect transistor is more balanced and stable.

[0019] In some embodiments, a projection of the first channel along the stacking direction has a curved edge.

[0020] The first channel of the curve boundary is actually also the protection layer of the curve boundary, which helps to ensure that the bottom surface of the gate oxide structure can be protected by at least a part of the protection layer along the first direction. The trench-type insulated gate field effect transistor has good comprehensive performance, ensuring low on-resistance while improving reliability.

[0021] In some embodiments, the doping concentration of the first channel is greater than or equal to the doping concentration of the first dielectric layer and the doping concentration of the third dielectric layer.

[0022] The first channel with a higher doping concentration can achieve effects such as lower resistivity, enhanced conductivity and reduced on-resistance.

[0023] In some embodiments, the trench-type insulated gate field effect transistor also includes a second channel, which passes through the second dielectric layer and is located on one side of the protective layer. The second channel has a first doping type, and the doping concentration of the second channel is greater than or equal to the doping concentration of the first dielectric layer and the doping concentration of the third dielectric layer. The second channel is electrically connected to the first channel.

[0024] By providing a second channel with a higher doping concentration, the trench-type insulated gate field effect transistor can achieve the effects of reduced resistivity, enhanced conductivity, and reduced on-resistance.

[0025] In some embodiments, the second dielectric layer, the first channel, and the third dielectric layer are configured as a current diffusion region, and the current diffusion region has a first doping type, and a doping concentration greater than a doping concentration of the first dielectric layer.

[0026] By setting a current diffusion region with a higher doping concentration, the trench-type insulated gate field effect transistor can achieve the effects of reduced resistivity, enhanced conductivity and reduced on-resistance.

[0027] In some embodiments, the gate oxide structure and the first source contact region are arranged in parallel along a first direction, and both ends of the protection layer along the first direction protrude from the gate oxide structure.

[0028] The trench-type insulated gate field effect transistor has good reliability, and the gate oxide structure is well protected.

[0029] The present disclosure provides an electronic component in another aspect, the electronic component comprising: the aforementioned trench-type insulated gate field effect transistor; and a circuit electrically connected to the trench-type insulated gate field effect transistor.

[0030] The electronic component can be used in a high voltage working environment, has high long-term reliability, and realizes low on-resistance and low power consumption. In addition, the manufacturing cost of the electronic component can be low. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a flowchart of a method for manufacturing a trench-type insulated gate field effect transistor in an embodiment of the present disclosure;

[0032] Figure 2 A schematic diagram of the structure of a semiconductor structure after forming a first prefabricated dielectric layer;

[0033] Figure 3 is a schematic structural diagram of a semiconductor structure after a protective layer is formed;

[0034] Figure 4 for Figure 3 Schematic diagram of the cross section at AA in the middle;

[0035] Figure 5 A schematic diagram of the structure of the semiconductor structure after forming the second prefabricated dielectric layer;

[0036] Figure 6 is a schematic structural diagram of a semiconductor structure after a second source contact region is formed;

[0037] Figure 7 is a schematic structural diagram of a semiconductor structure after trenches are formed;

[0038] Figure 8 is a schematic structural diagram of a semiconductor structure after an insulating layer is formed;

[0039] Fig. 9 is a schematic structural diagram of a semiconductor structure after a gate is formed;

[0040] Fig.10 for Fig. 9 a schematic axonometric view of the semiconductor structure shown;

[0041] Fig.11 A schematic cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure;

[0042] Fig.12 A schematic cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure;

[0043] Fig.13 A schematic cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure;

[0044] Fig.14 A schematic cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure;

[0045] Fig.15 A schematic cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure;

[0046] Fig.16 A schematic cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure;

[0047] Fig.17 A schematic cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure;

[0048] Fig.18 A schematic cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure;

[0049] Fig.19 A schematic cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure;

[0050] Fig. 20 A schematic cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure;

[0051] Fig.21 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0052] Fig. 22 for Fig.21 a schematic axonometric view of the semiconductor structure shown;

[0053] Fig.23 for Fig.21 A schematic cross-sectional view of the semiconductor structure shown;

[0054] Fig.24 A structural block diagram of an electronic component provided in an embodiment of the present disclosure.

[0055] Explanation of the accompanying drawings: 1. substrate; 2. first prefabricated dielectric layer; 3. first dielectric layer; 4. second dielectric layer; 5. protective layer; 6. first channel; 6-1. first first channel; 6-2. second first channel; 6-3. third first channel; 6-4. fourth first channel; 7. third dielectric layer; 8. second prefabricated dielectric layer; 9. channel layer; 10. first source contact region; 11. second source contact region; 12. groove; 13. insulating layer; 14. gate; 15. gate oxide structure; 16. second channel; 17. current diffusion region; 100. trench-type insulated gate field effect transistor; 200. circuit; 300. electronic component. DETAILED DESCRIPTION

[0056] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the specific implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the embodiments of the present disclosure. However, the embodiments of the present disclosure can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the embodiments of the present disclosure, so the embodiments of the present disclosure are not limited by the specific examples of the embodiments disclosed below.

[0057] In the description of the embodiments of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present disclosure.

[0058] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. Exemplarily, the first source contact region may also be referred to as the second source contact region, and the second source contact region may also be referred to as the first source contact region. In the description of the embodiments of the present disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0059] In the embodiments of the present disclosure, unless otherwise clearly specified and limited, the terms "connected", "connected", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a flexible connection, or a rigid connection along at least one direction; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly limited. The terms "installed", "set", "fixed", etc. can be broadly understood as connection. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to the specific circumstances.

[0060] In the embodiments of the present disclosure, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0061] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementation method.

[0062] See also Figure 1 , Figure 1 It is a flowchart of a method for manufacturing a trench-type insulated gate field effect transistor in an embodiment of the present disclosure. The method 1000 for manufacturing a trench-type insulated gate field effect transistor provided in an embodiment of the present disclosure includes the following steps.

[0063] Step S101, forming a patterned protective layer. Exemplarily, a patterned protective layer can be formed on a composite substrate, and then a first dielectric layer, a second dielectric layer and a first channel can be obtained based on the composite substrate. It should be understood that the channel in this article refers to a channel for conduction. Exemplarily, along the stacking direction of the first dielectric layer and the second dielectric layer, the protective layer penetrates the second dielectric layer, and the first channel penetrates the protective layer. The first dielectric layer, the second dielectric layer and the first channel have a first doping type respectively, and the protective layer has a second doping type.

[0064] The method 1000 includes the steps of forming a third dielectric layer, a channel layer, and a first source contact region that are sequentially arranged. Specifically, it may include step S102, forming a third dielectric layer; step S103, forming a channel layer; and step S104, forming a first source contact region. Along the direction in which the second dielectric layer is away from the first dielectric layer, the third dielectric layer, the channel layer, and the first source contact region are sequentially arranged. The third dielectric layer and the first source contact region have a first doping type, and the channel layer has a second doping type.

[0065] Step S105 , forming a gate oxide structure. The gate oxide structure penetrates the first source contact region and the channel layer and at least extends into the third dielectric layer. The gate oxide structure is stacked with the protection layer and the first channel.

[0066] The method for manufacturing a trench-type insulated gate field effect transistor provided in the embodiment of the present disclosure can form a protective layer on the side of the third dielectric layer facing the first dielectric layer by forming the first dielectric layer, the second dielectric layer and the third dielectric layer in steps, and can form a first channel. The protective layer can be formed on the composite substrate first, and then the third dielectric layer can be formed on the protective layer, which can avoid the commonly used process of high-energy ion implantation after grooving, reduce the process cost, and avoid the station transfer of the semiconductor structure, shortening the processing time. In addition, the first channel can be formed at the same station, and then a trench-type insulated gate field effect transistor with good reliability and small on-resistance can be manufactured.

[0067] Combination Figures 2 to 10 , a method for manufacturing a trench-type insulated gate field effect transistor provided by an embodiment of the present disclosure is described in detail below.

[0068] Combination Figure 2 As shown, Figure 2 The semiconductor structure after forming the first prefabricated dielectric layer in the embodiment of the present disclosure is shown. In some embodiments, the first prefabricated dielectric layer 2 can be formed on one side of the substrate 1 by epitaxial growth.

[0069] The materials of the substrate 1 and the first prefabricated dielectric layer 2 may include at least one of silicon carbide, silicon, silicon germanium, germanium, and III-V compounds such as gallium nitride and gallium arsenide. Fig.10 ) has a lower specific on-resistance because the gate oxide structure 15 ( Fig.10 ) may be a {1-100} or {11-20} crystal plane, which has a higher mobility than the {0001} crystal plane where the trench of the planar insulated gate field effect transistor is located. The substrate 1 and the first prefabricated dielectric layer 2 may have a first doping type, for example, N-type doping. The doping concentration of the substrate 1 may be higher than the doping concentration of the first prefabricated dielectric layer 2, and the doping type of the substrate 1 may be implemented as N-type heavy doping.

[0070] Figure 3 The semiconductor structure after forming the protective layer is shown. In some embodiments, the protective layer 5 can be formed by ion implanting the first prefabricated dielectric layer 2. At the same time, it can be considered that the first dielectric layer 3 and the second dielectric layer 4 are obtained. The first dielectric layer 3 is located between the protective layer 5 and the substrate 1. The second dielectric layer 4 is parallel to the protective layer 5. In other words, along the Z-axis direction, the protective layer 5 penetrates the second dielectric layer 4. The protective layer 5 has a second doping type, for example, P-type doping. The doping type of the protective layer 5 can be implemented as P-type heavy doping.

[0071] Figure 4 for Figure 3 Schematic diagram of the cross section at AA. Figure 4As shown, exemplarily, the protective layer 5 is a patterned structure, such as a spacer structure, and then the first channel 6 is also obtained in the step of forming the protective layer 5. The first channel 6, the second dielectric layer 4 and the first dielectric layer 3 can be an integrated structure, which is obtained based on the first prefabricated dielectric layer 2 with a first doping type. The first channel 6 can penetrate the protective layer 5 along the Z-axis direction and be electrically connected to the first dielectric layer 3. The first channel 6 can have an overall shape extending along the X-axis direction, such as a rectangle.

[0072] Figure 5 The semiconductor structure after forming the second prefabricated dielectric layer is shown. Exemplarily, the method includes the step of forming a third dielectric layer 7, which can be formed by an epitaxial process to cover the second dielectric layer 4, the protective layer 5 and the first channel 6. The third dielectric layer 7 has a first doping type.

[0073] In some embodiments, the method further comprises the step of forming a second prefabricated dielectric layer 8 on the third dielectric layer 7 by an epitaxial process. The second prefabricated dielectric layer 8 has a second doping type. In other embodiments, a thicker third dielectric layer may be formed, and then a second prefabricated dielectric layer located on the upper layer may be formed by ion implantation.

[0074] Figure 6 1 shows a semiconductor structure after forming the second source contact region. By way of example, by performing ion implantation on different regions of the second prefabricated dielectric layer 8, the first source contact region 10 and the second source contact region 11 can be formed, and the channel layer 9 can be obtained at the same time. The channel layer 9 is located on the third dielectric layer 7, which can be a P-well region. The first source contact region 10 has a first doping type, such as N-type heavy doping; the second source contact region 11 has a second doping type, such as P-type heavy doping. Figure 6 As shown, the semiconductor structure can be roughly mirror-symmetrical, and the symmetry plane is parallel to the YZ plane formed by the Y axis and the Z axis. Therefore, a half-edge structure can be described.

[0075] Figure 7 FIG. 4 shows a semiconductor structure after trench formation. Fig. 9 The step of forming the trench 12 may include: a sub-step of forming the trench 12, for example, etching the trench 12 by inductively coupled plasma etching. The second source contact region 11 is located on a side of the first source contact region 10 away from the trench 12. The trench 12 penetrates the first source contact region 10 and the channel layer 9, such as Figure 7 As shown, the groove 12 may penetrate the third dielectric layer 7 and the bottom surface may expose a portion of the protective layer 5. Along the X-axis direction, the size of the groove 12 may be smaller than the size of the protective layer 5, and both ends of the protective layer 5 may protrude from the groove 12. Exemplarily, at least one end of the protective layer 5 may also be flush with the sidewall surface of the groove 12.

[0076] Understandably, Figure 7 The first channel 6 is located at the interval of the protective layer 5, and the first channel 6 is electrically connected between the first dielectric layer 3 and the third dielectric layer 7. When one end of the protective layer 5 is flush with the sidewall surface of the groove 12, the first channel 6 can be electrically connected to the third dielectric layer 7 through the second dielectric layer 4.

[0077] Figure 8 1 shows a semiconductor structure after the insulating layer is formed. Exemplarily, the insulating layer 13 can be formed on the inner wall surface of the groove 12 by a thermal oxygen growth process. The material of the insulating layer 13 may include an oxide. The insulating layer 13 is located in the groove 12 and covers the inner wall surface. After the thermal oxygen growth process, the semiconductor structure can be annealed. Optionally, the insulating layer 13 can be formed, for example, by deposition.

[0078] Fig. 9 1 shows a semiconductor structure after the gate is formed. Exemplarily, the gate 14 can be formed by a polysilicon growth process and a back etching process, and its material includes polysilicon. The gate 14 may include other conductive materials. The gate 14 fills the remaining space in the original trench 12 except the insulating layer 13. The gate 14 and the insulating layer 13 can be used to form a gate oxide structure 15. Fig.10 for Fig. 9 The gate oxide structure 15 penetrates the first source contact region 10 , the channel layer 9 and the third dielectric layer 7 .

[0079] The method for manufacturing a trench insulated gate field effect transistor provided in the embodiment of the present disclosure forms a protective layer 5 and a first channel 6 that can partially overlap with a third dielectric layer 7 through two epitaxial processes, so that a trench insulated gate field effect transistor 100 can be formed quickly and at low cost.

[0080] refer to Figure 4 , Fig. 9 and Fig.10 The embodiment of the present disclosure provides a trench-type insulated gate field effect transistor 100. The trench-type insulated gate field effect transistor 100 includes: a first dielectric layer 3, a second dielectric layer 4, a third dielectric layer 7, a channel layer 9, a first source contact region 10, a gate oxide structure 15, a protective layer 5 and at least one first channel 6.

[0081] The first dielectric layer 3 , the second dielectric layer 4 , the third dielectric layer 7 , the channel layer 9 and the first source contact region 10 are stacked in sequence. The trench insulated gate field effect transistor 100 may further include a second source contact region 11 .

[0082] The gate oxide structure 15 penetrates the first source contact region 10 and the channel layer 9 and at least extends into the third dielectric layer 7. The gate oxide structure 15 and the first source contact region 10 are arranged along the X direction, and the gate oxide structure 15 and the second source contact region 11 are arranged along the X direction.

[0083] The protection layer 5 penetrates the second dielectric layer and is stacked with the gate oxide structure 15. The first channel 6 penetrates the protection layer 5. The first channel 6 is electrically connected between the first dielectric layer 3 and the third dielectric layer 7.

[0084] When the trench-type insulated gate field effect transistor 100 is in use, the protective layer 5 can effectively reduce the maximum electric field at the bottom insulating layer of the gate oxide structure 15, and has good long-term reliability. At the same time, the setting of the first channel 6 helps to reduce the on-resistance, so that the trench-type insulated gate field effect transistor 100 has better circuit performance.

[0085] Fig.11 : shows a cross section of a semiconductor structure provided by an embodiment of the present disclosure. In some embodiments, the first channel 6 has its narrowest dimension as the width direction, and its length direction can be inclined relative to the X-axis direction. In other words, the projection profile of each section of the protective layer 5 can be a parallelogram. Exemplarily, the X-axis direction is the first direction and the Y-axis direction is the second direction, then along the second direction, at least two first channels 6 are evenly spaced.

[0086] Fig.12 The cross section of the semiconductor structure provided by the embodiment of the present disclosure is shown. In some embodiments, the first channel 6 has a broken line shape as a whole.

[0087] Fig.13 FIG. 2 shows a cross section of a semiconductor structure provided by an embodiment of the present disclosure. In some embodiments, the projection of the first channel 6 along the stacking direction, i.e., the Z-axis direction, has a curved edge. Fig.13 As shown, the projection profile of the first channel 6 may have a wave shape.

[0088] Fig.14 The cross section of the semiconductor structure provided by the embodiment of the present disclosure is shown. In some embodiments, the projection of the first channel 6 along the stacking direction, ie, the Z-axis direction, has an arc-shaped edge.

[0089] Exemplarily, among the cross sections of the gate oxide structure 15 parallel to the XZ plane, some overlap with the projection of the protection layer 5, and others overlap with the projection of the protection layer 5 and the first channel 6. In some embodiments, it is possible to avoid that some cross sections of the gate oxide structure 15 completely overlap with the projection of the first channel 6. The gate oxide structure 15 is more fully protected, and these trench-type insulated gate field effect transistors 100 have better reliability.

[0090] Fig.15The cross section of the semiconductor structure provided by the embodiment of the present disclosure is shown. In some embodiments, in the step of forming the patterned protective layer 5, a second dielectric layer 4 and a plurality of first channels 6 are obtained. The plurality of first channels 6 may include a first first channel 6-1, a second first channel 6-2, a third first channel 6-3 and a fourth first channel 6-4. Along the X-axis direction, the first channel 6 does not penetrate the protective layer 5. Exemplarily, the first first channel 6-1 and the third first channel 6-3 are arranged relative to each other along the X-axis direction. The second first channel 6-2 and the fourth first channel 6-4 are arranged relative to each other along the X-axis direction, and the two are spaced apart from the first first channel 6-1 and the third first channel 6-3 along the Y-axis direction.

[0091] Fig.15 The double-dotted line in the figure indicates the projection boundary of the gate oxide structure 15. Both ends of the protective layer 5 can protrude from the gate oxide structure 15. The first first channel 6-1 partially overlaps with the gate oxide structure 15, and at the same time, the first first channel 6-1 is electrically connected between the first dielectric layer 3 and the third dielectric layer 7. The same is true for the remaining first channels 6. Exemplarily, the projection of the first first channel 6-1 has a rectangular outline.

[0092] Fig.16 1 shows a cross section of a semiconductor structure provided by an embodiment of the present disclosure. Exemplarily, the projection of the first first channel 6-1 has a parallelogram profile. In the cross-sectional structure of the trench insulated gate field effect transistor 100 provided by an embodiment of the present disclosure at AA, the first channel 6 can also be set in other forms, but is not limited thereto.

[0093] Fig.17 : shows a cross section of a semiconductor structure provided by an embodiment of the present disclosure. For example, in the trench insulated gate field effect transistor 100 provided by the embodiment of the present disclosure, the doping concentration of the first channel 6 is greater than the doping concentration of the first dielectric layer 3 and the doping concentration of the third dielectric layer 7. The trench insulated gate field effect transistor 100 has a smaller on-resistance.

[0094] Exemplarily, in the method for forming a trench-type insulated gate field effect transistor, the method further includes: forming a first channel by ion implantation. The first channel may have a heavily N-type doping type.

[0095] Fig.18: shows a cross section of a semiconductor structure provided by an embodiment of the present disclosure. In some embodiments, the trench-type insulated gate field effect transistor 100 includes a second channel 16. The second channel 16 runs through the second dielectric layer 4 and is located on one side of the protective layer 5 along the X-axis direction. The second channel 16 can be provided on both sides of the protective layer 5. The second channel 16 is located between the first dielectric layer 3 and the third dielectric layer 7. The second channel 16 can be an integral structure with the first channel 6. The second channel 16 can be electrically connected to the first channel 6. The second channel 16 has a first doping type, for example, N-type heavy doping, which can improve the conduction performance of the trench-type insulated gate field effect transistor 100. The doping concentration of the second channel 16 is greater than the doping concentration of the first dielectric layer 3 and the doping concentration of the third dielectric layer 7, and the doping concentration of the second channel 16 is also greater than the doping concentration of the second dielectric layer 4.

[0096] Fig.19 In some embodiments, the first channel 6 partially overlaps with the gate oxide structure 15 , thereby ensuring that the first channel 6 is electrically connected between the first dielectric layer 3 under the protective layer 5 and the third dielectric layer 7 on the protective layer 5 .

[0097] Fig. 20 : shows a cross section of a semiconductor structure provided by an embodiment of the present disclosure. In some embodiments, along the X-axis direction, one end of the first channel 6 protrudes from the gate oxide structure 15 and may be connected to the second dielectric layer 4, and the other end may not protrude from the gate oxide structure 15. A trench-type insulated gate field effect transistor having such a cross-sectional structure can protect the gate oxide structure 15 while reducing the specific on-resistance. Optionally, one end of the first channel 6 may protrude from the gate oxide structure 15, and the other end may be flush with or protrude from the gate oxide structure 15. Optionally, both ends of the first channel 6 may be flush with the gate oxide structure 15.

[0098] Fig.21 The semiconductor structure provided by the embodiment of the present disclosure is shown. Fig. 22 1 is an isometric view. Exemplarily, the embodiment of the present disclosure provides a trench-type insulated gate field effect transistor 100, in which the second dielectric layer 4 and the third dielectric layer 7 are configured as a current diffusion region 17. The current diffusion region 17 has a first doping type, and the doping concentration is greater than the doping concentration of the first dielectric layer 3. By providing the current diffusion region 17, the beneficial effects of reduced resistivity, strong conductivity, and reduced specific on-resistance are achieved.

[0099] Fig.23 Shows Fig.21 The cross section of the semiconductor structure shown in FIG. Optionally, the first channel 6 is provided as a part of the current diffusion region 17. Optionally, the doping concentration of the first channel 6 is greater than the doping concentration of the current diffusion region 17. The first dielectric layer 3 can be used as a drift region.

[0100] In some embodiments, the present disclosure provides a method for manufacturing Fig.21 The method of the trench insulated gate field effect transistor 100 shown in the figure, wherein the first prefabricated dielectric layer 2 can be formed by an epitaxial process; then a two-step ion implantation process is performed, one step forms the protective layer 5, and the other step forms the second dielectric layer 4 and the first channel 6, and the depths of the two-step ion implantation can be controlled to be substantially the same; and then an epitaxial process is performed to form the third dielectric layer 7. The second dielectric layer 4, the third dielectric layer 7 and the first channel 6 are set as a current diffusion region 17.

[0101] In other embodiments, the method for manufacturing a trench-type insulated gate field effect transistor further includes: forming a first dielectric layer 3; forming a prefabricated second dielectric layer located on a side of the first dielectric layer 3 away from the substrate 1 by an epitaxial process, wherein the doping concentration of the prefabricated second dielectric layer is greater than the doping concentration of the first dielectric layer 3; forming a patterned protective layer 5 by ion implantation, and obtaining a second dielectric layer 4 and a first channel 6, wherein the depth of the ion implantation can be controlled; and then forming a third dielectric layer 7 by an epitaxial process. The second dielectric layer 4, the third dielectric layer 7 and the first channel 6 are configured as a current diffusion region 17.

[0102] Optionally, the doping concentration of the first channel 6 may be set to be higher than the doping concentration of the current diffusion region 17 formed by the second dielectric layer 4 and the third dielectric layer 7 .

[0103] In summary, the current diffusion region 17 can be formed by multiple sub-steps. The trench 12 is then opened to expose the protection layer 5. This method can avoid high-energy ion implantation.

[0104] It should be understood that the trench insulated gate field effect transistor 100 provided in the embodiment of the present disclosure may also include other structures, for example, an electrode structure may be provided on the side of the substrate 1 away from the gate oxide structure 15 .

[0105] refer to Fig.24 , Fig.24 The electronic component 300 is provided in another aspect of the embodiment of the present disclosure. The electronic component 300 includes a trench insulated gate field effect transistor 100 and a circuit 200. The electronic component 300 can be used in a high voltage environment.

[0106] The trench insulated gate field effect transistor 100 can be any of the above-mentioned embodiments, which helps to make the electronic component 300 have higher integration, higher power density, higher reliability and lower on-resistance.

[0107] The circuit 200 is electrically connected to the trench insulated gate field effect transistor 100. By way of example, the circuit 200 may be electrically connected to the gate 14, the first source contact region 10, the second source contact region 11, the substrate 1, etc., and may also be electrically connected to the protective layer 5. By way of example, the circuit 200 may include metal interconnects or power contacts.

[0108] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] In the above embodiments, unless otherwise clearly specified and limited, the execution order of each step is not limited, for example, it can be executed in parallel, or it can be executed successively in different orders. The sub-steps of each step can also be executed alternately. The above various forms of processes can be used, and steps can be reordered, added or deleted, as long as the desired results of the technical solution provided in the embodiment of the present disclosure can be achieved, which is not limited herein.

[0110] The above embodiments only express several implementation methods of the invention, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection of the invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the invention, which all belong to the scope of patent protection required by the invention. Therefore, the scope of patent protection of the invention shall be based on the attached claims.

Claims

1. A method for manufacturing a trench-type insulated gate field effect transistor, It is characterized in that include: Forming a patterned protective layer on the composite substrate, and obtaining a first channel and a stacked first dielectric layer and a second dielectric layer, wherein the first dielectric layer, the second dielectric layer and the first channel respectively have a first doping type, the protective layer has a second doping type, the protective layer penetrates the second dielectric layer, and the first channel penetrates the protective layer; forming a third dielectric layer, a channel layer, and a first source contact region sequentially arranged along a direction in which the second dielectric layer is away from the first dielectric layer, wherein the third dielectric layer and the first source contact region have the first doping type, and the channel layer has the second doping type; and A gate oxide structure is formed, wherein the gate oxide structure penetrates the first source contact region and the channel layer and at least extends into the third dielectric layer, and the gate oxide structure is stacked with the protection layer and with the first channel.

2. The method for manufacturing a trench-type insulated gate field effect transistor according to claim 1, in, Also includes: The first channel is formed by ion implantation, wherein a doping concentration of the first channel is greater than or equal to a doping concentration of the first dielectric layer and a doping concentration of the third dielectric layer.

3. The method for manufacturing a trench-type insulated gate field effect transistor according to claim 1, in, The step of forming the third dielectric layer includes: forming the third dielectric layer by an epitaxial process.

4. The method for manufacturing a trench-type insulated gate field effect transistor according to claim 1 or 3, in, The method further includes: forming the second dielectric layer and the first channel by an epitaxial process, wherein the doping concentration of the second dielectric layer is greater than the doping concentration of the first dielectric layer.

5. A trench-type insulated gate field effect transistor, It is characterized in that include: A first dielectric layer, a second dielectric layer, a third dielectric layer, a channel layer and a first source contact region stacked in sequence, wherein the first dielectric layer, the second dielectric layer, the third dielectric layer and the first source contact region have a first doping type, and the channel layer has a second doping type; a gate oxide structure, penetrating the first source contact region and the channel layer, and extending at least into the third dielectric layer; a protective layer, penetrating the second dielectric layer and stacked with the gate oxide structure, the protective layer having the second doping type; and At least one first channel, the first channel penetrates the protection layer, the first channel has the first doping type and is electrically connected between the first dielectric layer and the third dielectric layer, and the first channel is stacked with the gate oxide structure.

6. The trench insulated gate field effect transistor according to claim 5, in, The gate oxide structure and the first source contact region are arranged in parallel along a first direction, and at least two of the first channels are evenly spaced apart along a second direction perpendicular to the stacking direction and the first direction.

7. The trench insulated gate field effect transistor according to claim 5, in, The projection of the first channel along the stacking direction has a curved edge.

8. The trench insulated gate field effect transistor according to claim 5, in, The doping concentration of the first channel is greater than or equal to the doping concentration of the first dielectric layer and the doping concentration of the third dielectric layer.

9. The trench insulated gate field effect transistor according to claim 8, in, It also includes a second channel, which runs through the second dielectric layer and is located on one side of the protective layer. The second channel has the first doping type, and the doping concentration of the second channel is greater than or equal to the doping concentration of the first dielectric layer and the doping concentration of the third dielectric layer. The second channel is electrically connected to the first channel.

10. The trench insulated gate field effect transistor according to claim 5, in, The second dielectric layer, the first channel and the third dielectric layer are configured as a current diffusion region. The current diffusion region has the first doping type and a doping concentration greater than a doping concentration of the first dielectric layer.

11. The trench insulated gate field effect transistor according to any one of claims 5 to 10, in, The gate oxide structure and the first source contact region are arranged in parallel along a first direction, and both ends of the protection layer along the first direction protrude from the gate oxide structure.

12. An electronic component, It is characterized in that include: A trench insulated gate field effect transistor as claimed in any one of claims 5 to 11; and The circuit is electrically connected to the trench-type insulated gate field effect transistor.

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