A positive and negative pulse high-speed large current driving circuit device

Abstract

The application relates to a positive and negative pulse high-speed large-current driving circuit device, which is characterized by being composed of a first-stage positive and negative pulse high-speed small-current driving circuit, a second-stage auxiliary driving circuit and a second-stage positive and negative signal high-speed large-current driving circuit connected in sequence. The first-stage positive and negative pulse high-speed small-current driving circuit is composed of a field effect transistor Q1 and a field effect transistor Q2; the second-stage auxiliary driving circuit is composed of a field effect transistor Q5, a field effect transistor Q6, a resistor R1 and a resistor R2; and the second-stage positive and negative signal high-speed large-current driving circuit is composed of a field effect transistor Q3 and a field effect transistor Q4. The application has the beneficial effect of solving the contradiction between the high speed and the large current of the driving circuit, and simultaneously realizing the high speed and the large current of the driving signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit driving, in particular to a positive and negative pulse high-speed large-current driving circuit device. BACKGROUND

[0002] The positive and negative pulse driving circuit is generally composed of high-speed triodes, power MOS tubes and the like. Since the gate of the power MOS tube has a parasitic capacitance, the capacitance Cin value increases greatly with the increase of the power of the MOS tube. Therefore, the driving current is generally not large when high-speed driving is achieved. When the driving current is large, the driving speed is relatively slow.

[0003] Through retrieval, the patent application for invention "Wide band gap MOSFET tube driving circuit" relates to the field of MOS tube driving, in particular to a wide band gap MOSFET tube driving circuit, which comprises a signal generation module for reconstructing the edges of an input PWM signal by using multiple sets of reconstructed pulse signals to generate a PWM signal with stepped waveform edges; a signal processing module for processing the generated PWM signal into a driving signal for the wide band gap MOSFET tube; and the input ends of the signal generation module and the signal processing module are connected. The wide band gap MOSFET switching performance can be improved, and the phenomena of gate voltage oscillation, voltage spike overshoot and ringing can be effectively avoided, and the anti-interference ability is strong. However, the triode base signal is generated by optical coupling, and the output stage adopts a triode pair tube output, so the driving current is small, there is a delay in the load, and the positive and negative power supply voltages are not symmetrically output.

[0004] The patent application for invention "Pulse driving circuit of magnetic retention electronic lock and magnetic retention electronic lock" discloses a pulse driving circuit of a magnetic retention electronic lock, which comprises a power supply unit for providing a power supply; a pulse conversion unit, the input end of the pulse conversion unit is connected with the power supply unit, the output end of the pulse conversion unit is connected with the electronic lock, and the pulse conversion unit is used for converting the power supply voltage into a pulse voltage to control the magnetic retention. SUMMARY

[0005] The present application aims to provide a positive and negative pulse high-speed large-current driving circuit device to solve the contradiction between high speed and large current of the positive and negative pulse driving circuit. Because when driving, the speed is high, the current generally cannot be too large, and when the current is large, the driving current of the previous stage must be large, and the parasitic side effects of the inductance of the high-current circuit are revealed.

[0006] The technical scheme adopted by the present application to solve the technical problems is as follows:

[0007] The positive and negative pulse high-speed large-current driving circuit device is characterized in that it is composed of a first-stage positive and negative pulse high-speed small-current driving circuit, a second-stage auxiliary driving circuit and a second-stage positive and negative signal high-speed large-current driving circuit connected in sequence.

[0008] Furthermore, the first-stage high-speed low-current driving circuit for positive and negative pulses consists of field-effect transistors Q1 and Q2; the second-stage auxiliary driving circuit consists of field-effect transistors Q5 and Q6, resistors R1 and R2; the second-stage high-speed high-current driving circuit for positive and negative signals consists of field-effect transistors Q3 and Q4; the high-speed low-current signals for positive and negative pulses are input from Vin, and the gates of the four field-effect transistors Q1, Q2, Q5, and Q6 are connected to Vin; the source of field-effect transistor Q2 is connected to a -5V power supply, and its drain is connected to one end of R2. The other end of R2 is connected to GND; the drain of MOSFET Q6 is connected to the drain of Q2, and the source is connected to GND; the source of MOSFET Q1 is connected to GND, the drain is connected to one end of R1, and the other end of R1 is connected to the +5V power supply; the source of MOSFET Q5 is connected to the +5V power supply, and the drain is connected to the drain of Q1; the gate of MOSFET Q4 is connected to the drains of Q5 and Q1, the source is connected to the +5V power supply, and the drain is connected to the output terminal Vout; the gate of MOSFET Q3 is connected to the drain of Q2, the drain is connected to the output terminal Vout, and the source is connected to the -5V power supply.

[0009] The beneficial effect of this invention is that it solves the contradiction between high speed and high current in the driving circuit, and at the same time achieves the purpose of high speed and high current in the driving signal. Attached Figure Description

[0010] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0011] Appendix Figure 1 This is the circuit schematic diagram of the present invention;

[0012] Appendix Figure 2 This is a circuit block diagram of the present invention. Detailed Implementation

[0013] like Figure 2 As shown in the circuit block diagram, this invention provides a high-speed, high-current driving circuit device for positive and negative pulses, including a first-stage high-speed, low-current driving circuit for positive and negative pulses (composed of Q1 and Q2), a second-stage auxiliary driving circuit (composed of Q5, Q6, R1, and R2), and a second-stage high-speed, high-current driving circuit for positive and negative signals (composed of Q3 and Q4).

[0014] like Figure 1 As shown, the specific structure of each driving circuit is as follows:

[0015] The high-speed, low-current drive circuit for first-stage positive and negative pulses consists of Q1 and Q2;

[0016] The secondary auxiliary drive circuit consists of Q5, Q6, R1, and R2;

[0017] The high-speed, high-current drive circuit for two positive and negative signals consists of Q3 and Q4.

[0018] Referring to Figure 1 , the positive and negative pulse high-speed small current signals are input from Vin, and the gates of Q1, Q2, Q5 and Q6 are connected to Vin; the source of Q2 is connected to a -5V power supply, the drain of Q2 is connected to one end of R2, and the other end of R2 is connected to a GND terminal; the drain of Q6 is connected to the drain of Q2, and the source of Q6 is connected to GND; the source of Q1 is connected to the GND terminal, the drain of Q1 is connected to one end of R1, and the other end of R1 is connected to a +5V power supply; the source of Q5 is connected to the +5V power supply, and the drain of Q5 is connected to the drain of Q1; the gate of Q4 is connected to the drain terminals of Q5 and Q1, the source of Q4 is connected to the +5V power supply, and the drain of Q4 is connected to an output terminal Vout; the gate of Q3 is connected to the drain of Q2, the drain of Q3 is connected to the output terminal Vout, and the source of Q3 is connected to the -5V power supply; one end of a load RL is connected to the output terminal Vout, and the other end of RL is connected to GND.

[0019] More specifically, Figure 1 , first, Q1, Q2, Q5 and Q6 are selected as high-speed small power MOSFET tubes, and Q3 and Q4 are selected as high-speed large power MOSFET tubes, wherein Q1 and Q2 are high-speed small power N-MOSFET tubes, Q5 and Q6 are high-speed small power P-MOSFET tubes, the gate opening threshold voltage V THQ1 and V THQ2 of Q1 and Q2 must be less than 5V (the input signal Vin is a positive and negative pulse, the positive pulse amplitude is 5V, and the negative pulse amplitude is -5V), the gate opening threshold voltage value V THQ5 of Q5 must satisfy 5-|V THQ5 |< V THQ1 , and {5-|V THQ5 |} is a positive value, so that Q5 must be closed when Q1 is opened; Q5 can be opened only after Q1 is closed, so that the charging time of the gate capacitor CINQ4 of R1 to Q4 is very short, Q4 is quickly closed, and the purpose of high-speed closing Q4 is achieved. Similarly, the gate opening threshold voltage value V THQ6 of Q6 must satisfy {5-V THQ2}<|V THQ6 |, and {5-V THQ2} is a positive value, so that Q6 must be closed when Q2 is opened; Q6 can be opened only after Q2 is closed, so that the charging time of the gate capacitor C INQ3 of R2 to Q3 is very short, Q3 is quickly opened, and the purpose of high-speed opening Q3 is achieved.

[0020] Figure 1The positive and negative high frequency pulse signals are input from Vin terminal, and the gates of Q1, Q2, Q5 and Q6 are connected, when the input signal is high level +5V, Q1 and Q2 are opened, so that the gate of Q4 is zero level, the gate of Q3 is -5V, Q4 is rapidly opened, Q3 is rapidly closed, and the output terminal Vout outputs +5V high level;

[0021] When the input signal Vin changes from high level +5V to -5V, Q1 is first disconnected, then Q5 is opened, the gate of Q4 is rapidly +5V level, Q4 is rapidly disconnected, and Vout output is zero level;

[0022] When the Vin signal continues to decrease to negative voltage, Q2 is first closed, then Q6 is opened, the gate of Q3 is rapidly charged to zero level, Q3 is rapidly opened, and Vout is rapidly output -5V low voltage, so that the purpose of Vout driving signal positive and negative pulse high speed large current is realized. INQ3 Rapidly charged to zero level, Q3 tube is rapidly opened, and Vout is rapidly output -5V low voltage, so that the purpose of Vout driving signal positive and negative pulse high speed large current is realized.

[0023] The above is only the preferred embodiment of the present application, and does not limit the present application in any form; any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into equivalent embodiments with the above disclosed methods and technical contents without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent replacement, equivalent change and modification of the above embodiments according to the technical essence of the present application, which does not depart from the content of the technical solution of the present application, still belongs to the protection scope of the technical solution of the present application.

Claims

1. A high-speed, high-current driving circuit device for positive and negative pulses, characterized in that... It consists of a high-speed, low-current drive circuit with positive and negative pulses, a secondary auxiliary drive circuit, and a high-speed, high-current drive circuit with positive and negative signals. The high-speed, low-current drive circuit for the first-stage positive and negative pulses is composed of field-effect transistors Q1 and Q2. The secondary auxiliary drive circuit consists of field-effect transistor Q5, field-effect transistor Q6, resistor R1, and resistor R2; The high-speed, high-current drive circuit for the two-stage positive and negative signals is composed of field-effect transistors Q3 and Q4. High-speed, low-current positive and negative pulse signals are input from Vin. The gates of four field-effect transistors (FETs) Q1, Q2, Q5, and Q6 are connected to Vin. The source of FET Q2 is connected to a -5V power supply, and its drain is connected to one end of resistor R2, with the other end of R2 connected to GND. The drain of FET Q6 is connected to the drain of Q2, and its source is connected to GND. The source of FET Q1 is connected to GND, and its drain is connected to one end of resistor R1, with the other end of R1 connected to a +5V power supply. The source of FET Q5 is connected to a +5V power supply, and its drain is connected to the drain of Q1. The gate of FET Q4 is connected to the drains of both Q5 and Q1, its source is connected to a +5V power supply, and its drain is connected to the output terminal Vout. The gate of FET Q3 is connected to the drain of Q2, its drain is connected to the output terminal Vout, and its source is connected to a -5V power supply.

2. The positive and negative pulse high-speed high-current driving circuit device according to claim 1, characterized in that: Field-effect transistors Q1, Q2, Q5, and Q6 are high-speed, low-power MOSFETs, while field-effect transistors Q3 and Q4 are high-speed, high-power MOSFETs. Among them, Q1 and Q2 are high-speed, low-power N-MOSFETs, and Q5 and Q6 are high-speed, low-power P-MOSFETs.

3. The positive and negative pulse high-speed high-current driving circuit device according to claim 2, characterized in that: The input signal Vin has a positive pulse amplitude of 5V and a negative pulse amplitude of -5V. The gate turn-on threshold voltage V of Q1, Q2, Q5, and Q6 is... THQ1 and V THQ2 Both must be less than 5V, the gate turn-on threshold voltage value V of Q5 THQ5 5-|V must be satisfied THQ5 |< V THQ1 And {5-|V THQ5 |} is a positive value; the gate turn-on threshold voltage value V of Q6 THQ6 Must satisfy {5-V THQ2 }<|V THQ6 |, and {5-V THQ2 } is a positive value.

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