A voltage detection circuit for high-side NMOS driving

Abstract

The application discloses a voltage detection circuit for high-side NMOS driving; the detection circuit can be applied to a driving circuit system realized by using a pump circuit mode; the system comprises a high-side driving, a pump circuit, a voltage detection circuit and a power tube NM1_H; the high-side driving is electrically connected with the pump circuit, the pump circuit is electrically connected with the power tube NM1_H, the input end of the voltage detection circuit is electrically connected with the gate and the source of the power tube NM1_H respectively, and the output end of the voltage detection circuit is electrically connected with the pump circuit; the voltage detection circuit comprises a high-voltage tube PM1, a high-voltage tube PM2, a high-voltage tube NM3, a high-voltage tube NM4, a bias current I1, a bias current I2, a bias current I3, a voltage stabilizing diode Z1 and an inverter INV1; the application uses the reverse breakdown voltage of the voltage stabilizing diode as a judgment threshold value, detects the voltage difference between two input signals, realizes the protection of the high-side power tube, has few devices, is low in cost and has very low power consumption.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a voltage detection circuit for high-side NMOS driving. Background Technology

[0002] With the continuous development of electronic technology, electronic devices need to meet the requirements of miniaturization, high performance, and low power consumption. Switching power supplies have become widely used, and driver circuits, as an important part of switching power supplies, are also constantly being optimized. Currently, NMOS power transistors are commonly used in driver circuits. Depending on whether the NMOS power transistor is connected to the power supply terminal or the ground terminal, it can be divided into high-side transistors and low-side transistors. In high-side NMOS driver circuits, the drain of the NMOS transistor is connected to the power supply terminal, and its gate voltage must be higher than the power supply voltage by a turn-on voltage; otherwise, a large turn-on voltage drop will occur on the power transistor.

[0003] Currently, providing a sufficiently large gate voltage for power transistors mainly employs bootstrap circuits and charge pump circuits. However, these methods introduce problems such as complex circuit structures, high power consumption, and high cost. Using a pump circuit, the power supply voltage is multiplied, and its output can be used as the gate voltage of the high-side NMOS power transistor. Furthermore, the pump circuit only operates when the high-side NMOS power transistor needs to be turned on, remaining off otherwise, thus reducing power consumption. Thin-gate oxide NMOS power transistors are commonly used in integrated circuits, with a gate-source breakdown voltage of approximately 5.5V. The gate voltage of an NMOS power transistor cannot be too high, otherwise it will burn out the transistor. Therefore, a simple, low-power detection circuit is needed to detect the voltage difference between the gate and source terminals of the high-side power transistor, thereby controlling the operation of the pump circuit to ensure that the gate-source voltage of the power transistor does not exceed its gate-source breakdown voltage.

[0004] For example, existing technologies such as Figure 3 As shown, in the driving circuit, a voltage higher than the power supply voltage is needed to power the high-side drive, which is usually achieved by using a charge pump.

[0005] It mainly includes a voltage regulator circuit, a charge pump, a high-side gate drive, and a power transistor NM1_H.

[0006] Voltage regulator circuit: generates a voltage VH1 that is less than the gate-source withstand voltage of the MOSFET.

[0007] Charge pump: generates a voltage VH higher than the power supply voltage VM, where VH = VH1 + VM.

[0008] High-side gate drive: The input signal VIN_UP is level-shifted, logic-based, etc., and output VG_UP to drive the gate of the high-side power transistor.

[0009] Power transistor NM1_H: The power transistor is turned on or off depending on the gate voltage VG_UP.

[0010] The aforementioned driving circuit first requires a voltage regulator to generate a voltage no higher than the device's gate-source breakdown voltage. Then, a charge pump generates a voltage higher than the supply voltage as the power supply for driving the high-side gate, making the circuit system relatively complex. Furthermore, the charge pump is constantly operating, resulting in significant power consumption. Additionally, the charge pump's output voltage is a constantly changing dynamic voltage, and it only charges the capacitor when the clock signal is high, leading to slow efficiency and substantial energy loss.

[0011] It has the following disadvantages: In traditional driving circuits, the use of bootstrap circuits and charge pump circuits results in high power consumption, complex circuit structure, and high cost. If the pump circuit is used to directly generate the gate control signal of the high-side power transistor, a voltage detection circuit is required to detect the voltage difference between the gate voltage and the source voltage of the high-side power transistor to ensure that its gate-source voltage does not exceed the device's withstand voltage (5.5V). This voltage detection circuit must have the characteristics of simple circuit structure and low power consumption.

[0012] The common way to perform voltage detection is to use a traditional comparator. However, traditional comparators use many components and require additional bias circuitry to generate a reference voltage, resulting in greater circuit complexity and power consumption.

[0013] This invention proposes a voltage detection circuit for high-side NMOS driving, aiming to protect the high-side power transistor in driving circuits that directly generate gate control signals for the high-side power transistor using a pump circuit, while solving the problems of high power consumption and complex circuit structure in traditional voltage detection circuits. Summary of the Invention

[0014] The purpose of this invention is to provide a voltage detection circuit for high-side NMOS driving, so as to solve the problems mentioned in the background art.

[0015] To achieve the above objectives, the present invention provides the following technical solution: a voltage detection circuit for high-side NMOS driving, comprising a voltage detection circuit, applicable to a driving circuit system implemented using a pump circuit, the system comprising a high-side drive, a pump circuit, a voltage detection circuit, and a power transistor NM1_H; the voltage detection circuit detects the voltage difference between the gate voltage VG_UP and the source voltage V_SW of the high-side power transistor, determines whether the voltage difference exceeds the gate-source withstand voltage of the power transistor, outputs a judgment signal VOUT, and controls and adjusts the operating state of the pump circuit;

[0016] The power transistor NM1_H is controlled to turn on or off based on the gate voltage VG_UP.

[0017] The voltage detection circuit includes high-voltage transistors PM1, PM2, NM3, and NM4, bias current I1, bias current I2, bias current I3, Zener diode Z1, and inverter INV1.

[0018] Preferably, the drive circuit system implemented using a pump circuit includes a high-side drive, a pump circuit, a voltage detection circuit, and a power transistor NM1_H;

[0019] The high-side driver is electrically connected to the input signal VIN_UP, the high-side driver is electrically connected to the pump circuit, the pump circuit is electrically connected to the power transistor NM1_H, the input terminal of the voltage detection circuit is electrically connected to the gate and source of the power transistor NM1_H respectively, the output terminal of the voltage detection circuit is electrically connected to the pump circuit, and the high-side driver, the pump circuit and the drain of the power transistor NM1_H are electrically connected to the power supply voltage VM respectively.

[0020] The high-side driver is used to receive the input signal VIN_UP, perform level conversion and logic judgment on the input signal VIN_UP, and then output VG_H;

[0021] The pump circuit is used to generate a voltage VG_UP that is higher than the power supply voltage VM, and the relationship between the voltage VG_UP and the power supply voltage VM is as follows: VG_UP = 2 * VM.

[0022] Preferably, the power supply voltage VM is the power supply voltage of the power transistor, which varies widely and may result in high voltage conditions. The gate-source withstand voltage of the power transistor NM1_H is generally 5.5V, and the on-resistance of the power transistor NM1_H is very small. When the power transistor NM1_H is turned on, the output V_SW is approximately equal to the power supply voltage VM. When the power transistor NM1_H is turned on, the output of the pump circuit is VG_UP = 2*VM, and the gate-source voltage of the power transistor NM1_H is approximately VG_UP - V_SW = VM. When the power supply voltage VM is greater than the gate-source withstand voltage of the device, the gate-source voltage of the power transistor NM1_H will exceed the withstand voltage, causing device damage.

[0023] Preferably, the voltage detection circuit controls and regulates the pump circuit; the voltage detection circuit detects the voltage difference between the output VG_UP of the pump circuit and the output V_SW of the power transistor NM1_H. When VG_UP - V_SW < 5.5V, the pump circuit operates normally; when VG_UP - V_SW reaches the gate-source withstand voltage of 5.5V, the output signal VOUT changes, shutting down the pump circuit, and the output VG_UP of the pump circuit no longer continues to rise.

[0024] Preferably, when the gate-source voltage of the power transistor NM1_H drops below its gate-source withstand voltage, the output signal VOUT of the voltage detection circuit returns to its original potential, and the pump circuit is turned on again. The pump circuit is in a loop of turning off and on according to the change of the output signal VOUT of the voltage detection circuit, so that the output VG_UP eventually stabilizes at the sum of the power supply voltage VM and the gate-source withstand voltage of the power transistor NM1_H, which is VM + 5.5V, thereby ensuring that the gate-source voltage of the power transistor NM1_H is maintained at 5.5V, and realizing the protection of the high-side power transistor under high power supply voltage.

[0025] Preferably, VDD in the voltage detection circuit is a low-voltage logic power supply, and the input V_SW and VG_UP are the signals to be detected, the output VOUT is the detection result, and the bias current I1 and bias current I2 are in the nA level, and I1 = I2.

[0026] Preferably, in the voltage detection circuit, VDD is electrically connected to the gate of the high-voltage transistor NM3, the source of the high-voltage transistor NM3 is connected to the bias current I1, the drain of the high-voltage transistor NM3 is electrically connected to the drain and gate of the high-voltage transistor PM1, the source of the high-voltage transistor PM1 receives the signal V_SW to be detected, the gate of the high-voltage transistor PM1 is electrically connected to the gate of the high-voltage transistor PM2, the source of the high-voltage transistor PM2 is electrically connected to the positive terminal of the Zener diode Z1, and the negative terminal of the Zener diode Z1 receives the signal VG_UP to be detected.

[0027] Preferably, the gate of the high-voltage transistor NM4 is electrically connected to the logic power supply VDD, the drain of the high-voltage transistor NM4 is electrically connected to the drain of the high-voltage transistor PM2, the source of the high-voltage transistor NM4 is connected to the bias current I2, the input terminal of the inverter INV1 is electrically connected to the drain of the high-voltage transistor PM2, and outputs VOUT with the output terminal of the inverter INV1, the bias current I3 is connected in series between the logic power supply VDD and the power supply terminal of the inverter INV1, and the other end of the inverter INV1 is electrically connected to GND.

[0028] Preferably, the bias current I1 and the bias current I2 are electrically connected to GND, and the input terminal of the bias current I1 is connected to the source of the high-voltage tube NM3 at point D.

[0029] Preferably, the input terminal of the bias current I2 is connected to the source of the high-voltage transistor NM4 at point C, and the drain of the high-voltage transistor NM4 is connected in series with the drain of the high-voltage transistor PM2 at point A.

[0030] Compared with the prior art, the beneficial effects of the present invention are:

[0031] The voltage detection circuit of this invention protects the high-side power transistor by detecting whether the voltage difference between the gate and source terminals of the high-side power transistor exceeds the reverse breakdown voltage (5.5V) of the Zener diode and controlling the pump circuit. The circuit uses the reverse breakdown voltage of the Zener diode as the judgment threshold. Compared with traditional voltage detection circuits, it does not require an additional bias circuit, has a simple detection principle and circuit implementation, uses very few components, has a small area, low cost, and the circuit structure can use a small bias current (nA level) with very low power consumption. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the system structure of the present invention;

[0033] Figure 2 This is a schematic diagram of the voltage detection circuit of the present invention;

[0034] Figure 3 This is a schematic diagram of the prior art system structure of the present invention. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] Please see Figures 1-2 The present invention provides a technical solution: a voltage detection circuit for high-side NMOS driving, which can be applied to a driving circuit system implemented by a pump circuit, the system including a high-side drive, a pump circuit, a voltage detection circuit and a power transistor NM1_H;

[0037] The high-side driver is electrically connected to the input signal VIN_UP, the high-side driver is electrically connected to the pump circuit, the pump circuit is electrically connected to the power transistor NM1_H, the input terminal of the voltage detection circuit is electrically connected to the gate and source of the power transistor NM1_H respectively, the output terminal of the voltage detection circuit is electrically connected to the pump circuit, and the high-side driver, the pump circuit and the drain of the power transistor NM1_H are electrically connected to the power supply voltage VM respectively.

[0038] The high-side driver is used to receive the input signal VIN_UP, perform level conversion and logic judgment on the input signal VIN_UP, and then output VG_H;

[0039] The pump circuit is used to generate a voltage VG_UP that is higher than the power supply voltage VM, and the relationship between the voltage VG_UP and the power supply voltage VM is as follows: VG_UP = 2 * VM;

[0040] The voltage detection circuit is used to detect the voltage difference between the output voltage VG_UP of the pump circuit and the output voltage V_SW of the power transistor NM1_H, determine whether the voltage difference exceeds the gate-source withstand voltage of the power transistor, output a judgment signal VOUT, and then control and adjust the working state of the pump circuit.

[0041] The power transistor NM1_H is controlled to turn on or off based on the gate voltage VG_UP.

[0042] The voltage detection circuit includes high-voltage transistors PM1, PM2, NM3, and NM4, bias current I1, bias current I2, bias current I3, Zener diode Z1, and inverter INV1.

[0043] In order to power the system and control the conduction of the power transistor NM1_H, in this embodiment, preferably, the power supply voltage VM is the power supply voltage of the power transistor, which varies greatly and may result in high voltage. The gate-source withstand voltage of the power transistor NM1_H is generally 5.5V, and the on-resistance of the power transistor NM1_H is very small. When the power transistor NM1_H is turned on, the output V_SW is approximately equal to the power supply voltage VM.

[0044] To achieve conduction control of the power transistor NM1_H, in this embodiment, preferably, the pump circuit generates a voltage higher than the power supply voltage VM when the power transistor NM1_H is turned on. The output voltage VG_UP of the pump circuit can reach up to 2*VM. The gate-source voltage of the power transistor NM1_H is approximately VG_UP - V_SW = VM. When the power supply voltage VM is greater than the device's gate-source withstand voltage, the gate-source voltage of the power transistor NM1_H will exceed the withstand voltage, causing device damage.

[0045] To detect the gate-source voltage of the power transistor NM1_H and achieve reverse control adjustment of the pump circuit, in this embodiment, preferably, the voltage detection circuit detects the voltage difference between the output VG_UP of the pump circuit and the output V_SW of the power transistor NM1_H. When VG_UP - V_SW < 5.5V, the pump circuit operates normally; when VG_UP - V_SW reaches the gate-source withstand voltage of 5.5V, the output signal VOUT changes, shutting down the pump circuit, and the output VG_UP of the pump circuit no longer continues to rise.

[0046] In order for the voltage detection circuit to control the pump circuit through the potential of the output signal VOUT, in this embodiment, preferably, when the gate-source voltage of the power transistor NM1_H drops below its gate-source withstand voltage, the output signal VOUT of the voltage detection circuit returns to its original potential, and the pump circuit is turned on again. The pump circuit is in a loop of turning off and on according to the change of the output signal VOUT of the voltage detection circuit, so that the output VG_UP eventually stabilizes at the sum of the power supply voltage VM and the gate-source withstand voltage of the power transistor NM1_H, which is VM+5.5V, thereby ensuring that the gate-source voltage of the power transistor is maintained at 5.5V, and realizing the protection of the high-side power transistor under high power supply voltage.

[0047] In order to power the voltage detection circuit and input the detection signal, in this embodiment, preferably, VDD in the voltage detection circuit is a low-voltage logic power supply, and the input V_SW and VG_UP are the signals to be detected, the output VOUT is the detection result, and the bias current I1 and bias current I2 are in the nA level, and I1 = I2.

[0048] To enable input of two signals to be detected, in this embodiment, preferably, the gate of the high-voltage transistor NM3 is electrically connected to VDD in the voltage detection circuit, the source of the high-voltage transistor NM3 is connected to the bias current I1, the drain of the high-voltage transistor NM3 is electrically connected to the drain and gate of the high-voltage transistor PM1, the source of the high-voltage transistor PM1 receives the signal V_SW to be detected, the gate and drain of the high-voltage transistor PM1 are electrically connected to the gate of the high-voltage transistor PM2, the source of the high-voltage transistor PM2 is electrically connected to the positive terminal of the Zener diode Z1, and the negative terminal of the Zener diode Z1 receives the signal VG_UP to be detected.

[0049] The output signal is achieved through inverter INV1. In this embodiment, preferably, the gate of the high-voltage transistor NM4 is electrically connected to the logic power supply VDD, the drain of the high-voltage transistor NM4 is electrically connected to the drain of the high-voltage transistor PM2, the source of the high-voltage transistor NM4 is connected to the bias current I2 and electrically connected to the input terminal of inverter INV1, the output terminal of inverter INV1 outputs VOUT, the bias current I3 is connected in series between the logic power supply VDD and the power supply terminal of inverter INV1, and the other end of inverter INV1 is electrically connected to GND.

[0050] In order to connect the bias current I1 to the high-voltage transistor NM3, in this embodiment, preferably, the bias current I1 and the bias current I2 are electrically connected to GND, and the input terminal of the bias current I1 is connected to the source of the high-voltage transistor NM3 at point D.

[0051] In order to connect the bias current I2 to the high-voltage transistor NM4, in this embodiment, preferably, the input terminal of the bias current I2 is connected to the source of the high-voltage transistor NM4 at point C, and the drain of the high-voltage transistor NM4 is connected in series with the drain of the high-voltage transistor PM2 at point A.

[0052] The working principle and usage process of this invention: When the power transistor NM1_H needs to be turned on, the pump circuit starts to work, and the VG_UP voltage starts to rise. When VG_UP is higher than the turn-on voltage of the power transistor NM1_H, its output V_SW will rise along with VG_UP.

[0053] When VG_UP-V_SW is small and less than the reverse breakdown voltage V of Zener diode Z1 Z1 At this time, the voltage at point B is lower than the voltage V_SW, the high-voltage transistor PM2 is cut off, and the Zener diode Z1 will not conduct, meaning no current flows through the Zener diode Z1. Therefore, the voltage at point C (V_SW) is... C When the voltage is low, the output VOUT is high, and the pump circuit is working normally.

[0054] When VG_UP - V_SW is large and greater than the reverse breakdown voltage V of Zener diode Z1 Z1 When current flows through Zener diode Z1, the voltage at point B rises. When the voltage at point B is higher than V_SW, the gate-source voltage of high-voltage diode PM2 is higher than that of high-voltage diode PM1. Since high-voltage diodes PM1 and PM2 have the same dimensions, the current flowing through high-voltage diode PM2 is greater than the current flowing through high-voltage diode PM1. The current flowing through high-voltage diode PM1 is the bias current I1, and I1 = I2. That is, the current flowing through high-voltage diode PM2 is greater than the bias current I2, and the voltage at point C rises (V_SW). C When the forward threshold of inverter INV1 is reached, the output VOUT jumps to a low level, the pump circuit shuts down, VG_UP no longer rises, and VG_UP-V_SW will be maintained at the reverse breakdown voltage V of Zener diode Z1. Z1 nearby;

[0055] In this circuit, the transistors used for bias currents I1 and I2 are low-voltage transistors, while V_SW and VG_UP are both high-voltage signals. Therefore, high-voltage transistors NM3 and NM4, whose gates are connected to the logic power supply VDD, are added to withstand the high voltage, making the voltage at points C and D lower. This is equivalent to subtracting the gate-source voltage from VDD, thereby protecting the low-voltage transistors used for bias currents I1 and I2. The bias current I3 connected in series with the inverter INV1 is used to limit its current and reduce circuit power consumption.

[0056] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A voltage detection circuit for high-side NMOS driving, characterized in that: Includes a voltage detection circuit, applicable to drive circuit systems implemented using a pump circuit. This system includes a high-side drive, a pump circuit, a voltage detection circuit, and a power transistor NM1_H. The voltage detection circuit detects the voltage difference between the gate voltage VG_UP and the source voltage V_SW of the high-side power transistor, determines whether the voltage difference exceeds the gate-source withstand voltage of the power transistor, outputs a judgment signal VOUT, and controls and adjusts the operating state of the pump circuit. The power transistor NM1_H is controlled to turn on or off based on the gate voltage VG_UP. The voltage detection circuit includes high-voltage transistors PM1, PM2, NM3, and NM4, bias current I1, bias current I2, bias current I3, Zener diode Z1, and inverter INV1. The high-side driver is electrically connected to the input signal VIN_UP, the high-side driver is electrically connected to the pump circuit, the pump circuit is electrically connected to the power transistor NM1_H, the input terminal of the voltage detection circuit is electrically connected to the gate and source of the power transistor NM1_H respectively, the output terminal of the voltage detection circuit is electrically connected to the pump circuit, and the high-side driver, the pump circuit and the drain of the power transistor NM1_H are electrically connected to the power supply voltage VM respectively. The high-side driver is used to receive the input signal VIN_UP, perform level conversion and logic judgment on the input signal VIN_UP, and then output VG_H to the pump circuit. The pump circuit is used to generate a voltage VG_UP that is higher than the power supply voltage VM, and the relationship between voltage VG_UP and power supply voltage VM is as follows: VG_UP = 2 VM; The voltage detection circuit controls and regulates the pump circuit. It detects the voltage difference between the pump circuit's output VG_UP and the power transistor NM1_H's output V_SW. When VG_UP - V_SW < 5.5V, the pump circuit operates normally. When VG_UP - V_SW reaches the gate-source withstand voltage of 5.5V, the output signal VOUT changes, shutting down the pump circuit, and the pump circuit's output VG_UP stops rising. VDD in the voltage detection circuit is a low-voltage logic power supply, and the inputs V_SW and VG_UP are the signals to be detected. The output VOUT is the detection result. The bias currents I1 and I2 are in the nA range, and I1 = I2. In the voltage detection circuit, VDD is electrically connected to the gate of the high-voltage transistor NM3, the source of the high-voltage transistor NM3 is connected to the bias current I1, the drain of the high-voltage transistor NM3 is electrically connected to the drain and gate of the high-voltage transistor PM1, the source of the high-voltage transistor PM1 receives the signal V_SW to be detected, the gate of the high-voltage transistor PM1 is electrically connected to the gate of the high-voltage transistor PM2, the source of the high-voltage transistor PM2 is electrically connected to the positive terminal of the Zener diode Z1, and the negative terminal of the Zener diode Z1 receives the signal VG_UP to be detected. The gate of the high-voltage transistor NM4 is electrically connected to the low-voltage logic power supply VDD. The drain of the high-voltage transistor NM4 is electrically connected to the drain of the high-voltage transistor PM2. The source of the high-voltage transistor NM4 is connected to the bias current I2 and is electrically connected to the input terminal of the inverter INV1. The output terminal of the inverter INV1 outputs VOUT. The bias current I3 is connected in series between the logic power supply VDD and the power supply terminal of the inverter INV1. The ground terminal of the inverter INV1 is electrically connected to GND. The bias current I1 and the bias current I2 are electrically connected to GND.

2. The voltage detection circuit for high-side NMOS driving according to claim 1, characterized in that: When the gate-source voltage of the power transistor NM1_H drops below its gate-source withstand voltage, the output signal VOUT of the voltage detection circuit returns to its original potential, and the pump circuit is turned on again. The pump circuit is in a loop of turning off and on according to the change of the output signal VOUT of the voltage detection circuit, so that the output VG_UP eventually stabilizes at the sum of the power supply voltage VM and the gate-source withstand voltage of the power transistor NM1_H, i.e., VM + 5.5V, thereby ensuring that the gate-source voltage of the power transistor NM1_H is maintained at 5.5V, and realizing the protection of the high-side power transistor under high power supply voltage.

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