A method, device and storage medium for rapid analysis of EM / IR of integrated circuit layout

Abstract

The present invention discloses a method, device and storage medium for rapid analysis of EM / IR of integrated circuit layout. The present invention loads the acquired load current corresponding to the effective MOS tube to the position where the power wiring of the effective MOS tube is located; based on the loaded load current, the resistor network of the configuration area of ​​the effective MOS tube is extracted and a resistor network matrix is ​​established; based on the resistor network matrix, the electrical index parameters for analyzing EM / IR in the circuit wiring related to the effective MOS tube are calculated; and the analysis result of EM / IR of the integrated circuit layout is output.

Description

Technical Field

[0001] The present invention relates to the technical field of EDA tool design and analysis, and in particular to a method, device and storage medium for rapid analysis of power / ground layout EM / IR. Background Art

[0002] As the ultra-large-scale integrated circuit process enters the deep submicron stage, the chip power supply voltage is reduced, and the resistance of the power / ground network can no longer be ignored. Generally, the power grid on the chip (including power signals and ground signals) is treated as an ideal network. In fact, this assumption does not exist in engineering design, especially when the integrated circuit process evolves to ultra-deep submicron and below, the impedance characteristics of all interconnects including the power network are very obvious. Due to the existence of resistance, capacitance, and inductance of the power network interconnection lines, the voltage on the power network fluctuates, and the voltage value will no longer be a stable single value, which causes the problem of power supply voltage drop (IR-drop) and ground voltage rise or ground-bounce. For simplicity, the following "power supply" includes the power signal VDD and the ground signal VSS; "IR drop" includes the voltage drop on the power signal VDD and the voltage bounce on the ground signal VSS.

[0003] IR drop refers to a phenomenon in which the voltage drops or rises on the power and ground networks in an integrated circuit. The magnitude of the voltage drop is determined by the magnitude of the equivalent resistance from the power supply to the calculated logic gate unit. IR drop can be local or global. When a certain number of logic gate units in adjacent positions have logic flip actions at the same time, it causes a local IR drop phenomenon, and when the resistance value of a specific part of the power grid is particularly high, it will also cause a local IR drop; when the logic action in a certain area of ​​the chip causes an IR drop in other areas, it is called a global phenomenon.

[0004] IR drop problems often manifest themselves as timing or even signal integrity issues. If the global IR drop of a chip is too high, the logic gates will have functional failures, causing the chip to fail completely, even though logic simulation shows that the design is correct. Local IR drop is more sensitive and can only occur under certain conditions, such as when all bus data is flipped synchronously, so the chip will intermittently exhibit some functional failures. The most common effect of IR drop is that it reduces the speed of the chip.

[0005] In addition to voltage fluctuations, the current capacity that the power network connection can withstand is also an issue that must be considered in power supply design. For the metal layer that serves as the interconnection line, under a certain manufacturing process, the maximum current that can flow through it is limited. Otherwise, excessive current will cause the metal connection to fuse after a period of high current flowing through it, causing chip failure. This phenomenon is called electromigration (EM).

[0006] Electromigration (EM) is a term used to describe some of the failures that cause metal interconnects on a chip to break or melt. When electrons flow through a metal wire, they collide with atoms in the wire, which increases the resistance of the metal and generates heat. Electromigration (EM) is a long-term loss phenomenon that often manifests itself as timing or functional errors in the chip after a period of time. If a certain connection in a chip is unique, then when electromigration occurs, the entire chip will fail. If some connections have redundant designs, such as the power network, when electromigration occurs, some of the connections will be disconnected, while other parts of the connection will be subject to a larger IR drop problem. If electromigration causes a short circuit between lines, the entire chip will fail.

[0007] In the existing technology, the analysis of EM / IR in the power / ground layout relies on simulation technology to simulate the voltage of the corresponding points and solve the EM / IR information. The problem is that too many conditions are required: 1. The front-end engineer needs to provide a "virtual platform" testbench; 2. The back-end engineer needs to complete the layout and extract the special DSPF (Detailed Standard Parasitic Format) used for EM / IR calculation; 3. The result analysis and modification require the cooperation and iteration of the front-end and back-end engineers.

[0008] In addition, the traditional method of analyzing the current density and voltage drop of the power / ground layout requires calling the simulator, setting up a testbench for simulation to obtain the voltage and current points at the corresponding positions, and then obtaining the EM / IR at the corresponding positions. Summary of the invention

[0009] The present invention is made in view of the above problems. In view of the problems that the traditional analysis of current density, voltage drop, etc. in integrated circuit layout requires many steps and tools, the purpose of the present invention is to provide a method for rapid analysis of EM / IR of integrated circuit layout.

[0010] Solutions for solving technical problems

[0011] A method for rapidly analyzing EM / IR of an integrated circuit layout, comprising:

[0012] (1) Search for MOS tubes connected to the power / ground network in the integrated circuit layout;

[0013] (2) Screening and extracting effective MOS tubes in a normal saturation working state based on the searched MOS tubes;

[0014] (3) according to the size of the effective MOS tube, referring to the normalized load current of the MOS tube of a preset unit size, obtaining the load current corresponding to the effective MOS tube, and loading the obtained load current to the position where the power wiring of the effective MOS tube is located;

[0015] (4) extracting the resistor network of the configuration area of ​​the effective MOS tube based on the applied load current and establishing a resistor network matrix;

[0016] (5) calculating electrical index parameters for analyzing EM / IR in circuit wiring related to effective MOS tubes based on the resistor network matrix; and

[0017] (6) Output the EM / IR analysis results of the integrated circuit layout.

[0018] In one implementation of the present invention, for an effective MOS tube composed of multiple single gates, multiple load currents corresponding to the multiple single gates are calculated respectively according to the sizes of the single gates, and the calculated multiple load currents are used as the load current of the effective MOS tube.

[0019] In one implementable manner of the present invention, a voltage excitation is applied to the input terminal of an effective MOS tube, and resistance information including metal, vias, contact holes, and active areas related to the effective MOS tube is extracted according to the load current loaded at the position of the effective MOS tube, and a resistance network matrix is ​​established based on the resistance information.

[0020] In one possible implementation of the present invention, step (5) includes: using the formula Calculate the voltage and power at each point in the circuit layout related to the effective MOS tube, where P i Represents the power of each point in the circuit layout related to the effective MOS tube, V i Represents the voltage at each point in the circuit wiring related to the effective MOS tube, θ ij represents the resistance value between the circuit wiring nodes related to the effective MOS tube, i, j = 1, 2...n, and

[0021] The current density of the circuit wiring related to the effective MOS tube is calculated according to the voltage and power.

[0022] The present invention also provides a device for quickly analyzing EM / IR of an integrated circuit layout, which includes a processing unit, a storage unit connected to the processing unit, and a display unit, wherein the processing unit includes:

[0023] An extraction module, which screens and extracts effective MOS tubes in a normal saturation region working state;

[0024] A load current loading module, which obtains a load current corresponding to the effective MOS tube according to the extracted size of the effective MOS tube and refers to a normalized load current of a MOS tube of a preset unit size, and loads the obtained load current to a position where a power wiring of the effective MOS tube is located;

[0025] A calculation module, which extracts the resistance network of the configuration area of ​​the effective MOS tube based on the applied load current and establishes a resistance network matrix, and calculates the electrical index parameters for analyzing EM / IR in the circuit wiring related to the effective MOS tube based on the resistance network matrix;

[0026] The output module is used to output the EM / IR analysis results of the integrated circuit layout.

[0027] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program is executed when running, and the method for rapidly analyzing the EM / IR of the integrated circuit layout according to any one of claims 1 to 5 is executed. Invented Effect .

[0028] The present invention can quickly evaluate the EM / IR of the power network of any module in a finished or semi-finished integrated circuit layout, and present to the user a graphical result of the robustness of the integrated circuit layout under the worst distribution condition.

[0029] The present invention simplifies the EM / IR analysis process of the integrated circuit layout, reduces the workload of front-end and back-end engineers, improves the efficiency of power supply design, and reduces costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The figure is a flow chart of the EM / IR method for rapidly analyzing integrated circuit layout according to the present invention.

[0031] Figure 2 The integrated circuit layout obtained for the present invention.

[0032] Figure 3 This is a schematic diagram of an effective MOS tube extracted by the present invention.

[0033] Figure 4The parameter information related to the effective MOS tube obtained by the present invention includes the loaded load current, rectangular area, etc.

[0034] Figure 5 The analysis results of the voltage drop distribution are shown for the present invention.

[0035] Figure 6 It is the value and position of the voltage excitation applied to the effective MOS tube by the present invention and the current value and position of the starting end of the voltage AVDD.

[0036] Figure 7 The analysis results of the current density shown for the present invention.

[0037] Figure 8 A block diagram of the processing unit of the apparatus for rapidly analyzing EM / IR of an integrated circuit layout according to the present invention. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0039] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0040] The EM / IR method for rapidly analyzing an integrated circuit layout of the present invention extracts effective MOS tubes connected to a power / ground network from an integrated circuit layout including power / ground, loads a load current corresponding to the effective MOS tube to a configuration area of ​​the effective MOS tube, extracts a resistance network corresponding to the wiring of the effective MOS tube and establishes a resistance network matrix, and then calculates a power spectrum and a voltage point at a corresponding coordinate position of the effective MOS tube using a matrix solver according to the resistance network matrix and a power supply excitation applied to the effective MOS, and then calculates electrical index values ​​such as current density and voltage drop in the integrated circuit layout at a corresponding position based on the resistance connected to the corresponding node, and graphically plots them.

[0041] The present invention can quickly evaluate the EM / IR of the power / ground network of any module (BLOCK) in the layout of a finished or semi-finished integrated circuit, and present to the user the graphical analysis results of the EM / IR of the robustness of the integrated circuit layout.

[0042] Figure 1 This is a flow chart of the EM / IR method for rapid analysis of integrated circuit layout according to the present invention. Figure 1 , the EM / IR method for rapid analysis of integrated circuit layout of the present invention is described in detail. The present invention comprises the following steps:

[0043] (1) Search for all MOS tubes connected to the power / ground network in the integrated circuit layout;

[0044] (2) extracting effective MOS tubes in a normal saturation working state from the searched MOS tubes;

[0045] In a specific embodiment of the present invention, for the searched MOS tubes, according to a predetermined rule, a part of the MOS tubes are filtered out, and the MOS tubes that meet the rule (ie, are in a normal saturation region working state) are left as effective MOS tubes (current loads) for analysis.

[0046] (3) For an effective MOS tube, assuming that the normalized load current of a MOS tube with a unit width-to-length ratio is I, if the width-to-length ratio of a single effective MOS is k, then the load current corresponding to this effective MOS is k*I.

[0047] The obtained load current k*I is loaded onto the location of the power wiring of the effective MOS tube.

[0048] (4) applying voltage excitation to the input end of the effective MOS tube, extracting the resistor network of the configuration area of ​​the effective MOS tube in the integrated circuit layout and establishing a resistor network matrix based on the obtained load current corresponding to the effective MOS tube (i.e., the load current loaded at the location where the power wiring of the effective MOS tube is located);

[0049] (5) Based on the established resistor network matrix and the voltage excitation input to the effective MOS tube, calculate the electrical index values ​​related to the effective MOS tube for EM / IR analysis;

[0050] (6) Output the EM / IR analysis results of the integrated circuit layout.

[0051] The present invention includes displaying solved electrical index values ​​such as voltage and current density spectrum at positions corresponding to effective MOS tubes in a graphical manner or the like.

[0052] In a specific embodiment of the present invention, the EM / IR method for rapid analysis of integrated circuit layout specifically includes the following steps:

[0053] First, in step 101, Figure 1 As shown, an integrated circuit layout including power / ground is obtained, and one or more effective MOS tubes in the integrated circuit layout that are connected to the power / ground network and are in a normal saturation region working state are screened and extracted.

[0054] In an embodiment of the present invention, all MOS tubes connected to the power / ground network in the integrated circuit layout are traversed and searched, and then, according to the set rules, it is determined (screened) one by one whether the searched MOS tubes are MOS tubes in a normal saturation region working state.

[0055] Specifically, the present invention extracts effective MOS tubes according to the set rules, including: (a) presetting some enable and shutdown signals Enable Signals (EN) / Power Down (PD). When screening MOS tubes, for the searched MOS tubes, if the gate (Gate) of the MOS tube is marked as PD or EN, the current MOS tube is filtered out; (b) MOS tubes with short-circuited source and drain are filtered out. It should be noted that the above-mentioned set rules are only an exemplary description of the present invention for extracting effective MOS tubes, and the set rules are not limited to the above description. As long as the set rules can extract MOS tubes in a normal saturation working state, they are applicable to the present invention.

[0056] like Figure 2 As shown, in the present invention, according to at least one of the above-mentioned setting rules, it is judged that the four MOS transistors M5, M6, M7 and M8 are in the normal saturation region working state, and therefore the four MOS transistors M5, M6, M7 and M8 are judged as effective MOS transistors.

[0057] In step 102, for the extracted effective MOS tube, a load current corresponding to the effective MOS tube is obtained.

[0058] In the embodiment of the present invention, the MOS transistor (M5, M6, M7, M8) is generally composed of multiple (for example, 4) finger gates (single gates). For the effective MOS transistor composed of multiple finger gates (single gates), multiple load currents corresponding to the multiple finger gates (single gates) are calculated respectively, and the calculated multiple load currents are used as the load current of the effective MOS transistor.

[0059] Specifically, for example, for the effective MOS tube M5, after finding the first finger gate (single gate) of the effective MOS tube M5 and the diffusion layer (active area) connected to the voltage AVDD side, at the intersection of the first finger gate (single gate) and the diffusion layer (active area), the first finger gate (single gate) edge is used as the starting point to move a predetermined distance to the diffusion layer (active area) side to set the center point coordinates of the rectangular area for loading the load current, and then based on the center point coordinates, the width of the first finger gate (single gate) is used as the long side of the rectangular area for loading the load current, and the width is 5 to 10 nm, and a rectangular area for recording the load current is established on the diffusion layer (active area). Next, according to the width-to-length ratio K of the first finger gate (single gate) multiplied by the normalized load current I of the MOS tube with a unit width-to-length ratio, the load current I1=k*I of the first finger gate (single gate) in the established rectangular area is obtained. Then repeat the above steps to obtain the load current I2…I of other finger gates (single gate) of the effective MOS M5 in the established rectangular area. n The calculated load current I1…I n Set to the effective MOS tube load current A5.

[0060] Preferably, the present invention stores the center point coordinates, size, process layer where the effective MOS tube M5 is placed, load current A5 and the identifier of the effective MOS tube M5 in association with the rectangular area for loading the load current associated with the effective MOS tube M5.

[0061] For other effective MOS transistors M6, M7, and M8, refer to the above processing steps for the effective MOS transistor M5 to calculate the load currents A6, A7, and A8 corresponding to the effective MOS transistors M6, M7, and M8 respectively.

[0062] Similarly, the center point coordinates, dimensions, process layers at which the effective MOS tubes M6, M7, M8 are placed, load currents A6, A7, A8 and identifiers of the effective MOS tubes M6, M7, M8 respectively associated with the effective MOS tubes M6, M7, M8 can be preferably stored in association with the rectangular areas for loading the load current.

[0063] Figure 4 An example is shown in which the above parameter information calculated for the extracted effective MOS transistors M5, M6, M7, and M8 are stored respectively: E1-E12.

[0064] In step 103, a voltage excitation is applied to the input end of the effective MOS tube, and based on the acquired load current corresponding to the effective MOS tube (i.e., the load current loaded at the circuit wiring position of the effective MOS tube), a resistor network is extracted from the configuration area of ​​the effective MOS tube and a resistor network matrix is ​​established.

[0065] Specifically, in the present invention, voltage excitation is applied to the input terminals of the effective MOS tubes M5, M6, M7, and M8, and according to the load currents A5, A6, A7, and A8 corresponding to the effective MOS tubes M5, M6, M7, and M8 respectively obtained in step 102, resistance information including metal, via, contact, and diffusion related to the effective MOS tubes M5, M6, M7, and M8 in the integrated circuit layout is extracted to establish a resistance network matrix R:

[0066]

[0067] Among them, θ 11 …θ nn Indicates the resistance value between nodes in the circuit wiring related to the effective MOS tubes M5, M6, M7, and M8.

[0068] In step 104, based on the established resistor network matrix R and the voltage stimulus input to the effective MOS tube, the electrical index value related to the effective MOS tube for EM / IR analysis is calculated.

[0069] In a specific embodiment of the present invention, a matrix solver is called to solve the established resistor network matrix R to calculate the voltage and power of each point in the circuit wiring related to the effective MOS tubes M5, M6, M7, and M8.

[0070] Specifically, voltage excitation is applied to the input terminals of the effective MOS tubes M5, M6, M7, and M8, and the Kirchhoff equation is used to solve the above resistance network R:

[0071] Among them, P i Represents the power of each point in the circuit layout related to the effective MOS tubes M5, M6, M7, and M8, V i represents the voltage of each point in the circuit wiring related to the effective MOS tubes M5, M6, M7, and M8, θ ij Represents the resistance value between the circuit wiring nodes related to the effective MOS tubes M5, M6, M7, and M8, i, j = 1, 2...n.

[0072] In the present invention, the voltage value across each resistor is first obtained, the current flowing through each resistor is calculated, the power of each point is calculated according to formula (1), and then the current density of the circuit wiring related to the effective MOS tubes M5, M6, M7, and M8 in the integrated circuit layout is calculated according to the voltage and power.

[0073] In step 105, the visual analysis result of EM / IR of the integrated circuit layout is output.

[0074] In the specific implementation of the present invention, after the solution is completed, the analysis results of the EM / IR characteristics of the integrated circuit layout are output. Specifically, the analysis results of the voltage drop of the display voltage AVDD are output. Figure 5 As shown in the figure, different grayscales represent different voltage drop distributions; the second shows the analysis results of the current, such as Figure 6 As shown, it shows the value and position of the voltage excitation applied to the effective MOS tube and the current value and position of the starting end of the voltage AVDD; the third shows the analysis results of the current density, such as Figure 7 As shown, the current density of each layer of metal conductors and vias in the integrated circuit layout is displayed to determine whether the power lines and vias meet the requirements of the wafer foundry for electrical mobility and ensure the safety of chip design.

[0075] The method for quickly analyzing the EM / IR of the power / ground layout involved in the present invention is implemented, for example, by a computer terminal installed with dedicated application software (multiple applications such as the power / ground layout design program involved in the present invention and the EM / IR for quickly analyzing the power / ground layout). The computer terminal can realize the functions described later by executing processing related to multiple applications, including the hardware resources required to realize the functions. The computer terminal has an input device, a display device, an external I / F, a communication I / F, a processor, and a memory. These hardware are connected to each other in a manner that can communicate via a bus.

[0076] The input device is, for example, a keyboard, a mouse, a touch panel, etc. The display device is, for example, various types of flat panel displays.

[0077] The processor is a computer's internal CPU, or a dedicated CPU, DSP, or other processing unit. The memory device includes a computer-readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0078] The computer can communicate with the server through a network. The computer and the server can be used to execute the method for quickly analyzing the power / ground layout EMIR provided in this application. The computer and the server can also be used to collaboratively execute the computer provided in this application. For example, the server can transmit the integrated circuit layout required for the method for quickly analyzing the power / ground layout EMIR to the computer. The computer can also send the analysis results of the power / ground layout MIR to the server.

[0079] In one embodiment, the present invention also provides a device for quickly analyzing the EM / IR of a power / ground layout, which includes a processing unit, a storage unit, and a display unit. Figure 8 As shown, the processing unit includes: an extraction module 101, a load current loading module 102, a calculation module 103, and an output module 104. Among them:

[0080] An extraction module 101 is used to screen and extract effective MOS tubes in a normal saturation region working state;

[0081] A load current loading module 102, which obtains a load current corresponding to the effective MOS tube according to the extracted size of the effective MOS tube and refers to a normalized load current of a MOS tube of a preset unit size, and loads the obtained load current to a position where a power wiring of the effective MOS tube is located;

[0082] A calculation module 103, which extracts the resistance network of the configuration area of ​​the effective MOS tube based on the applied load current and establishes a resistance network matrix, and calculates electrical index parameters for analyzing EM / IR in the circuit wiring related to the effective MOS tube based on the resistance network matrix;

[0083] The output module 104 is used to output the EM / IR analysis results of the integrated circuit layout.

[0084] For other specific limitations of the device for rapid analysis of EM / IR of power / ground layout described in the present invention, please refer to the limitations of the method for rapid analysis of EM / IR of power / ground layout described in the present invention, which will not be repeated here. Each module in the above-mentioned device for rapid analysis of EM / IR of power / ground layout can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0085] In one embodiment of the present invention, the present invention further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is run, the method for rapid EM / IR analysis of an integrated circuit layout as described above is executed.

[0086] Those skilled in the art can understand that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention is described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions recorded in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for rapid analysis of EM / IR of integrated circuit layout, characterized in that: include: (1) Search for MOS tubes connected to the power / ground network in the integrated circuit layout; (2) Screening and extracting effective MOS tubes in normal saturation working state based on the searched MOS tubes; (3) according to the size of the effective MOS tube, referring to the normalized load current of the MOS tube of a preset unit size, obtaining the load current corresponding to the effective MOS tube, and loading the obtained load current to the position where the power wiring of the effective MOS tube is located; (4) extracting a resistance network of the configuration area of ​​the effective MOS tube based on the loaded load current and establishing a resistance network matrix, wherein a voltage excitation is applied to the input end of the effective MOS tube, and according to the load current loaded at the position of the effective MOS tube, resistance information related to the effective MOS tube including metal, via, contact hole, and active area is extracted, and the resistance network matrix is ​​established based on the resistance information; (5) Calculating electrical index parameters for analyzing EM / IR in circuit wiring related to effective MOS tubes based on the resistor network matrix, the step (5) comprises: using formula P i = i / θ ij Calculate the voltage and power at each point in the circuit layout related to the effective MOS tube, where P i Represents the power of each point in the circuit layout related to the effective MOS tube, V i Represents the voltage at each point in the circuit wiring related to the effective MOS tube, θ ij Representing the resistance value between the circuit wiring nodes related to the effective MOS tube, i, j=1, 2...n, and calculating the current density of the circuit wiring related to the effective MOS tube according to the voltage and power; and (6) Output the EM / IR analysis results of the integrated circuit layout.

2. The method for rapid analysis of EM / IR of integrated circuit layout according to claim 1, characterized in that: For an effective MOS tube composed of a plurality of single gates, a plurality of load currents corresponding to the plurality of single gates are calculated respectively according to the size of the single gates, and the calculated plurality of load currents are used as the load current of the effective MOS tube.

3. A device for rapidly analyzing EM / IR of an integrated circuit layout, comprising a processing unit, a storage unit connected to the processing unit, and a display unit, characterized in that: The processing unit comprises: An extraction module, which screens and extracts effective MOS tubes in a normal saturation region working state; A load current loading module, which obtains a load current corresponding to the effective MOS tube according to the extracted size of the effective MOS tube and refers to a normalized load current of a MOS tube of a preset unit size, and loads the obtained load current to a position where a power wiring of the effective MOS tube is located; A calculation module is provided, which extracts the resistance network of the configuration area of ​​the effective MOS tube based on the loaded load current and establishes a resistance network matrix, and calculates the electrical index parameters for analyzing EM / IR in the circuit wiring related to the effective MOS tube based on the resistance network matrix, wherein a voltage excitation is applied to the input end of the effective MOS tube, and according to the load current loaded at the position of the effective MOS tube, the resistance information related to the effective MOS tube including metal, via, contact hole, and active area is extracted, and the resistance network matrix is ​​established based on the resistance information, and the calculation module uses formula P i = i / θ ij Calculate the voltage and power of each point in the circuit wiring related to the effective MOS tube, where P i Represents the power of each point in the circuit layout related to the effective MOS tube, V i Represents the voltage at each point in the circuit wiring related to the effective MOS tube, θ ij Representing the resistance value between the circuit wiring nodes related to the effective MOS tube, i, j=1, 2...n, and calculating the current density of the circuit wiring related to the effective MOS tube according to the voltage and power; The output module is used to output the EM / IR analysis results of the integrated circuit layout.

4. The device for rapid analysis of EM / IR of integrated circuit layout according to claim 3, characterized in that: For an effective MOS tube composed of multiple single gates, the load current loading module calculates multiple load currents corresponding to the multiple single gates according to the size of the single gates, and uses the calculated multiple load currents as the load current of the effective MOS tube.

5. A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed, executes the method for rapid EM / IR analysis of an integrated circuit layout as claimed in claim 1 or 2.

Images