A method for measuring eye height of NRZ eye diagram and CDR lock detection circuit

Abstract

The present application provides an eye height measurement method of an NRZ eye diagram and a CDR lock detection circuit, belonging to the field of communication technology, the method comprising: when a clock data recovery circuit is in a locked state, taking the middle level of the NRZ signal as the initial value of the first threshold and the second threshold; performing a first type of single adjustment on the first threshold and the second threshold, increasing the first threshold to obtain the first target threshold, and reducing the second threshold to obtain the second target threshold; calculating the actual transition density corresponding to the first target threshold and the second target threshold; determining whether the actual transition density is greater than the expected transition density; if the actual transition density is greater than the expected transition density, determining the difference between the first target threshold and the second target threshold as the internal eye height of the NRZ eye diagram. By adopting the above-mentioned eye height measurement method of the NRZ eye diagram and the CDR lock detection circuit, the problem of low efficiency of eye height measurement of the NRZ eye diagram is solved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an eye height measurement method of an NRZ eye diagram and a CDR lock detection circuit. Background Art

[0002] With the rapid development of communication technology, the demand for data bandwidth is increasing, which has led to the electronic system changing from the traditional parallel bus to the serial bus. Serial data transmission has the characteristics of fewer signal lines and low cost. At present, the more common serial signal is the NRZ signal, and the eye diagram is used to describe the NRZ signal. The eye diagram contains rich information. From the eye diagram, the influence of inter-code crosstalk and noise can be observed, which reflects the overall characteristics of the digital signal, so as to estimate the quality of the digital system transmission performance. Eye diagram analysis is the core of the signal integrity analysis of high-speed interconnection systems. In the eye diagram analysis, eye height is an important indicator of eye diagram analysis. The traditional eye height measurement method is to measure the NRZ signal multiple times through an oscilloscope to obtain a large amount of data, and then restore the eye diagram data of the NRZ signal based on these data, and determine the eye height based on the eye diagram data.

[0003] However, the above-mentioned method for measuring eye height not only requires multiple measurements, but also requires the use of measurement data to restore the eye diagram. The whole process takes a long time, resulting in the problem of low efficiency in measuring the eye height of the NRZ eye diagram. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide an eye height measurement method of an NRZ eye diagram and a CDR lock detection circuit to solve the problem of low efficiency in eye height measurement of an NRZ eye diagram.

[0005] In a first aspect, an embodiment of the present application provides an eye height measurement method of an NRZ eye diagram, comprising:

[0006] When the clock data recovery circuit is in a locked state, the middle level of the NRZ signal is used as the initial value of the first threshold and the second threshold;

[0007] Performing a first type of single adjustment on the first threshold and the second threshold, increasing the first threshold to obtain a first target threshold, and decreasing the second threshold to obtain a second target threshold;

[0008] Calculating the actual transition density corresponding to the first target threshold and the second target threshold;

[0009] determining whether the actual transition density is greater than the expected transition density;

[0010] If the actual transition density is greater than the expected transition density, the difference between the first target threshold and the second target threshold is determined as the inner eye height of the NRZ eye diagram.

[0011] Optionally, after determining whether the actual transition density is greater than the expected transition density, it also includes: if the actual transition density is not greater than the expected transition density, using the first target threshold as the new first threshold and the second target threshold as the new second threshold; returning to perform the first type of single adjustment step on the first threshold and the second threshold.

[0012] Optionally, after determining the difference between the first target threshold and the second target threshold as the internal eye height of the NRZ eye diagram, it also includes: performing a second type of single adjustment on the first threshold and the second threshold, increasing the first threshold to obtain the first target threshold, and reducing the second threshold to obtain the second target threshold; calculating the actual transition density corresponding to the first target threshold and the second target threshold; determining whether the actual transition density is less than the expected transition density; if the actual transition density is less than the expected transition density, determining the difference between the first target threshold and the second target threshold as the external eye height of the NRZ eye diagram.

[0013] Optionally, a first type of single adjustment is performed on the first threshold and the second threshold, the first threshold is increased to obtain the first target threshold, and the second threshold is reduced to obtain the second target threshold, or a second type of single adjustment is performed on the first threshold and the second threshold, the first threshold is increased to obtain the first target threshold, and the second threshold is reduced to obtain the second target threshold, including: determining the adjustment step; adding the first threshold to the adjustment step to achieve a single adjustment of the first threshold, and determining the result of the addition as the first target threshold; subtracting the second threshold from the adjustment step to achieve a single adjustment of the second threshold, and determining the result of the subtraction as the second target threshold.

[0014] Optionally, after determining whether the actual transition density is less than the expected transition density, it also includes: if the actual transition density is not less than the expected transition density, using the first target threshold as the new first threshold and the second target threshold as the new second threshold; returning to perform the step of performing the second type of single adjustment on the first threshold and the second threshold.

[0015] Optionally, the actual transition density corresponding to the first target threshold and the second target threshold is calculated, including: using the clock signal to sample the NRZ signal to obtain the NRZ signal level, comparing the NRZ signal level with the first target threshold and the second target threshold respectively, to obtain a first comparison result and a second comparison result; determining the output signal corresponding to the NRZ signal level according to the logical relationship between the first comparison result and the second comparison result; determining the number of transitions of adjacent output signals and the number of clock signals in the output signal, the transition of adjacent output signals being the numerical change between the nth output signal and the n-1th output signal or the nth output signal and the n+1th output signal; when the number of clock signals reaches the set threshold, determining the ratio of the number of level transitions of the output signal to the number of clock signals as the actual transition density.

[0016] Optionally, determining an output signal corresponding to the NRZ signal level according to a logical relationship between the first comparison result and the second comparison result includes: inverting the second comparison result; performing a NOR operation on the inverted second comparison result and the first comparison result to determine the output signal.

[0017] Optionally, the number of level transitions includes the number of rising edges and / or the number of falling edges; the ratio of the number of transitions of the output signal to the number of clock signals is determined as the actual transition density, including: if the number of rising edges or the number of falling edges of the output signal is determined, the ratio of the number of rising edges to the number of clock signals is used as the actual transition density, or the ratio of the number of falling edges to the number of clock signals is used as the actual transition density; if the sum of the number of rising edges and the number of falling edges of the output signal is determined, the ratio of the sum to the number of clock signals is used as the actual transition density.

[0018] Optionally, the sum of the first threshold and the second threshold is 1.

[0019] In a second aspect, an embodiment of the present application further provides a CDR circuit lock detection circuit, the circuit comprising a first comparison trigger, a second comparison trigger, a logic circuit and a statistical circuit, the first comparison trigger and the second comparison trigger are comparison triggers with thresholds;

[0020] The clock signal output by the CDR circuit is input to the clock control terminals of the first comparison trigger and the second comparison trigger respectively;

[0021] The NRZ signal is input to the data input terminals of the first comparison trigger and the second comparison trigger respectively;

[0022] An output terminal of the first comparison trigger and an output terminal of the second comparison trigger are respectively connected to a first input terminal and a second input terminal of the logic circuit;

[0023] The first input terminal of the statistical circuit is connected to the output terminal of the logic circuit, and the second input terminal of the statistical circuit receives the clock signal output by the CDR circuit.

[0024] The embodiments of the present application bring the following beneficial effects:

[0025] An eye height measurement method for an NRZ eye diagram and a CDR lock detection circuit provided in an embodiment of the present application can synchronously adjust a first threshold and a second threshold, gradually increase the first threshold, and gradually decrease the second threshold, and determine the actual transition density corresponding to the first target threshold and the second target threshold after each adjustment, compare the actual transition density with the expected transition density, and when the actual transition density is greater than the expected transition density, use the difference between the first target threshold and the second target threshold at this time as the internal eye height. Compared with the eye height measurement method for the NRZ eye diagram in the prior art, the problem of low efficiency in eye height measurement of the NRZ eye diagram is solved.

[0026] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 A flow chart of the eye height measurement method of the NRZ eye diagram provided in an embodiment of the present application is shown;

[0029] Figure 2 A schematic diagram showing the adjustment process of the first threshold and the second threshold provided in an embodiment of the present application;

[0030] Figure 3 A schematic diagram showing the structure of the NRZ eye diagram provided in an embodiment of the present application is shown;

[0031] Figure 4 A circuit diagram of a CDR lock detection circuit provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0032] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application usually described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, each other embodiment obtained by those skilled in the art without making creative work belongs to the scope of protection of the present application.

[0033] It is worth noting that before the present application was proposed, with the rapid development of communication technology, the demand for data bandwidth has increased day by day, which has led to the electronic system changing from the traditional parallel bus to the serial bus. Serial data transmission has the characteristics of a small number of signal lines and low cost. At present, the more common serial signal is the NRZ signal, and the eye diagram is used to describe the NRZ signal. The eye diagram contains rich information. The influence of inter-code crosstalk and noise can be observed from the eye diagram, which reflects the overall characteristics of the digital signal, so that the quality of the digital system transmission performance can be estimated. Eye diagram analysis is the core of the signal integrity analysis of the high-speed interconnection system. In the eye diagram analysis, the eye height is an important indicator of the eye diagram analysis. The traditional eye height measurement method is to measure the NRZ signal multiple times through an oscilloscope to obtain a large amount of data, and then restore the eye diagram data of the NRZ signal based on these data, and determine the eye height based on the eye diagram data. However, the above-mentioned method of measuring the eye height not only requires multiple measurements, but also requires the use of the measured data to restore the eye diagram. The whole process takes a lot of time, resulting in the problem of low efficiency of the eye height measurement of the NRZ eye diagram.

[0034] Based on this, an embodiment of the present application provides an eye height measurement method for an NRZ eye diagram to improve the efficiency of eye height measurement of an NRZ eye diagram.

[0035] See also Figure 1 , Figure 1 Flow chart of a method for measuring the eye height of an NRZ eye diagram provided in an embodiment of the present application. Figure 1 As shown, the eye height measurement method of the NRZ eye diagram provided in the embodiment of the present application includes:

[0036] Step S101: When the clock data recovery circuit is in a locked state, the middle level of the NRZ signal is used as the initial value of the first threshold and the second threshold.

[0037] In this step, the clock data recovery circuit may be referred to as a CDR (Clock Data Recovery, CDR) circuit.

[0038] The clock data recovery circuit is an important module at the data receiving end in serial data communication. The clock data recovery circuit mainly completes two tasks, one is clock recovery and the other is data recovery.

[0039] Among them, clock recovery refers to the clock recovery of the data input to the CDR circuit, so that the recovered clock has the same clock frequency as the input data, and is phase-locked to the middle of the eye diagram for sampling, so that the correct data can be sampled through the comparison trigger, thereby recovering the data.

[0040] The locked state means that the frequency and phase of the clock recovered by the clock data recovery circuit are correct and synchronized with the frequency and phase of the input data signal, that is, the clock signal and the data signal are locked.

[0041] NRZ signal is a digital logic signal that uses high and low signal levels to represent the transmitted information. It is a line code used to represent bits 0 and 1. Positive voltage represents logic 1, and negative voltage represents logic 0.

[0042] The middle level may refer to a level between the set low level 0 and the high level 1. Exemplarily, the middle level is 1 / 2.

[0043] The first threshold may refer to a threshold corresponding to a first comparison trigger in the CDR lock detection circuit, and the first threshold is used to compare with the level of the NRZ signal to determine a first comparison result.

[0044] The second threshold may refer to a threshold corresponding to a second comparison trigger in the CDR lock detection circuit, and the second threshold is used to compare with the level of the NRZ signal to determine a second comparison result.

[0045] The CDR lock detection circuit may refer to a circuit used to determine whether the clock data recovery circuit is in a locked state, that is, whether the clock signal is locked with the input data signal, and whether the clock frequency and phase recovered by the CDR circuit are synchronized with the input data signal clock and frequency by using the CDR lock detection circuit. When the clock phase and frequency recovered by the CDR circuit are synchronized with the frequency and phase of the input data signal, it is determined that the two have reached a locked state. At this time, when the clock signal recovered by the CDR is used to sample the data signal, the phase of the clock is located in the middle of the NRZ signal eye diagram.

[0046] In the embodiment of the present application, the CDR lock detection circuit is first used to determine whether the clock data recovery circuit is in a locked state. If the clock data recovery circuit is in a locked state, the first threshold corresponding to the first comparison trigger in the CDR lock detection circuit is set to 1 / 2, and at the same time, the second threshold corresponding to the second comparison trigger in the CDR lock detection circuit is also set to 1 / 2. The first threshold and the second threshold are both stored in a register.

[0047] Step S102: performing a first type of single adjustment on the first threshold and the second threshold, increasing the first threshold to obtain a first target threshold, and decreasing the second threshold to obtain a second target threshold.

[0048] In this step, the first type of single adjustment may refer to the adjustment adopted when the actual transition density gradually increases but does not exceed the expected transition density. The first type of single adjustment is used to gradually increase the actual transition density until it exceeds the expected transition density for the first time to determine the inner eye height of the NRZ eye diagram.

[0049] The first target threshold may refer to a threshold obtained after a single adjustment of the first threshold. The first target threshold is used as a new first threshold to continue adjusting based on the new first threshold.

[0050] The second target threshold may refer to a threshold obtained after a single adjustment of the second threshold. The second target threshold is used as a new second threshold to continue adjusting based on the new second threshold.

[0051] Refer to the following Figure 2 The adjustment process of the first threshold and the second threshold will be introduced below.

[0052] Figure 2 A schematic diagram of the adjustment process of the first threshold and the second threshold provided in an embodiment of the present application is shown.

[0053] like Figure 2 As shown, the middle value of the high level 1 and the low level 0 in the NRZ eye diagram is 1 / 2, that is, the middle level. The initial values ​​of the first threshold and the second threshold are both set to the middle level, that is, set to 1 / 2, and then the value of the first threshold is increased once, so that the value of the first threshold moves upward to obtain the first target threshold, and the value of the second threshold is reduced once, so that the value of the second threshold moves downward to obtain the second target threshold.

[0054] In an optional embodiment, the sum of the first threshold and the second threshold is 1.

[0055] Specifically, the numerical relationship between the first threshold and the second threshold may be set so that the sum of the first threshold and the second threshold is 1, and the numerical value of the increase in the first threshold is equal to the numerical value of the decrease in the second threshold.

[0056] In an optional embodiment, a first type of single adjustment is performed on the first threshold and the second threshold, the first threshold is increased to obtain the first target threshold, and the second threshold is reduced to obtain the second target threshold, including: determining the adjustment step; adding the first threshold to the adjustment step to achieve a single adjustment of the first threshold, and determining the result of the addition as the first target threshold; subtracting the second threshold from the adjustment step to achieve a single adjustment of the second threshold, and determining the result of the subtraction as the second target threshold.

[0057] Here, the adjustment step may refer to the value by which the first threshold is increased and the value by which the second threshold is decreased each time the values ​​of the first threshold and the second threshold are adjusted.

[0058] Specifically, taking the adjustment step of 0.1 as an example, since the initial values ​​of the first threshold and the second threshold are both 1 / 2, after the first adjustment, the first threshold increases by 0.1 equals to 0.6, that is, the first target threshold after the first adjustment is 0.6, and the second threshold decreases by 0.1 equals to 0.4, that is, the second target threshold after the first adjustment is 0.4.

[0059] Step S103, calculating the actual transition density corresponding to the first target threshold and the second target threshold;

[0060] In this step, the actual transition density may refer to the transition density of the NRZ signal level, and the transition density may refer to the proportion of the number of level transitions to the total number of signals.

[0061] Specifically, the input NRZ signal is sampled using the clock signal recovered by the locked CDR to obtain the NRZ signal level, and the NRZ signal level is compared with the first target threshold and the second target threshold respectively, and the output signal is obtained according to the comparison result, and the ratio of the number of transitions of the output signal to the number of clock signals is determined, and the ratio is used as the actual transition density. The above method for calculating the actual transition density can be implemented using a CDR lock detection circuit.

[0062] In an optional embodiment, the actual transition density corresponding to the first target threshold and the second target threshold is calculated, including: using the clock signal to sample the NRZ signal to obtain the NRZ signal level, comparing the NRZ signal level with the first target threshold and the second target threshold respectively, to obtain a first comparison result and a second comparison result; determining the output signal corresponding to the NRZ signal level according to the logical relationship between the first comparison result and the second comparison result; determining the number of transitions of adjacent output signals and the number of clock signals in the output signal, the transition of adjacent output signals being the numerical change between the nth output signal and the n-1th output signal or the nth output signal and the n+1th output signal; when the number of clock signals reaches the set threshold, determining the ratio of the number of transitions of the output signal to the number of clock signals as the actual transition density.

[0063] Here, the first comparison result may refer to a comparison result of the NRZ signal level and the first target threshold value.

[0064] The second comparison result may refer to a comparison result of the NRZ signal level with the second target threshold value.

[0065] The logical relationship may refer to whether the first comparison result is the same as the second comparison result.

[0066] The number of transitions between adjacent output signals may refer to the number of transitions from 0→1 or from 1→0 of the levels of adjacent output signals.

[0067] Specifically, when the NRZ signal is sampled using the CDR clock signal, the NRZ signal is sampled at the edges (rising edge and falling edge) of the CDR clock signal. The number of CDR clock signals can be regarded as the number of samples of the NRZ signal sampled by the clock signal, that is, the number of edges.

[0068] The number of CDR clock signals or the number of cycles of CDR clock signals can be obtained by counting the number of rising edges or falling edges in the clock signal. When the rising edge of the clock signal is counted, the number of CDR clock signals is increased by 1 for each rising edge of the clock signal, that is, the number of clock signals is continuously accumulated. When the falling edge of the clock signal is counted, the number of CDR clock signals is increased by 1 for each falling edge of the clock signal, that is, the number of clock signals is continuously accumulated.

[0069] In the CDR lock detection circuit, the NRZ signal is input into the CDR lock detection circuit, and the level of the NRZ signal is represented by a logic bit. For each logic bit value, the logic bit value is respectively input into a first comparison trigger and a second comparison trigger of the CDR lock detection circuit, and the logic bit is compared with a first target threshold corresponding to the first comparison trigger to obtain a first comparison result, and the logic bit is compared with a second target threshold corresponding to the second comparison trigger to obtain a second comparison result.

[0070] When comparing the logic bit value with the target threshold, if the logic bit value is greater than the target threshold, the comparison result is 1; otherwise, if the logic bit value is less than or equal to the target threshold, the comparison result is 0.

[0071] After determining the first comparison result and the second comparison result, the first comparison result and the second comparison result are input into the logic circuit, and the logic circuit determines the value of the output signal according to the logical relationship between the first comparison result and the second comparison result. If the first comparison result is the same as the second comparison result, the output signal is 0; if the first comparison result is different from the second comparison result, the output signal is 1.

[0072] The NRZ signal is represented by a series of logic bit values, which correspond to multiple output signals. At the same time, the clock signal output by the CDR is also input into the CDR lock detection circuit. The statistical circuit in the CDR lock detection circuit continuously counts the number of transitions of the output signal and the number of clock signals. When the number of CDR clock signals reaches the set threshold, for example, when it reaches 30,000, that is, before the divider, the number of CDR clock signals is 30,000 bits (bit), the number of CDR clock signals output after the divider is counted at this time, that is, the set threshold is 30,000 / set divisor, where the set divisor refers to the built-in divisor of the divider, that is, the frequency reduction ratio, for example, the set divisor can be 2 or 4 or 8, or 256, or 1024. When the set divisor is 2, the threshold is set to 15,000.

[0073] The ratio of the number of transitions of the output signal to the number of clock signals is determined as the actual transition density. Then, the number of transitions of the output signal and the number of clock signals in the next counting cycle are counted again.

[0074] In an optional embodiment, the output signal corresponding to the NRZ signal level is determined based on the logical relationship between the first comparison result and the second comparison result, including: inverting the second comparison result; performing an OR operation on the inverted second comparison result and the first comparison result to determine the output signal.

[0075] Here, after determining the second comparison result, the second comparison result can be inverted first. If the second comparison result is 1, it is inverted to 0. If the second comparison result is 0, it is inverted to 1. Then, the inverted second comparison result and the first comparison result are OR-inverted to obtain the value of the output signal.

[0076] When the first comparison result is 1 and the second comparison result is 1, the second comparison result is negated to be 0, and an OR operation is performed on the first comparison result 1 and the negated second comparison result 0 to obtain an output result of 0.

[0077] When the first comparison result is 1 and the second comparison result is 1, the second comparison result is negated to be 0, and an OR operation is performed on the first comparison result 1 and the negated second comparison result 0 to obtain an output result of 0.

[0078] When the first comparison result is 0 and the second comparison result is 1, the second comparison result is negated to be 0, and an OR operation is performed on the first comparison result 0 and the negated second comparison result 0 to obtain an output result of 1.

[0079] When the first comparison result is 0 and the second comparison result is 0, the second comparison result is negated to be 1, and an OR operation is performed on the first comparison result 0 and the negated second comparison result 1 to obtain an output result of 0.

[0080] It can be seen that if the first comparison result is the same as the second comparison result, the output signal is 0, and if the first comparison result is different from the second comparison result, the output signal is 1. The above method for determining the output result can be implemented by a logic circuit in the CDR lock detection circuit, and the logic circuit includes an inverter for inverting the second comparison result, and a NOR gate circuit for performing a NOR operation on the inverted second comparison result and the first comparison result.

[0081] In an optional embodiment, the number of level transitions includes the number of rising edges and / or the number of falling edges; the ratio of the number of transitions of the output signal to the number of clock signals is determined as the actual transition density, including: if the number of rising edges or the number of falling edges of the output signal is determined, the ratio of the number of rising edges to the number of clock signals is used as the actual transition density, or the ratio of the number of falling edges to the number of clock signals is used as the actual transition density; if the sum of the number of rising edges and the number of falling edges of the output signal is determined, the ratio of the sum to the number of clock signals is used as the actual transition density.

[0082] Here, the number of transitions of adjacent output signals includes the number of rising edges of the adjacent output signals when the level jumps from 0 to 1, and / or the number of falling edges when the level jumps from 1 to 0. When determining the actual transition density, the number of rising edges or the number of falling edges can be used for calculation alone, or the sum of the number of rising edges and the number of falling edges can be used for calculation.

[0083] It should be noted that, under normal circumstances, different statistical methods for the number of transitions correspond to different expected transition densities. If the number of rising edges or falling edges is counted, it corresponds to the first expected transition density. If the number of rising edges and falling edges is counted, it corresponds to the second expected transition density, and the first expected transition density should be half of the second expected transition density. However, since the NRZ signal has only two levels, high and low, and the output signal value is 0 when the CDR circuit is in the locked state, the expected transition density should be set to 0, and there is no need to distinguish between the first expected transition density and the second expected transition density.

[0084] Step S104, determining whether the actual transition density is greater than the expected transition density;

[0085] In this step, the expected transition density may refer to an expected value of the transition density, and the expected transition density is used as a comparison standard.

[0086] From the above analysis, it can be seen that when the CDR circuit is in the locked state, the value of the output signal should be 0, and the expected transition density can be set to 0. However, since the unbounded characteristics of random noise and jitter satisfy the characteristics of Gaussian distribution, there will always be a certain probability of error as the amount of data increases, and it will not be the theoretical transition density, so the expected transition density can be set to a value higher than 0, for example: 0.1, 0.08, that is, when the actual transition density is in the range of 0 to 0.1, it can be determined that the CDR circuit is in the locked state.

[0087] In the embodiment of the present application, after the actual transition density is determined by the statistical circuit, a comparison is made to see whether the actual transition density is greater than the expected transition density.

[0088] In an optional embodiment, after determining whether the actual transition density is greater than the expected transition density, it also includes: if the actual transition density is not greater than the expected transition density, using the first target threshold as the new first threshold, and using the second target threshold as the new second threshold; returning to perform the first type of single adjustment step of the first threshold and the second threshold.

[0089] Taking the above example, the adjustment step is 0.1. After the first first-type single adjustment, the first threshold increases by 0.1, which is equal to 0.6, that is, the first target threshold is 0.6 after the first first-type single adjustment, and the second threshold decreases by 0.1, which is equal to 0.4, that is, the second target threshold is 0.4 after the first first-type single adjustment. It is determined that the actual transition density is 0.05 when the first target threshold is 0.6 and the second target threshold is 0.4. Since 0.05 is less than 0.1, the second first-type single adjustment is continued.

[0090] When performing the second first-type single adjustment, 0.6 is used as the new first threshold value, and 0.4 is used as the new second threshold value. The new first threshold value 0.6 is increased by 0.1 to obtain 0.7, that is, the first target threshold value after the second adjustment is 0.7, and the new second threshold value 0.4 is reduced by 0.1 to obtain 0.3, that is, the second target threshold value after the second adjustment is 0.3. It is determined whether the actual transition density obtained when the first target threshold value is 0.7 and the second target threshold value is 0.3 is not greater than 0.1. If it is still not greater than 0.1, the first-type single adjustment threshold, the determination of the actual transition density, and the comparison of the actual transition density with the expected transition density are continued in a loop until the actual transition density is greater than the expected transition density. At this time, the internal eye height of the NRZ eye diagram can be determined.

[0091] Step S105: if the actual transition density is greater than the expected transition density, the difference between the first target threshold and the second target threshold is determined as the inner eye height of the NRZ eye diagram.

[0092] In this step, the internal eye height may refer to the internal height of the eye in the NRZ eye diagram.

[0093] It should be noted that the amplitude (width) and height of the NRZ eye diagram will be affected by the residual influence of noise ISI (inter symbol interference, ISI). When there is noise in the amplitude, the eye height will be reduced, that is, ISI causes the eye opening height to become smaller. At the same time, the threshold non-ideality of the comparison trigger in the CDR circuit will make the eye opening height of the NRZ eye diagram that actually enters the CDR sampling smaller. Therefore, the eye height of the eye diagram actually measured will not be 1, and it is more reasonable to obtain a value with a margin.

[0094] Refer to the following Figure 3 Let's introduce the eye height determination process of NRZ eye diagram.

[0095] Figure 3 A schematic diagram of the structure of the NRZ eye diagram provided in an embodiment of the present application is shown.

[0096] like Figure 3 As shown in the figure, after the NRZ signal is affected by noise, the eye width and internal eye height in the NRZ eye diagram will be reduced. What needs to be measured is the internal eye height indicated by the dotted line in the figure. Under the premise that the CDR circuit is already in the locked state, first set the first threshold and the second threshold to the middle level 1 / 2, and then adjust the two thresholds to move up and down respectively to obtain the first target threshold and the second target threshold, and set the expected transition density to 0.1. When the distance L between the first target threshold and the second target threshold is less than the eye height of the NRZ eye diagram, the actual transition density should be 0 in theory, that is, the actual transition density measured by the CRZ lock detection circuit should be less than the expected transition density 0.1, and the CRZ circuit remains locked.

[0097] As the first threshold and the second threshold continue to move upward and downward, the distance L between the first target threshold and the second target threshold begins to be greater than the internal eye height of the NRZ eye diagram, and the output signal changes from all 0s to a state with a small amount of 1s, that is, the actual transition density begins to be greater than the expected transition density. At this time, the CDR circuit is determined to be in an unlocked state, and the difference between the first target threshold and the second target threshold at this time is the internal eye height.

[0098] Depend on Figure 3 It can be seen that when the CDR circuit is in a locked state, the sampling phase is the locked sampling position indicated by the arrow in the figure. If the CDR circuit is not in a locked state, that is, it deviates from the position indicated by the arrow in the figure, it will cause the problem of inaccurate internal eye height measurement.

[0099] In an optional embodiment, after determining the difference between the first target threshold and the second target threshold as the internal eye height of the NRZ eye diagram, it also includes: performing a second type of single adjustment on the first threshold and the second threshold, increasing the first threshold to obtain the first target threshold, and reducing the second threshold to obtain the second target threshold; calculating the actual transition density corresponding to the first target threshold and the second target threshold; determining whether the actual transition density is less than the expected transition density; if the actual transition density is less than the expected transition density, determining the difference between the first target threshold and the second target threshold as the external eye height of the NRZ eye diagram.

[0100] Here, the second type of single adjustment may refer to an adjustment adopted after the actual transition density exceeds the expected transition density, and the second type of single adjustment is used to determine the outer eye height of the NRZ eye diagram.

[0101] The external eye height corresponds to Figure 3 The height indicated in .

[0102] Specifically, the first threshold and the second threshold are continuously adjusted to move to both sides. As the first threshold and the second threshold gradually move, the proportion of the value 1 in the output signal gradually increases. When the proportion of the value 0 and the value 1 in the output signal is substantially the same, the actual transition density obtained by the CDR lock detection circuit reaches the theoretical maximum value. Thereafter, as the first threshold and the second threshold continue to move upward and downward, the proportion of the value 1 in the output signal begins to be higher than the proportion of the value 0, and the actual transition density decreases accordingly. When the distance between the first target threshold and the second target threshold begins to be greater than the outer height of the eye diagram, the output signal changes from partially being the value 1 to being all the value 1. At this time, the actual transition density corresponding to the output signal should theoretically return to 0, that is, the actual transition density becomes less than the expected transition density. Therefore, when the actual transition density is less than the expected transition density, the difference between the corresponding first target threshold and the second target threshold is used as the outer height of the eye.

[0103] In an optional embodiment, a second type of single adjustment is performed on the first threshold and the second threshold, the first threshold is increased to obtain the first target threshold, and the second threshold is reduced to obtain the second target threshold, including: determining the adjustment step; adding the first threshold to the adjustment step to achieve a single adjustment of the first threshold, and determining the result of the addition as the first target threshold; subtracting the second threshold from the adjustment step to achieve a single adjustment of the second threshold, and determining the result of the subtraction as the second target threshold.

[0104] Specifically, similar to the first type of single adjustment, the adjustment step is still 0.1. Each time the second type of single adjustment is performed, the first threshold is increased by 0.1 to obtain the first target threshold after the second type of single adjustment, and the second threshold is reduced by 0.1 to obtain the second target threshold after the second type of single adjustment.

[0105] In an optional embodiment, after determining whether the actual transition density is less than the expected transition density, it also includes: if the actual transition density is not less than the expected transition density, using the first target threshold as the new first threshold and the second target threshold as the new second threshold; returning to perform the second type of single adjustment step of the first threshold and the second threshold.

[0106] Taking the above example, the adjustment step is 0.1. After the internal eye height is determined and the first second-type single adjustment is performed, a new first target threshold and a second target threshold are obtained, and the actual transition density corresponding to the new first target threshold and the second target threshold is determined. Assuming that the actual transition density is 0.3, since 0.3 is greater than 0.1, the second second-type single adjustment is continued.

[0107] When performing the second second-type single adjustment, determine whether the actual transition density corresponding to the first target threshold and the second target threshold after the second second-type single adjustment is not less than 0.1. If it is still greater than 0.1, continue to loop the third second-type single adjustment, as well as the process of determining the actual transition density and comparing the actual transition density with the expected transition density until the actual transition density is less than the expected transition density. At this time, the external eye height of the NRZ eye diagram can be determined.

[0108] Compared with the eye height measurement method of the NRZ eye diagram in the prior art, the present application can synchronously adjust the first threshold and the second threshold, gradually increase the first threshold, and gradually reduce the second threshold, and determine the actual transition density corresponding to the first target threshold and the second target threshold after each adjustment, and compare the actual transition density with the expected transition density. When the actual transition density is greater than the expected transition density, the difference between the first target threshold and the second target threshold at this time is used as the internal eye height, which solves the problem of low efficiency in eye height measurement of the NRZ eye diagram.

[0109] Based on the same inventive concept, the embodiment of the present application also provides a CDR circuit lock detection circuit corresponding to the eye height measurement method of the NRZ eye diagram. Since the principle of solving the problem by the circuit in the embodiment of the present application is similar to the eye height measurement method of the NRZ eye diagram in the embodiment of the present application, the implementation of the circuit can refer to the implementation of the method, and the repeated parts will not be repeated.

[0110] See also Figure 4 , Figure 4 A circuit diagram of a CDR lock detection circuit provided in an embodiment of the present application. Figure 4 As shown in , the CDR lock detection circuit 10 includes: a first comparison trigger 100, a second comparison trigger 200, a logic circuit 300 and a statistical circuit 400, the first comparison trigger 100 and the second comparison trigger 200 are comparison triggers with thresholds;

[0111] The clock signal output by the CDR circuit is input to the clock control terminals of the first comparison trigger 100 and the second comparison trigger 200 respectively;

[0112] The NRZ signal is input to the data input terminals of the first comparison trigger 100 and the second comparison trigger 200 respectively;

[0113] The output terminal of the first comparison trigger 100 and the output terminal of the second comparison trigger 200 are respectively connected to the first input terminal and the second input terminal of the logic circuit 300;

[0114] A first input terminal of the statistical circuit 400 is connected to an output terminal of the logic circuit 300 , and a second input terminal of the statistical circuit 400 receives a clock signal output by the CDR circuit. The statistical circuit 400 is used to determine a locking state of the CDR circuit.

[0115] Here, the comparison trigger may refer to a D-type trigger, namely, a DFF. The comparison trigger is a trigger that outputs a result under the action of a clock signal and changes according to the state of the input terminal D.

[0116] Specifically, a first threshold is set for the first comparison trigger, and a second threshold is set for the second comparison trigger.

[0117] The first comparison trigger 100 is used for comparing the NRZ signal level of each bit with a first threshold value to obtain a first comparison result.

[0118] The second comparison trigger 200 is used for comparing the NRZ signal level of each bit with a second threshold to obtain a second comparison result.

[0119] The clock signal may refer to a clock signal output by the CDR circuit, and the clock signal is simultaneously input to the first comparison flip-flop 100 and the second comparison flip-flop 200 .

[0120] The logic circuit 300 may be a logic gate circuit, and the logic circuit 300 is used to determine an output signal according to the first comparison result and the second comparison result.

[0121] Exemplarily, the logic circuit 300 may be a circuit composed of an inverter and a NOR gate circuit, or may be an XOR gate circuit.

[0122] The statistical circuit 400 is used to determine the transition density of the output signal OUT within a period of time, and determine the locking state of the CDR based on the transition density.

[0123] In an optional embodiment, the logic circuit 300 includes an inverter and a NOR gate circuit; the output end of the first comparison trigger 100 is connected to the first input end of the NOR gate circuit; the output end of the second comparison trigger 200 is connected to the input end of the inverter; and the output end of the inverter is connected to the second input end of the NOR gate circuit.

[0124] Specifically, the logic circuit 300 is composed of an inverter 301 and a NOR gate circuit 302. The inverter 301 inverts the second comparison result B of the second comparison trigger 200, and the inverted second comparison result B and the first comparison result A output by the first comparison trigger 100 are input into the NOR gate circuit 302 together, and the output signal OUT is obtained after passing through the NOR gate circuit 302.

[0125] In addition, the logic circuit 300 can also be an XOR gate circuit, and the output end of the first comparison trigger 100 and the output end of the second comparator trigger 200 are respectively connected to the two input ends of the XOR gate circuit, so that the first comparison result A output by the first comparison trigger 100 and the second comparison result B output by the second comparison trigger 200 are respectively input to the two input ends of the XOR gate circuit, and the output signal OUT is obtained after passing through the XOR gate circuit.

[0126] In an optional embodiment, the statistical circuit 400 includes a data selector 410, a divider 420 and a digital circuit 430; the first input end of the data selector 410 is connected to the output end of the logic circuit 300; the second input end of the data selector 410 receives the clock signal output by the CDR circuit; the third input end of the data selector 410 is connected to the output end of the digital circuit 430; the output end of the data selector 410 is connected to the input end of the divider 420; and the output end of the divider 420 is connected to the input end of the digital circuit 430.

[0127] The data selector 410 may refer to a multiplexer, and the data selector 410 is used to select one of a plurality of input signals as an output signal, and the output signal thereof is the same as only one of the input signals at a certain moment.

[0128] In the embodiment of the present application, the data selector 410 is used to select a signal from the output signal of the logic circuit 300 and the clock signal output by the CDR circuit as the output signal of the data selector.

[0129] The divider 420 may refer to a logic circuit that implements a division operation. The divider 420 is used to perform frequency reduction processing on the signal to facilitate subsequent processing by a digital circuit.

[0130] Exemplarily, the divider 420 may be a divide-by-two circuit. When high-multiple division is required, it is sufficient to connect multiple divide-by-two circuits in series.

[0131] The digital circuit 430 may refer to a circuit for counting and determining transition density. The digital circuit 403 can generally only process signals below 1 GHz.

[0132] The output signal OUT and the clock signal output by the CDR circuit are respectively input to the first input terminal and the second input terminal of the data selector 410, the second output terminal of the digital circuit 430 is connected to the third input terminal of the data selector 410, the output terminal of the data selector 410 is connected to the input terminal of the divider 420, and the output terminal of the divider 420 is connected to the input terminal of the digital circuit 430; the first output terminal of the digital circuit 430 outputs a locked state.

[0133] In an optional embodiment, the digital circuit 430 includes a synchronizer 431, a third comparison trigger 432, an XOR gate circuit 433, an adder 434 and a processor 435; the first input end of the synchronizer 431 is connected to the output end of the divider 420, and the second input end of the synchronizer 431 receives a digital clock; the first input end of the third comparison trigger 432 is connected to the output end of the synchronizer 431, and the second input end of the third comparison trigger 432 receives a digital clock; the first input end of the XOR gate circuit 433 is connected to the output end of the synchronizer 431, and the second input end is connected to the output end of the third comparison trigger 432; the output end of the XOR gate circuit 433 is connected to the input end of the adder 434; the output end of the adder 434 is connected to the input end of the processor 435; the output end of the processor 435 is connected to the third input end of the data selector 410.

[0134] Here, the synchronizer 431 may refer to a digital circuit synchronizer, and the synchronizer 431 is used to synchronize the output signal OUT output by the divider with a digital clock.

[0135] The third comparison trigger 432 may refer to a comparison trigger, and the third comparison trigger 432 is used to delay the signal input to the comparison trigger to obtain an output signal D.

[0136] Among them, the output signal C and the output signal D are the same data, but after passing through the third comparison trigger 432, the output signal D is delayed by one clock cycle compared to the output signal C of the synchronizer. In this way, when the output signal C and the output signal D pass through the XOR gate circuit 433, when the output signal C and the output signal D are different, the result is 1, that is, when the output signal OUT jumps, a pulse output signal E will be generated.

[0137] The adder 434 may be referred to as an accumulator, and the adder 434 is used to count the number of pulses.

[0138] The processor 435 may refer to a calculation processing circuit, and the processor 435 is used to calculate the ratio of the number of transitions of the output signal OUT to the number of clock signals, and determine the locking state of the CDR circuit according to the ratio.

[0139] The output signal OUT output by the divider 420 is input to the first input terminal of the synchronizer 431, and the digital clock is input to the second input terminal of the synchronizer 431. The synchronizer 431 processes the output signal OUT and the digital clock to obtain the output signal C. The output signal C is input to the first input terminal of the third comparison trigger 432, and the digital clock is input to the second input terminal of the third comparison trigger 432. The third comparison trigger processes the output signal C and the digital clock to obtain the output signal D. The output signal C and the output signal D are input to the first input terminal and the second input terminal of the XOR gate circuit 433 to obtain the output signal E. The adder 434 counts the output signal E and sends the counting result to the processor 435. The processor 435 calculates the transition density using the received counting result, determines the locking state of the CDR circuit according to the transition density, and sends the determined locking state through the first output terminal. At the same time, the processor 435 also sends a control signal through the second output terminal, and the data selector 410 selects a signal from the output signal OUT output by the logic circuit and the clock signal output by the CDR according to the control signal as the output signal of the data selector 410.

[0140] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0141] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0142] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0143] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0144] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application can essentially be embodied in the form of a software product, or in other words, the part that contributes to the prior art or the part of the technical solution. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0145] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for measuring eye height of an NRZ eye diagram, characterized in that: include: When the clock data recovery circuit is in a locked state, the middle level of the NRZ signal is used as the initial value of the first threshold and the second threshold; Performing a first type of single adjustment on the first threshold and the second threshold, increasing the first threshold to obtain a first target threshold, and decreasing the second threshold to obtain a second target threshold; Calculating actual transition densities corresponding to the first target threshold and the second target threshold; determining whether the actual transition density is greater than an expected transition density; If the actual transition density is greater than the expected transition density, the difference between the first target threshold and the second target threshold is determined as the inner eye height of the NRZ eye diagram; After determining the difference between the first target threshold and the second target threshold as the internal eye height of the NRZ eye diagram, the method further includes: Performing a second type of single adjustment on the first threshold and the second threshold, increasing the first threshold to obtain a first target threshold, and decreasing the second threshold to obtain a second target threshold; Calculating actual transition densities corresponding to the first target threshold and the second target threshold; determining whether the actual transition density is less than an expected transition density; If the actual transition density is less than the expected transition density, the difference between the first target threshold and the second target threshold is determined as the outer eye height of the NRZ eye diagram.

2. The method according to claim 1, characterized in that After determining whether the actual transition density is greater than the expected transition density, the method further includes: If the actual transition density is not greater than the expected transition density, the first target threshold is used as a new first threshold, and the second target threshold is used as a new second threshold; Return to the step of performing the first type of single adjustment on the first threshold and the second threshold.

3. The method according to claim 1, characterized in that The performing a first type of single adjustment on the first threshold and the second threshold, increasing the first threshold to obtain a first target threshold, and reducing the second threshold to obtain a second target threshold, or the performing a second type of single adjustment on the first threshold and the second threshold, increasing the first threshold to obtain the first target threshold, and reducing the second threshold to obtain the second target threshold, includes: Determine the adjustment step size; Adding the first threshold value to the adjustment step length to implement a single adjustment of the first threshold value, and determining the result of the addition as the first target threshold value; The second threshold is subtracted from the adjustment step length to implement a single adjustment of the second threshold, and the subtraction result is determined as the second target threshold.

4. The method according to claim 1, characterized in that: After determining whether the actual transition density is less than the expected transition density, the method further includes: If the actual transition density is not less than the expected transition density, the first target threshold is used as a new first threshold, and the second target threshold is used as a new second threshold; Return to the step of performing the second type of single adjustment on the first threshold and the second threshold.

5. The method according to claim 1, characterized in that The calculating the actual transition density corresponding to the first target threshold and the second target threshold includes: The NRZ signal is sampled by using the clock signal to obtain the NRZ signal level, and the NRZ signal level is compared with the first target threshold and the second target threshold respectively to obtain a first comparison result and a second comparison result; Determine an output signal corresponding to the NRZ signal level according to a logical relationship between the first comparison result and the second comparison result; Determining the number of transitions of adjacent output signals and the number of clock signals in the output signal, wherein the transition of adjacent output signals is a change in value between an nth output signal and an n-1th output signal or between an nth output signal and an n+1th output signal; When the number of the clock signals reaches a set threshold, the ratio of the number of transitions of the output signal to the number of the clock signals is determined as the actual transition density.

6. The method according to claim 5, characterized in that The step of determining the output signal corresponding to the NRZ signal level according to the logical relationship between the first comparison result and the second comparison result includes: performing inversion processing on the second comparison result; Perform a negation operation on the second comparison result after the inversion processing and the first comparison result to determine an output signal.

7. The method according to claim 5, characterized in that The number of transitions includes the number of rising edges and / or the number of falling edges; The step of determining the ratio of the number of transitions of the output signal to the number of clock signals as the actual transition density comprises: If the number of rising edges or falling edges of the output signal is determined, the ratio of the number of rising edges to the number of clock signals is taken as the actual transition density, or the ratio of the number of falling edges to the number of clock signals is taken as the actual transition density; If the sum of the number of rising edges and the number of falling edges of the output signal is determined, the ratio of the sum to the number of clock signals is taken as the actual transition density.

8. The method according to claim 1, characterized in that The sum of the first threshold and the second threshold is 1.

9. A CDR lock detection circuit, used to perform the eye height measurement method of the NRZ eye diagram according to any one of claims 1 to 8, characterized in that: It includes a first comparison trigger, a second comparison trigger, a logic circuit and a statistical circuit, wherein the first comparison trigger and the second comparison trigger are comparison triggers with thresholds; The clock signal output by the CDR circuit is input to the clock control terminals of the first comparison trigger and the second comparison trigger respectively; The NRZ signal is input to the data input terminals of the first comparison trigger and the second comparison trigger respectively; The output terminal of the first comparison trigger and the output terminal of the second comparison trigger are respectively connected to the first input terminal and the second input terminal of the logic circuit; The first input end of the statistical circuit is connected to the output end of the logic circuit, the second input end of the statistical circuit receives the clock signal output by the CDR circuit, and the statistical circuit is used to determine the locking state of the CDR circuit.

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