Imaging device and electronic device

Abstract

Provided are an imaging device capable of suppressing errors in the timing of reversal of a comparison result when a pixel signal is compared with a predetermined reference signal, and an electronic device including the imaging device. The imaging device according to the present application includes a load current source, a comparator including an input transistor connected between the load current source and a signal line for transmitting a signal read from a pixel, a first capacitor unit for inputting a predetermined reference signal to a gate electrode of the input transistor, and a second capacitor unit connected between a reference potential node and the gate electrode of the input transistor. The electronic device according to the present application includes the imaging device configured as above.

Description

TECHNICAL FIELD

[0001] The present application relates to an imaging device and an electronic apparatus. BACKGROUND

[0002] An analog-digital conversion section that digitizes an analog pixel signal read from a pixel is mounted on an imaging device. The analog-digital conversion section is a so-called column-parallel analog-digital conversion section that includes a plurality of analog-digital converters arranged corresponding to a pixel column.

[0003] As an analog-digital converter that constitutes the column-parallel analog-digital conversion section, for example, a so-called single-slope analog-digital converter is known that digitizes the analog pixel signal by comparing the analog pixel signal read from the pixel with a predetermined reference signal.

[0004] The single-slope analog-digital converter includes, for example, a comparator that compares the analog pixel signal with the predetermined reference signal, and a counter that counts based on a comparison result of the comparator. As the imaging device having the single-slope analog-digital converter, for example, an imaging device is proposed in which a P-channel metal-oxide semiconductor (MOS) transistor and an inverter are arranged in the comparator, in the P-channel metal-oxide semiconductor (MOS), the analog pixel signal is input to a source electrode and the predetermined reference signal is input to a gate electrode (for example, see Patent Literature 1).

[0005] List of Citation Literature

[0006] Patent Literature

[0007] Patent Literature 1: US 2018 / 0103222 A1 SUMMARY

[0008] Technical Problem to be Solved by the Invention

[0009] In the imaging device described in Patent Literature 1, the comparator of the analog-digital converter is configured to share a load current source of a pixel (pixel circuit) as a current source, and the sharing of the current source realizes a reduction in power consumption compared to a case where the current source is provided separately from the pixel circuit in the comparator.

[0010] However, in the connection configuration of the P-channel MOS transistor in the imaging device described in Patent Literature 1 described above, when the analog pixel signal matches the predetermined reference signal, the drain voltage of the P-channel MOS transistor varies depending on the level of the pixel signal. Therefore, the timing at which the comparison result of the comparator is inverted can deviate from the ideal timing at which the pixel signal matches the reference signal. This error in the inversion timing causes an error or nonlinearity to occur in a digital signal obtained by the analog-digital conversion of the pixel signal, thereby degrading the image quality of the image data.

[0011] An object of the present application is to provide an imaging device capable of suppressing an error in a time of inversion of a comparison result when a pixel signal is compared with a predetermined reference signal, and an electronic apparatus including the imaging device.

[0012] Solution to the problem

[0013] The imaging device for achieving the above object of the present application includes:

[0014] a load current source;

[0015] a comparator having an input transistor connected between the load current source and a signal line through which a signal read from a pixel is transmitted;

[0016] a first capacitor that inputs a predetermined reference signal to a gate electrode of the input transistor; and

[0017] a second capacitor connected between the gate electrode of the input transistor and a reference potential node.

[0018] Further, the electronic apparatus for achieving the above object of the present application includes the imaging device having the above configuration. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a block diagram schematically showing an outline of a system configuration of a CMOS image sensor which is an example of an imaging device to which the technology according to the present application is applied.

[0020] Figure 2 is a circuit diagram showing an exemplary circuit configuration of a pixel.

[0021] Figure 3A is a perspective view schematically showing a flat chip structure, and Figure 3B is an exploded perspective view schematically showing a stacked semiconductor chip structure.

[0022] Figure 4 is a block diagram schematically showing an exemplary configuration of an analog-digital conversion section.

[0023] Figure 5 is a circuit diagram showing an example of a circuit configuration of a comparator according to a reference example.

[0024] Figure 6 is a timing chart for explaining an example of a circuit operation of the comparator according to the reference example.

[0025] Figure 7 is a characteristic diagram showing an exemplary characteristic of a P-channel MOS transistor.

[0026] Figure 8This is a circuit diagram used to illustrate the buffer noise in the case of a comparator according to the reference example.

[0027] Figure 9 This is a circuit diagram illustrating an example of the circuit structure of a comparator according to an embodiment of the present invention.

[0028] Figure 10 This is a circuit diagram showing an example of the circuit structure of a comparator according to Example 1.

[0029] Figure 11A It is a waveform diagram showing the relationship between the slope of the ramp of the reference signal and the intersection point of the pixel signal, and Figure 11B This is a graph showing the relationship between the analog gain of the analog-to-digital converter and the amplitude of the ramp of the reference signal.

[0030] Figure 12 This is a circuit diagram illustrating an example of the circuit structure of a comparator according to Embodiment 2.

[0031] Figure 13 This is a circuit diagram showing an example of the circuit structure according to a specific example 1 of the attenuation ratio.

[0032] Figure 14 This is a circuit diagram showing an example of the circuit structure based on a specific example 2 of the attenuation ratio.

[0033] Figure 15 This is a circuit diagram showing an example of the circuit structure based on specific example 3 of the attenuation ratio.

[0034] Figure 16 This is a circuit diagram showing an example of the circuit structure based on specific example 4 of the attenuation ratio.

[0035] Figure 17A It is a graph showing the relationship between the analog gain and capacitance value of the first and second capacitors, and Figure 17B This is a graph showing the relationship between the analog gain of the reference signal and the amplitude of the ramp wave.

[0036] Figure 18 This is a circuit diagram illustrating an example of the circuit structure of a comparator according to Embodiment 3.

[0037] Figure 19 This is a circuit diagram illustrating an example of the circuit structure of a comparator according to Embodiment 4.

[0038] Figure 20 This is a circuit diagram illustrating an example of the circuit structure of a comparator according to Embodiment 5.

[0039] Figure 21 This is a circuit diagram illustrating an example of the circuit structure of a comparator according to Embodiment 6.

[0040] Figure 22 FIG. 7 is a circuit diagram showing an example of a circuit structure of a comparator according to Embodiment 7.

[0041] Figure 23 FIG. 8 is a circuit diagram showing an example of a circuit structure of an analog-digital converter according to Embodiment 8.

[0042] Figure 24 FIG. 9 is an operation explanatory diagram of Operation Example 1 of Embodiment 8.

[0043] Figure 25 FIG. 10 is an operation explanatory diagram of Operation Example 2 of Embodiment 8.

[0044] Figure 26 FIG. 11 is an operation explanatory diagram of Operation Example 3 of Embodiment 8.

[0045] Figure 27 FIG. 12 is an operation explanatory diagram of Operation Example 4 of Embodiment 8.

[0046] Figure 28 FIG. 13 is a circuit diagram showing another circuit structure of a reference signal generation section.

[0047] Figure 29 FIG. 14 is a circuit diagram showing an example of a circuit structure of a power supply noise correction circuit according to Embodiment 9.

[0048] Figure 30 FIG. 15 is an operation explanatory diagram of Gain Control Example 1 of Embodiment 9.

[0049] Figure 31 FIG. 16 is an operation explanatory diagram of Gain Control Example 2 of Embodiment 9.

[0050] Figure 32 FIG. 17 is an operation explanatory diagram of Gain Control Example 3 of Embodiment 9.

[0051] Figure 33 FIG. 18 is an operation explanatory diagram of Gain Control Example 4 of Embodiment 9.

[0052] Figure 34 FIG. 19 is a circuit diagram showing an example of a circuit structure of an analog-digital converter according to Embodiment 10.

[0053] Figure 35 FIG. 20 is a block diagram schematically showing an outline of a system configuration of a CMOS image sensor according to Embodiment 11.

[0054] Figure 36 FIG. 21 is a flowchart showing an example of a processing procedure of setting a DAC setting signal and a switch setting signal.

[0055] Figure 37 FIG. 22 is a circuit diagram showing a first modification example of a comparator.

[0056] Figure 38 FIG. 6 is a circuit diagram showing a second modification example of the comparator.

[0057] Figure 39 FIG. 7 is a circuit diagram showing a configuration example of a conventional configuration example adding a capacitor C ADJ

[0058] Figure 40 FIG. 8 is a diagram showing an application example according to the technology of the present application.

[0059] Figure 41 FIG. 9 is a block diagram schematically showing a configuration example of an imaging system as an example of the electronic apparatus of the present application.

[0060] Figure 42 FIG. 10 is a block diagram schematically showing a configuration example of a vehicle control system as an example of a mobile body control system to which the technology according to the present application can be applied.

[0061] Figure 1 FIG. 11 is a diagram showing an example of a mounting position of an imaging section of the mobile body control system. DETAILED DESCRIPTION

[0062] Hereinafter, embodiments (hereinafter, referred to as "embodiments") according to the technology of the present application will be described in detail with reference to the accompanying drawings. The technology according to the present application is not limited to the embodiments. In the following description, the same reference numerals are used for the same elements or elements having the same function, and redundant description thereof will be omitted. Note that the description will be made in the following order.

[0063] 1. SUMMARY OF THE IMAGING DEVICE AND THE ELECTRONIC APPARATUS OF THE PRESENT INVENTION

[0064] 2. IMAGING DEVICE TO WHICH THE TECHNOLOGY ACCORDING TO THE PRESENT INVENTION IS APPLIED

[0065] 2-1. CONFIGURATION EXAMPLE OF CMOS IMAGE SENSOR

[0066] 2-2. CIRCUIT STRUCTURE EXAMPLE OF PIXEL

[0067] 2-3. SEMICONDUCTOR CHIP STRUCTURE

[0068] 2-3-1. FLAT SEMICONDUCTOR CHIP STRUCTURE

[0069] 2-3-2. STACKED SEMICONDUCTOR CHIP STRUCTURE

[0070] 2-4. CONFIGURATION EXAMPLE OF ANALOG-DIGITAL CONVERTING SECTION

[0071] 2-5. COMPARATOR WITH RESPECT TO ANALOG-DIGITAL CONVERTER

[0072] 2-6. COMPARATOR ACCORDING TO REFERENCE EXAMPLE

[0073] ​2-6-1. Circuit structure example of comparator according to reference example

[0074] 2-6-2. Operation example of comparator circuit according to reference example

[0075] 2-6-3. Regarding buffer noise

[0076] 3. Embodiments of the present application

[0077] 3-1. Embodiment 1 (example using a variable capacitance element as the first and second capacitors)

[0078] 3-2. Embodiment 2 (example using a combination of a plurality of capacitance elements and a plurality of switching elements to constitute the first and second capacitors)

[0079] 3-2-1. Specific example 1 of capacitance attenuation ratio (example where the capacitance attenuation ratio is 4 / 4 (no attenuation))

[0080] 3-2-2. Specific example 2 of capacitance attenuation ratio (example where the capacitance attenuation ratio is 3 / 4)

[0081] 3-2-3. Specific example 3 of capacitance attenuation ratio (example where the capacitance attenuation ratio is 2 / 4)

[0082] 3-2-4. Specific example 4 of capacitance attenuation ratio (example where the capacitance attenuation ratio is 1 / 4)

[0083] 3-3. Embodiment 3 (variant of Embodiment 2: example of controlling the analog gain)

[0084] 3-4. Embodiment 4 (example where no switching element is provided on the reference potential node side)

[0085] 3-5. Embodiment 5 (example including three capacitance elements and three switching elements)

[0086] 3-6. Embodiment 6 (variant of Embodiment 5: example where the connection relationship between the capacitance elements and the switching elements is different)

[0087] 3-7. Embodiment 7 (example where the circuit structure of the comparator is different)

[0088] 3-8. Embodiment 8 (application example of a CMOS image sensor having a function of suppressing power supply noise of a pixel power supply)

[0089] 3-8-1. Operation example 1 (example where the capacitance attenuation ratio is 4 / 4)

[0090] 3-8-2. Operation example 2 (example where the capacitance attenuation ratio is 3 / 4)

[0091] 3-8-3. Operation example 3 (example of case where capacitance attenuation ratio is 2 / 4)

[0092] 3-8-4. Operation example 4 (example of case where capacitance attenuation ratio is 1 / 4)

[0093] 3-9. Embodiment 9 (example of circuit structure of power supply noise correction circuit)

[0094] 3-9-1. Gain control example 1 (control example when additional gain is one time)

[0095] 3-9-2. Gain control example 2 (control example when additional gain is 4 / 3 times)

[0096] 3-9-3. Gain control example 3 (control example when additional gain is two times)

[0097] 3-9-4. Gain control example 4 (control example when additional gain is four times)

[0098] 3-10. Embodiment 10 (modified example of Embodiment 8: application example of MOS image sensor using reference voltage in pixel)

[0099] 3-11. Embodiment 11 (example of setting DAC setting signal and switch setting signal when switching slope of ramp and input capacitance)

[0100] 3-12. Embodiment 12 (process of setting DAC setting signal and switch setting signal)

[0101] 4. Modified example

[0102] 5. Application example

[0103] 6. Application example according to the present technology

[0104] 6-1. Electronic device of the present application (example of imaging device)

[0105] 6-2. Application example of mobile body

[0106] 7. Configuration that can be adopted by the present application

[0107] [Summary of imaging device and electronic device of the present application]

[0108] In the imaging device and the electronic apparatus of the present application having the above-described preferred configuration, each of the first capacitor and the second capacitor can be configured to include a plurality of capacitance elements each having a first terminal connected to the gate electrode of the input transistor and a plurality of switching elements each connected between second terminals of the plurality of capacitance elements. Further, a configuration can be employed in which a switching element is further provided between the reference potential node and the second terminal of the capacitance element of the plurality of capacitance elements on the reference potential node side.

[0109] In the imaging device and the electronic apparatus of the present application having the above-described preferred configuration, each of the first capacitor and the second capacitor can be configured to include a plurality of capacitance elements each having a first terminal connected to the gate electrode of the input transistor and a plurality of switching elements each connected between second terminals of the plurality of capacitance elements. Further, a configuration can be employed in which a switching element is further provided between the reference potential node and the second terminal of the capacitance element of the plurality of capacitance elements on the reference potential node side.

[0110] Further, in the imaging device and the electronic apparatus of the present application having the above-described preferred configuration, the predetermined reference signal can be configured to be a ramp waveform voltage that linearly varies with a predetermined slope. Then, the comparator can be configured to compare the voltage of the signal line with the ramp waveform voltage.

[0111] Further, in the imaging device and the electronic apparatus of the present application having the above-described preferred configuration, the voltage amplitude of the ramp waveform is attenuated by using the capacitance division of the first capacitor and the second capacitor. At this time, the reference signal generation section that generates the ramp waveform voltage can be configured to set the voltage amplitude of the ramp waveform to a large amplitude in advance so that the amplitude after attenuation by the capacitance division becomes a desired amplitude.

[0112] Further, the imaging device and the electronic apparatus of the present application having the above-described preferred configuration can include an analog gain control section that controls the analog gain of the analog-digital converter by adjusting the voltage amplitude of the ramp waveform. Then, the analog gain control section can be configured to control the voltage amplitude of the ramp waveform and the capacitance values of the first capacitor and the second capacitor.

[0113] Further, in the imaging device and the electronic apparatus of the present application having the above-described preferred configuration, the load current source can include an input-side load current source and an output-side load current source, and the input transistor can be configured to be connected between the signal line and the input-side load current source. In addition, the comparator can include an output transistor connected between the signal line and the output-side load current source, and use the output of the input transistor as a gate input.

[0114] Further, the imaging device and the electronic apparatus of the present application having the above-described preferred configuration can include a noise correction circuit that superimposes a correction voltage corresponding to noise of a pixel power supply on a reference signal generated by a reference signal generation section. At this time, the noise correction circuit can be configured to switch a gain for generating the correction voltage in accordance with switching of the capacitance value of each of a first capacitor and a second capacitor.

[0115] Further, the imaging device and the electronic apparatus of the present application having the above-described preferred configuration can include a control section that sets a reference signal setting signal for the reference signal generation section to generate a reference signal and a switch setting signal for switching a plurality of switching elements when an analog gain of an analog-digital converter is controlled. Further, a configuration provided with a logic circuit section that generates illumination data based on data after analog-digital conversion by the analog-digital converter can also be employed. In addition, the control section can be configured to set the reference signal setting signal and the switch setting signal in accordance with the illumination data generated by the logic circuit section.

[0116] [Imaging device to which the technology according to the present application is applied]

[0117] As an imaging device to which the technology according to the present application is applied, a complementary metal oxide semiconductor (CMOS) image sensor as an example of an X-Y address imaging device will be described. The CMOS image sensor is an image sensor manufactured by applying or partially using a CMOS process.

[0118] [Configuration example of CMOS image sensor]

[0119] Figure 1 is a block diagram schematically showing an outline of a system configuration of the CMOS image sensor as an example of an imaging device to which the technology according to the present application is applied.

[0120] The CMOS image sensor 1 according to the present application example includes a pixel array section 11 and a peripheral circuit section of the pixel array section 11. The pixel array section 11 has a configuration in which pixels (pixel circuits) 20 including light-receiving elements are two-dimensionally arranged in a row direction and a column direction (i.e., in a matrix). Here, the row direction refers to an array direction of the pixels 20 in a pixel row, and the column direction refers to an array direction of the pixels 20 in a pixel column. The pixels 20 perform photoelectric conversion to generate and accumulate photocharges corresponding to the amount of received light.

[0121] The peripheral circuit section of the pixel array section 11 includes, for example, a row selection section 12, an analog-digital conversion section 13, a logic circuit section 14 as a signal processing section, a timing control section 15, and the like.

[0122] In the pixel array section 11, with respect to the pixel array of a matrix shape, a pixel control line 31 (311 to 31 m ) is arranged for each pixel row in the row direction. Further, a signal line 32 (321 to 32 n ) is arranged for each pixel column in the column direction. The pixel control line 31 transmits a drive signal for performing driving when reading a signal from the pixel 20. Figure 2 The pixel control line 31 is illustrated as one wire, but it is not limited to one. The pixel control line 31 has one end connected to an output terminal corresponding to each row of the row selection section 12.

[0123] Hereinafter, each constituent element of the peripheral circuit section of the pixel array section 11, that is, the row selection section 12, the analog-digital conversion section 13, the logic circuit section 14, and the timing control section 15 will be described.

[0124] The row selection section 12 includes a shift register and an address decoder, and the like, and controls scanning of the pixel row and the address of the pixel row at the time of selection of each pixel 20 of the pixel array section 11. Although the specific configuration thereof is not shown, the row selection section 12 generally includes two scanning systems of a read scanning system and a reset scanning system.

[0125] The read scanning system selects and scans the pixels 20 of the pixel array section 11 in order by row, so as to read a pixel signal from the pixel 20. The pixel signal read from the pixel 20 is an analog signal. The reset scanning system performs reset on the read row to be subjected to the read scanning by the read scanning system at a time corresponding to the shutter speed before the read scanning.

[0126] The reset scanning performed by the reset scanning system resets the photoelectric conversion element of the pixel 20 of the read row by removing unnecessary charge, thereby resetting the photoelectric conversion element. In addition, the so-called electronic shutter operation is performed by the reset scanning system to remove (reset) the unnecessary charge. Here, the electronic shutter operation refers to an operation of removing the photocharge of the photoelectric conversion element and newly starting exposure (starting accumulation of the photocharge).

[0127] The analog-digital conversion section 13 includes a plurality of analog-digital converters (ADCs) provided corresponding to the pixel columns (for example, for each pixel column) of the pixel array section 11. The analog-digital conversion section 13 is a column parallel analog-digital conversion section that converts the analog pixel signal output through each signal line 321 to 32 n for each pixel column into a digital signal.

[0128] As the analog-digital converter in the analog-digital conversion section 13, for example, a single slope analog-digital converter, which is an example of a reference signal comparison analog-digital converter, can be used.

[0129] The logic circuit section 14 as the signal processing section reads the pixel signal digitized by the analog-digital conversion section 13, and performs predetermined signal processing. Specifically, as the predetermined signal processing, the logic circuit section 14 performs, for example, correction of vertical line defects and point defects or clamping of the signal, and further digital signal processing such as parallel-serial conversion, compression, encoding, addition, averaging, or intermittent operation. The logic circuit section 14 outputs the generated image data as the output signal OUT of the CMOS image sensor 1 to a subsequent device.

[0130] The timing control section 15 generates various timing signals, clock signals, and control signals, and the like, based on a synchronization signal supplied from the outside. Then, the timing control section 15 controls the driving of the row selection section 12, the analog-digital conversion section 13, the logic circuit section 14, and the like, based on the generated signals.

[0131] [Example of circuit structure of pixel]

[0132] Figure 3A is a circuit diagram showing an exemplary circuit structure of the pixel 20. The pixel 20 includes, for example, a photodiode 21 as a photoelectric conversion element. The pixel 20 includes, in addition to the photodiode 21, a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25.

[0133] For example, an N-channel MOS field effect transistor is used as the four transistors of the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25. However, the combination of the conductive types of the four transistors 22 to 25 exemplified here is merely an example, and the combination is not limited thereto.

[0134] For the pixel 20, as the pixel control lines 31 (311 to 31 m The plurality of pixel control lines are connected to the output terminals of the respective pixel rows corresponding to the row selection section 12 in units of pixel rows. The row selection section 12 appropriately outputs the transfer signal TRG, the reset signal RST, and the selection signal SEL to the plurality of pixel control lines.

[0135] The photodiode 21 has an anode electrode connected to a low-potential side power supply (for example, ground), which photoelectrically converts the received light into a photocharge (here, a photoelectron) corresponding to the amount of light, and accumulates the photocharge. The photodiode 21 has a cathode electrode electrically connected to the gate electrode of the amplification transistor 24 via the transfer transistor 22. Here, the region to which the gate electrode of the amplification transistor 24 is electrically connected is a floating diffusion (floating diffusion region / impurity diffusion region) FD. The floating diffusion FD is a charge-voltage conversion section that converts a charge into a voltage.

[0136] The row selection section 12 supplies a high level (e.g., V) to the gate electrode of the transmission transistor 22. DD The transmission signal TRG is activated at a certain level. The transmission transistor 22 enters the on state in response to the transmission signal TRG, thereby transferring the photocharge converted by photodiode 21 and accumulated in photodiode 21 to the floating diffuser FD.

[0137] Reset transistor 23 is connected to the high-potential side power supply voltage V. DD The node is between the floating diffuse FD and the node. A reset signal RST, activated at a high level, is supplied from the row select section 12 to the gate electrode of the reset transistor 23. The reset transistor 23 enters the on state in response to the reset signal RST and resets the floating diffuse FD to voltage V by sweeping out the charge of the floating diffuse FD. DD The node.

[0138] Amplifying transistor 24 has a gate electrode connected to the floating diffuser FD and a power supply voltage V connected to the high-potential side. DD The drain electrode of the node. The amplifying transistor 24 serves as the input of the source follower, which reads the signal obtained by photoelectric conversion in the photodiode 21. That is, the amplifying transistor 24 has a source electrode connected to the signal line 32 via the select transistor 25.

[0139] The selection transistor 25 has a drain electrode connected to the source electrode of the amplifying transistor 24 and a source electrode connected to the signal line 32. A selection signal SEL, which is activated at a high level, is supplied from the row selection section 12 to the gate electrode of the selection transistor 25. In response to the selection signal SEL, the selection transistor 25 enters a conducting state, thereby transmitting the signal output from the amplifying transistor 24 to the signal line 32 when the pixel 20 is in the selected state.

[0140] Note that the above circuit example illustrates a pixel 20 with a 4-Tr configuration including four transistors (i.e., transfer transistor 22, reset transistor 23, amplification transistor 24, and selection transistor 25), but the invention is not limited thereto. For example, a 3-Tr configuration can be used, omitting the selection transistor 25 and using the amplification transistor 24 as the selection transistor 25, and a 5-Tr or more configuration with an increased number of transistors can be used if necessary.

[0141] [Semiconductor chip structure]

[0142] As a semiconductor chip structure of the CMOS image sensor 1 having the above-described configuration, a flat semiconductor chip structure and a stacked semiconductor chip structure can be exemplified. Further, regarding the pixel structure, assuming that a substrate surface on a side on which a wiring layer is formed is defined as a front surface (front side), a backside-illumination type pixel structure that captures light irradiated from a backside opposite side, or a frontside-illumination type pixel structure that captures light irradiated from the front side can be adopted.

[0143] Hereinafter, an outline of the flat semiconductor chip structure and the stacked semiconductor chip structure will be described.

[0144] (Flat semiconductor chip structure)

[0145] Figure 3A is a perspective view schematically showing a flat chip structure of the CMOS image sensor 1. As shown in Figure 3B , the flat semiconductor chip structure has a configuration in which each constituent element of the peripheral circuit portion of the pixel array portion 11 is formed on the same semiconductor chip 41 as the pixel array portion 11 in which the pixels 20 are arranged in a matrix form. Specifically, the row selection portion 12, the analog-digital conversion portion 13, the logic circuit portion 14, the timing control portion 15, and the like are formed on the same semiconductor chip 41 as the pixel array portion 11. For example, a pad 42 for external connection and a power supply are provided at both left and right ends of the first layer semiconductor chip 41.

[0146] (Stacked semiconductor chip structure)

[0147] Figure 3B is an exploded perspective view schematically showing a stacked semiconductor chip structure of the CMOS image sensor 1. As shown in Figure 4 , the stacked semiconductor chip structure, that is, the stacked structure has a structure in which at least two semiconductor chips of the first layer semiconductor chip 43 and the second layer semiconductor chip 44 are stacked.

[0148] In this stacked semiconductor chip structure, the first layer semiconductor chip 43 is a pixel chip in which the pixel array portion 11 in which the pixels 20 including a photoelectric conversion element (for example, a photodiode 21) are arranged in a matrix two-dimensionally is formed. For example, a pad 42 for external connection and a power supply are provided at both left and right ends of the first layer semiconductor chip 41.

[0149] The second layer semiconductor chip 44 is a circuit chip in which the peripheral circuit portion of the pixel array portion 11, that is, the row selection portion 12, the analog-digital conversion portion 13, the logic circuit portion 14, the timing control portion 15, and the like are formed. Note that the arrangement of the row selection portion 12, the analog-digital conversion portion 13, the logic circuit portion 14, and the timing control portion 15 is an example, and is not limited to this arrangement example.

[0150] The pixel array section 11 on the first layer semiconductor chip 43 and the peripheral circuit section on the second layer semiconductor chip 44 are electrically connected via bonding sections 72 and 73, which include metal-metal bonding including Cu-Cu bonding, through silicon via (TSV), micro bumps, and the like.

[0151] According to the stacked semiconductor chip structure described above, a process suitable for manufacturing the pixel array section 11 can be applied to the first layer semiconductor chip 43, and a process suitable for manufacturing the circuit section can be applied to the second layer semiconductor chip 44. Thus, the process can be optimized in the course of manufacturing the CMOS image sensor 1. Therefore, the process can be optimized to manufacture the CMOS image sensor 1. In particular, an advanced process can be applied to manufacture the circuit section.

[0152] [Configuration example of analog-digital conversion section]

[0153] Next, an exemplary configuration of the analog-digital conversion section 13 will be described. Here, a single slope analog-digital converter is used as each analog-digital converter of the analog-digital conversion section 13.

[0154] Figure 5 An exemplary configuration of the analog-digital conversion section 13 is shown. In the CMOS image sensor 1, the analog-digital conversion section 13 includes a plurality of single slope analog-digital converters each of which is provided corresponding to a pixel column of the pixel array section 11. Here, a single slope analog-digital converter 130 of the nth column will be described as an example.

[0155] The analog-digital converter 130 has a circuit configuration including a comparator 131 and a counter 132. In addition, in the single slope analog-digital converter 130, a reference signal generated by a reference signal generation section 16 is used. The reference signal generation section 16, for example, includes a digital-analog converter (DAC) and generates a ramp waveform (so-called ramp) reference signal V RAMP which monotonously decreases in level (voltage) over time, and supplies the reference signal V RAMP as a standard signal to the comparator 131 provided for each pixel column.

[0156] The comparator 131 uses the analog pixel signal V VSL read from the pixel 20 as a comparison input, and uses the ramp reference signal V RAMP generated by the reference signal generation section 16 as a reference input, to compare the two signals. Then, for example, when the reference signal V RAMP is greater than the pixel signal V VSL , the output of the comparator 131 is in a first state (high level), and when the reference signal V RAMP is equal to or less than the pixel signal V VSLWhen the signal level of the analog pixel signal V VSL is higher than the signal level of the reference signal V

[0157] The counter 132 is supplied with the clock signal CLK at the same timing as the supply start timing of the reference signal V RAMP to the comparator 131. Then, the counter 132 performs a counting operation in synchronization with the clock signal CLK to measure the period of the pulse width of the output pulse of the comparator 133, that is, the time period from the start of the comparison operation to the end of the comparison operation. The counting result (count value) of the counter 132 is supplied to the logic circuit section 14 as a digital value obtained by digitizing the analog pixel signal V VSL .

[0158] According to the analog-digital conversion section 13 including a set of the above-described single slope analog-digital converters 130, it is possible to obtain a digital value from the time information until the magnitude relationship between the reference signal V RAMP generated by the reference signal generation section 16 and the analog pixel signal V VSL read from the pixel 20 through the signal line 32 changes.

[0159] Note that, in the above-described example, the configuration in which the analog-digital converters 130 are arranged in one-to-one correspondence with the pixel columns of the pixel array section 11 is exemplified as the analog-digital conversion section 13, but a configuration in which the analog-digital converters 130 are arranged in units of a plurality of pixel columns can also be employed.

[0160] [Comparator of analog-digital converter]

[0161] In the above-described single slope analog-digital converter 130, a comparator having a differential amplifier configuration is generally used as the comparator 131. However, in the case where the comparator has a differential amplifier configuration, it is necessary to secure the input range according to the signal amount of the pixel 20, and thus it is necessary to set the power supply voltage V DD to a relatively high voltage. Thus, there is a problem in that the power consumption of the analog-digital converter 130 and the power consumption of the CMOS image sensor 1 become relatively high.

[0162] On the other hand, there is a related art having a configuration in which a P-channel metal oxide semiconductor (MOS) transistor in which an analog pixel signal is input to a source electrode and a predetermined reference signal is input to a gate electrode is provided, and a load current source of a pixel (pixel circuit) is shared as a current source of a comparator (for example, see Patent Literature 1). According to this related art, it is possible to reduce the power consumption compared to the case where a configuration in which a current source is also provided separately from the pixel circuit in the comparator is employed.

[0163] However, in the above connection configuration of the related art, when the analog pixel signal matches the predetermined reference signal, the drain voltage of the P-channel MOS transistor varies depending on the level of the pixel signal, and thus the timing at which the comparison result of the comparator is inverted can deviate from the ideal timing at which the pixel signal and the reference signal coincide. This error in the inversion timing leads to the following problems: an error or nonlinearity occurs in a digital signal obtained by analog-digital conversion of the pixel signal, thereby causing deterioration of the image quality of image data.

[0164] [Comparator according to Reference Example]

[0165] As a comparator according to the reference example, a comparator for solving the above problems of the related art will be described below.

[0166] (Circuit structure example of comparator according to Reference Example)

[0167] Figure 5 A circuit structure example of the comparator according to the reference example is shown. Here, a circuit structure corresponding to one pixel column is shown for the sake of simplification of the drawing.

[0168] As Figure 1 shown, the comparator 131 according to the reference example includes a capacitance element C 11 , an auto-zero switch SW AZ , an input transistor PT 11 , an input-side load current source I 11 , a capacitance element C 12 , an input-side clamp transistor PT 13 , an input-side clamp transistor NT 11 , an output transistor PT 12 , an output-side load current source I 12 , and an output-side clamp transistor NT 12 .

[0169] The input transistor PT 11 includes a P-channel MOS transistor, and is connected between the signal line 32 and the input-side load current source I 11 . Specifically, the input transistor PT 11 has a source electrode connected to the signal line 32 and a drain electrode connected to the first end of the input-side load current source I 11 . Thus, the analog pixel signal V VSL is input to the source electrode of the input transistor PT 11 through the signal line 32. The back gate and the source electrode of the input transistor PT 11 are ideally short-circuited to suppress the back gate effect.

[0170] The input-side load current source I 11It has a second terminal connected to a low-potential power supply (e.g., ground, GND). Input-side load current source I 11 Input transistor PT 11 A constant current is supplied by the series circuit of signal line 32.

[0171] Capacitor element C 11 The reference signal V connected to the ramp wave RAMP Input terminal T 11 With input transistor PT 11 Between the gate electrodes, used relative to the reference signal V RAMP The input capacitor absorbs the offset. Therefore, the analog pixel signal V is transmitted through signal line 32. VSL Input to input transistor PT 11 The source electrode, and via capacitor element C 11 The reference signal V of the ramp wave RAMP Input to the gate electrode.

[0172] Input transistor PT 11 Amplify the reference signal V of the ramp input to the gate electrode. RAMP The analog pixel signal V input to the source electrode VSL The difference between them, i.e., the input transistor PT 11 Gate-source voltage V gs And the amplified difference is used as the drain voltage V. d Output from the drain electrode.

[0173] Automatic zeroing switch SW AZ Connected to the input transistor PT 11 Between the gate electrode and the drain electrode, and via the input terminal T 12 from Figure 6 The timing control unit 15 shown is controlled by the drive signal AZ input to turn on (off) or off (open). The automatic zeroing switch SW is turned on. AZ Set to the ON state to perform a zeroing (initialization) operation that causes a short circuit between the gate and drain electrodes of the input transistor. An auto-zeroing switch SW can be constructed using P-channel or N-channel MOS transistors. AZ .

[0174] Capacitor element C 12 With input transistor PT 11 Parallel connection. Specifically, capacitor element C 12 The first terminal is connected to the input transistor PT. 11 The source electrode, and the capacitor element C 12 The second terminal is connected to the input transistor PT. 11 The drain electrode. Capacitor element C 12is a band-limiting capacitor.

[0175] input-side clamp transistor PT 13 For example, includes a P-channel MOS transistor, and is connected between the source electrode and the drain electrode of the input transistor PT 11 . The input-side clamp transistor PT 13 has a diode-connected configuration in which the gate electrode and the source electrode are commonly connected, and functions to suppress a decrease in the drain voltage of the input transistor PT 11 when the input transistor PT 11 is in a non-conductive state.

[0176] input-side clamp transistor NT 11 For example, includes an N-channel MOS transistor, and has a drain electrode connected to the source electrode of the input transistor PT 11 and a source electrode connected to the drain electrode of the input semiconductor PT 11 . The input-side clamp transistor NT 11 has a gate electrode to which a predetermined bias voltage biasl is applied.

[0177] A predetermined bias voltage biasl is applied to the gate electrode of the input-side clamp transistor NT 11 . Therefore, regardless of the voltage of the signal line 32, it is possible to limit the lower limit of the drain voltage V 11 of the input transistor PT d , and it is possible to directly prevent the supply of the drain current from stopping.

[0178] output transistor PT 12 For example, includes a P-channel MOS transistor, and is connected between the signal line 32 and the output-side load current source I 12 . Specifically, the output transistor PT 12 has a source electrode connected to the signal line 32 and a drain electrode connected to the first end of the output-side load current source I 12 . Therefore, an analog pixel signal V VSL is input to the source electrode of the output transistor PT 12 through the signal line 32. In order to suppress the back gate effect, the back gate and the source electrode of the output transistor PT 12 are desirably short-circuited.

[0179] output-side load current source I 12 has a second end connected to a low-potential side power supply (for example, a ground GND). The output-side load current source I 12 supplies a constant current to a series circuit of the output transistor PT 12 and the signal line 32.

[0180] output transistor PT12 has a gate electrode connected to the drain electrode of the input transistor PT 11 . Therefore, the drain voltage of the input transistor PT 11 is input to the gate electrode of the output transistor PT 12 .

[0181] The output transistor PT 12 outputs the signal OUT as a comparison result between the analog pixel signal V VSL and the reference signal V RAMP of the ramp wave from the drain electrode through the output terminal T 13 , and the signal OUT indicates whether the voltage difference between the analog pixel signal V VSL input to the source electrode through the signal line 32 and the drain voltage V 11 of the input transistor PT d input to the gate electrode exceeds a predetermined threshold voltage.

[0182] The output-side clamp transistor NT 12 includes, for example, an N-channel MOS transistor, and has a drain electrode connected to the source electrode of the output transistor PT 12 and a source electrode connected to the drain electrode of the output transistor PT 12 . The gate electrode of the output-side clamp transistor NT 12 is applied with a predetermined bias voltage bias2. The output-side clamp transistor NT 12 including the N-channel MOS transistor is capable of limiting the lower limit of the drain voltage of the output transistor PT 12 .

[0183] As described above, the comparator 131 according to the reference example has the circuit structure in which the load current source I 11 that supplies the current to the signal line 32 and the load current source I 12 share the current source of the comparator 131. According to the comparator 131 having the circuit structure, it is possible to reduce the power consumption of the analog-digital converter 130, and in turn, the power consumption of the CMOS image sensor 1. That is, the comparator 131 according to the reference example is a super low power consumption comparator.

[0184] Further, in the comparator 131 according to the reference example, the input transistor PT 11 supplies the drain-source voltage between the gate and the source of the output transistor PT 12 , and therefore, it is possible to invert the comparison result at the timing at which the change of the analog pixel signal V VSL coincides with the change of the reference signal V RAMP of the ramp wave. Therefore, it is possible to reduce the non-linearity caused by the inversion timing error, and it is possible to improve the image quality of the image data.

[0185] (Circuit operation example of comparator)

[0186] Next, an exemplary circuit operation of the comparator 131 having the above-described basic circuit structure will be described. Figure 6 is a timing chart for explaining an exemplary circuit operation of the comparator 131 according to the reference example. Figure 6 The timing chart of shows the timing relationship between the waveforms of the analog pixel signal V VSL , the reference signal V RAMP , the drain voltage V 11 of the input transistor PT d , the comparison result COMP of the comparator 131, and the drive signal AZ of the auto-zero switch SW AZ .

[0187] At the time t1 immediately before the start of analog-digital conversion (AD conversion), the drive signal AZ of the auto-zero switch SW AZ enters an active state (high level state) for a predetermined auto-zero period. Therefore, in response to the drive signal AZ, the auto-zero switch SW AZ is set to an on (closed) state, resulting in a short circuit between the gate electrode and the drain electrode of the input transistor PT 11 , and an initialization operation of the comparator 131, i.e., an auto-zero operation, is performed.

[0188] After the auto-zero operation, the reference signal generation section 16 starts outputting the reference signal V RAMP at the time t2. The reference signal V RAMP is a ramp signal whose level (voltage) monotonously decreases over time.

[0189] Meanwhile, in the CMOS image sensor 1, a noise removal process is generally performed by correlated double sampling (CDS) so as to remove noise at the time of the reset operation of the pixel 20. Therefore, for example, the reset level (P-phase) V VSL_P and the signal level (D-phase) V VSL_D are read from the pixel 20 as pixel signals.

[0190] When the floating diffusion FD of the pixel 20 has been reset, the reset level V VSL_P corresponds to the potential of the floating diffusion FD. The signal level V VSL_D corresponds to the potential obtained by photoelectric conversion by the photodiode 21, i.e., the potential of the floating diffusion FD when the charge accumulated in the photodiode 21 is transferred to the floating diffusion FD.

[0191] Suppose that the reference signal V RAMP , which gradually decreases over time, is input to the comparator 131 at the time t3 together with the reset level V VSL_PIntersection. Here, assume that the input transistor PT at time t3 is... 11 Drain voltage V d Defined as V d_P The voltage will be lower than the drain voltage V. d_P The voltage is set to low and will be equal to or higher than the drain voltage V. d_p The voltage is set to high level, and the input transistor PT is applied around time t3. 11 Drain voltage V d Invert from low level to high level.

[0192] Then, initialize the reference signal V. RAMP And starting from time t4, the reference signal V is gradually decreased. RAMP Simultaneously, in pixel 20, charge is transferred from photodiode 21 to floating diffuser FD, and signal level V is... VSL_D As a pixel signal output. The signal level V VSL_D Set to the reset level V VSL-P The level of low ΔV.

[0193] Then, assume a reference signal V whose voltage gradually decreases over time. RAMP At time t5, the signal level V VSL_D Intersection. Here, assume that the input transistor PT is at time t5. 11 Drain voltage V d Defined as V d_d Drain voltage V d_d The value is greater than the drain voltage V d_p Low ΔV. That is, the drain voltage V at time t5. d_d Because at this time, the signal level V, which is the pixel signal, is... VSL_d It becomes a lower value due to its lower value.

[0194] At reset level V VSL_p During the conversion, the input transistor PT 11 Drain voltage V d_d From drain voltage V d_p The drain voltage V decreases by ΔV. In related technologies, the drain voltage V is determined. d The time reversal occurs at time t6 after time t5. Therefore, if the drain voltage V is used... d_p The comparison result COMP of comparator 131 is generated. The time when the comparison result COMP reverses (around time t6) deviates from the reference signal V. RAMP With signal level V VSL_D The ideal moment of intersection (around t5). Therefore, the analog-to-digital converter 130 exhibits linearity errors and offsets, and there is a possibility that the image quality of the image data will deteriorate due to these errors.

[0195] On the other hand, in the comparator 131 according to the reference example, the output transistor PT 11 is provided at a subsequent stage of the input transistor PT 12 , and the source electrode and the drain electrode of the input transistor PT 11 are connected to the source electrode and the gate electrode of the output transistor PT 12 . With this connection, the drain-source voltage V 11 of the input transistor PT ds is input to the output transistor PT 12 as its gate-source voltage.

[0196] As shown in the timing chart of FIG. 9, at the time t3 and the time t5 at which the reference signal V RAMP and the pixel signal V VSL intersect, the amount of voltage drop ΔV of the pixel signal V VSL is the same as the amount of voltage drop of the drain voltage V 11 of the input transistor PT d . Therefore, the drain-source voltage V ds has the same value at these times. At this time (i.e., at the time t3 and the time t5), the value of the drain-source voltage V ds is the same as that at the time of automatic zeroing. Since the drain-source voltage V 11 of the input transistor PT ds is the gate-source voltage of the output transistor PT 12 , the drain voltage of the output transistor PT 12 inverts around the time t3 and the time t5.

[0197] Since the time of inversion of the comparison result COMP of the comparator 131 corresponds to the ideal time at which the reference signal V RAMP and the signal level V VSL_D intersect, the error of the inversion timing is suppressed. Therefore, compared to the case where the drain voltage V 11 of the input transistor PT d_p is used to generate the comparison result COMP, the image quality of the image data can be improved by reducing the linearity error and the offset.

[0198] Next, why the amount of voltage drop ΔV of the drain voltage V 11 of the input transistor PT d at the time t3 and the time t5 is the same as the amount of voltage drop of the pixel signal V 11 input to the source electrode of the input transistor PT VSL will be described.

[0199] Figure 7 is a graph showing the drain voltage V 11 of the input transistor PT11 characteristic diagram of exemplary characteristics of the P-channel MOS transistor. In Figure 6 In the characteristic diagram, the vertical axis represents the drain current, and the horizontal axis represents the drain-source voltage. Further, the broken line represents a boundary between a linear region and a saturation region.

[0200] Generally, the operating point of the P-channel MOS transistor is determined so as to operate in the saturation region at the time of auto-zero. The drain current I d is represented by the following equation (1).

[0201] I d = (1 / 2) · μC OX (W / L) · (V GS -V th ) 2 (1+λV ds ) (1)

[0202] Here, μ is the electron mobility, C OX is the capacitance per unit area of the MOS capacitor, W is the gate width, L is the gate length, V th is the threshold voltage, and λ is a predetermined coefficient.

[0203] Since the input transistor PT 11 is a P-channel MOS transistor, equation (1) holds in the saturation region. At this time, the drain current I 11 of the input transistor PT d is a constant value I 11 supplied by the input-side load current source I d1 . Further, the electron mobility μ, the unit capacitance C OX , the gate width W, the gate length L, the threshold voltage V th , and the coefficient λ are constant values.

[0204] Further, when the reference signal V 11 input to the gate electrode of the input transistor PT RAMP intersects the pixel signal V VSL input to the source electrode, the gate-source voltage V gs has a constant value determined at the time of auto-zero.

[0205] Therefore, when the reference signal V 11 input to the gate electrode of the input transistor PT RAMP intersects the pixel signal V VSL input to the source electrode, the drain-source voltage V ds according to equation (1) also has a constant value. This constant drain-source voltage is assumed to be V ds1Then, the following equations (2) and (3) hold at time t3 and time t5.

[0206] V ds1 = V VSL_P - V d_P (2)

[0207] V ds1 = V VSL_D - V d_d (3)

[0208] When the drain-source voltage V ds1 is eliminated from equation (2) and equation (3), the following equation (4) is obtained.

[0209] V VSL_P - V VSL_D = V d_p - V d_d (4)

[0210] Note that in the case where the operating point is determined so that the P-channel MOS transistor operates in the linear region at the time of auto-zero, equation (1) has a different form, but equation (4) similarly holds.

[0211] According to equation (4), the amount of voltage drop ΔV 11 of the drain voltage V d of the input transistor PT VSL becomes the same as the amount of voltage drop of the pixel signal V RAMP input to the source electrode. Therefore, the timing relationship shown in the timing chart of FIG. 8 can be obtained. Figure 8

[0212] (Regarding Buffer Noise)

[0213] Meanwhile, in a single slope A / D converter, for the purpose of increasing the driving force of the reference signal V 11 of the ramp wave supplied to the comparator of each pixel column and reducing the output impedance, a buffer is provided in front of the capacitive element C RAMP which is configured to absorb offset. At this time, the noise of the buffer adversely affects the comparator, and therefore, for example, in a conventional comparator having a differential amplifier configuration, the output terminal of the buffer is connected between the pixel columns, and the noise of the buffer is reduced by averaging.

[0214] However, in the ultra-low power comparator 131 according to the above-described reference example, kickback is large, and it is difficult to connect the output terminal of the buffer 50 between the pixel columns. Figure 9The pixel columns marked with an 'x' are arranged to avoid interference with other pixel columns, specifically stripes (stripes noise). Therefore, it is difficult to average the noise of buffer 50 across the pixel columns; thus, the noise of buffer 50 remains constant without attenuation, thereby worsening the noise of the entire comparator 131. Here, "feedback" is the phenomenon where the potential changes (fluctuates) with the injection or removal of charge.

[0215] Note that regarding noise that adversely affects the analog-to-digital converter 13, examples have been given here of noise arranged in the capacitor element C. 11 The noise of the buffer 50 mentioned above is used as an example to illustrate its problem. However, noise that adversely affects the analog-to-digital converter 13 is not limited to the noise of the buffer 50. For example, even in the capacitor element C 11 There is no buffer 50 in front of the ramp reference signal V. RAMP Noise in the reference signal generation unit 16 can also cause image quality problems in the image data.

[0216] <Simplification of the present invention>

[0217] The comparator 131 according to an embodiment of the present invention is an ultra-low power comparator, which includes a load current source connected to the load current source (specifically, the input-side load current source I). 11 The input transistor PT between signal line 32 and signal line 32 11 Additionally, such as Figure 10 As shown, the comparator 131 according to this embodiment includes: a first capacitor 51, which supplies power to the input transistor PT. 11 The gate electrode is input with a predetermined reference signal, specifically, the reference signal V of the ramp wave. RAMP ; and a second capacitor 52, which is connected to the input transistor PT. 11 Between the gate electrode and the reference potential node (e.g., ground).

[0218] In the comparator 131 according to this embodiment, which has the above-described structure, for example, in order to increase the reference signal V of the ramp wave... RAMP To achieve the driving force and reduce output impedance, buffer 50 is placed on top of input transistor PT. 11 The case of the gate input side. Even in this case, the comparator 131 according to this embodiment, having the above-described configuration, can reduce the input-to-input transistor PT by utilizing the capacitive attenuation of the capacitive voltage division using the first capacitor 51 and the second capacitor 52, even if the output of the buffer 50 is not connected between pixel columns. 11 The noise of the gate electrode buffer 50 is reduced. This not only reduces the noise of the buffer 50, but also reduces the noise of the reference signal V in the ramp wave. RAMPThe noise in the reference signal generation unit 16 is reduced. Furthermore, even without the buffer 50, the noise in the reference signal V on the ramp can be reduced by using capacitive attenuation through capacitive voltage division between the first capacitor 51 and the second capacitor 52. RAMP Noise in the reference signal generation unit 16.

[0219] The following will explain the reference signal V, which includes the ramp wave. RAMP Input to input transistor PT 11 The first capacitor 51 of the gate electrode and connected to the input transistor PT 11 A specific example of the comparator 131 according to this embodiment is the second capacitor 52 between the gate electrode and the reference potential node.

[0220] [Example 1]

[0221] Example 1 is an example of using a variable capacitor element with a variable capacitance value as either the first capacitor 51 or the second capacitor 52. Figure 10 An example of the circuit structure of comparator 131 according to embodiment 1 is shown.

[0222] like Figure 4 As shown, in the comparator 131 according to Embodiment 1, a variable capacitor element VC having a variable capacitance value is used. RAMP Used as the first capacitor 51, and a variable capacitor element VC with a variable capacitance value. VSS Used as a second capacitor 52. Variable capacitance element VC RAMP Connected to the output of buffer 50 and the input transistor PT 11 Between the gate electrodes, and the reference signal V of the ramp input via buffer 50. RAMP Applied to the input transistor PT 11 The gate electrode. Variable capacitor element VC VSS Connected to the input transistor PT 11 Between the gate electrode and the reference potential node (e.g., ground).

[0223] Using the comparator 131 according to Embodiment 1 with the above-described structure, the first capacitor 51 and the second capacitor 52 each include a variable capacitance element VC. RAMP and variable capacitor element VC VSS Furthermore, since the capacitance value is variable, the attenuation ratio of the capacitor attenuation using capacitor voltage division can be arbitrarily set during noise reduction. For example, the attenuation ratio of the variable capacitor element VC can be set according to the analog gain of the analog-to-digital converter 130 including comparator 131. RAMP and variable capacitor element VC VSS The attenuation ratio of the capacitor attenuation.

[0224] For example, the analog gain of the analog-digital converter 130 depends on the slope of the ramp wave of the reference signal V RAMP generated by the reference signal generation section 16 (refer to Figure 11A ). As Figure 4 shown in FIG. 6, in a case where the slope of the ramp wave of the reference signal V RAMP is gentle, the time to the intersection with the pixel signal V VSL is long, and the count of the counter 132 (refer to Figure 11B ) increases. This corresponds to increasing the analog gain of the analog-digital converter 130. Therefore, as Figure 35 shown in FIG. 6, the amplitude of the ramp wave of the reference signal V RAMP is inversely proportional to the analog gain of the analog-digital converter 130. The slope of the ramp wave of the reference signal V RAMP may be set in the reference signal generation section 16, for example, based on a DAC setting signal (refer to Figure 12 ) to be described later.

[0225] Note that according to the comparator 131 of Embodiment 1, the noise of the buffer 50 or the like can be reduced by using the voltage division by the capacitances of the first capacitor 51 and the second capacitor 52, but at the same time, the amplitude of the ramp wave (voltage of the ramp waveform) of the reference signal V RAMP is also attenuated. Therefore, it is necessary to set the ramp wave amplitude of the reference signal V RAMP to be large in advance in the reference signal generation section 16 so that the amplitude after the attenuation due to the voltage division becomes the desired amplitude.

[0226] [Embodiment 2]

[0227] Embodiment 2 is an example in which the first capacitor 51 and the second capacitor 52 include a combination of a plurality of capacitive elements and a plurality of switching elements. Figure 12 An example of the circuit structure of the comparator 131 according to Embodiment 2 is shown.

[0228] As Figure 12 shown in FIG. 7, the comparator 131 according to Embodiment 2 has a configuration in which the first capacitor 51 and the second capacitor 52 include a combination of a plurality of capacitive elements and a plurality of switching elements, for example, a combination of four capacitive elements C1 to C4 and four switching elements SW1 to SW4. Each of the four capacitive elements C1 to C4 has a first end connected to the gate electrode of the input transistor PT 11 . Among the four switching elements SW1 to SW4, three switching elements SW1 to SW3 are connected between the second ends of the four capacitive elements C1 to C4.

[0229] Specifically, the switching element SW1 is connected between the second terminal of the capacitance element C1 and the second terminal of the capacitance element C2. The switching element SW2 is connected between the second terminal of the capacitance element C2 and the second terminal of the capacitance element C3. The switching element SW3 is connected between the second terminal of the capacitance element C3 and the second terminal of the capacitance element C4. Further, the switching element SW4 is connected between the reference potential node side (for example, ground) and the second terminal of the capacitance element C4 which is located on the reference potential node side among the four capacitance elements C1 to C4.

[0230] In the comparator 131 according to Embodiment 2 having the above-described configuration, by setting only one of the four switching elements SW1 to SW4 to the off (open) state and the remaining three to the on (closed) state, it is possible to change the capacitance values of the first capacitor 51 and the second capacitor 52. Note that, Figure 13 The circuit structure shown is an example, and the present application is not limited to this circuit structure. That is, the number of the plurality of capacitance elements and the number of the plurality of switching elements are not limited to four.

[0231] Hereinafter, a specific example of the capacitance attenuation ratio will be described, in which only one of the four switching elements SW1 to SW4 is set to the off state and the remaining three are set to the on state.

[0232] (Specific Example 1)

[0233] Specific Example 1 is an example in the case where the capacitance attenuation ratio is 4 / 4 (no attenuation). Figure 13 A circuit structure example according to Specific Example 1 of the capacitance attenuation ratio is shown.

[0234] As Figure 14 shown, in Specific Example 1, only the switching element SW4 which is connected between the second terminal of the capacitance element C4 and the reference potential node among the four switching elements SW1 to SW4 is set to the off state, and the remaining three switching elements SW1 to SW3 are set to the on state.

[0235] In the case of Specific Example 1, the four capacitance elements C1 to C4 are connected in parallel between the output terminal of the buffer 50 and the gate electrode of the input transistor PT 11 In this case, there is no second capacitor 52. Therefore, in the case where only the switching element SW4 is turned off and the remaining three switching elements SW1 to SW3 are turned on, no capacitance division using the first capacitor 51 and the second capacitor 52 occurs, and thus the capacitance attenuation ratio becomes 4 / 4 (no attenuation).

[0236] (Specific Example 2)

[0237] Specific Example 2 is an example in the case where the capacitance attenuation ratio is 3 / 4. Figure 14A circuit configuration example according to a specific example 2 of the capacitance attenuation ratio is shown.

[0238] As shown in Figure 15 , in the specific example 2, only the switching element SW3 among the four switching elements SW1 to SW4 is set to the off state, and the remaining three switching elements SW1, SW2, and SW4 are set to the on state.

[0239] In the case of the specific example 2, the three capacitance elements C1 to C3 are connected in parallel between the output terminal of the buffer 50 and the gate electrode of the input transistor PT 11 , a first capacitor 51 is formed, and the capacitance element C4 on the reference potential node side forms a second capacitor 52. Therefore, in a case where only the switching element SW3 is turned off and the remaining three switching elements SW1, SW2, and SW4 are turned on, the capacitance attenuation ratio becomes 3 / 4.

[0240] (Specific example 3)

[0241] The specific example 3 is an example in a case where the capacitance attenuation ratio is 2 / 4. Figure 15 A circuit configuration example according to a specific example 3 of the capacitance attenuation ratio is shown.

[0242] As shown in Figure 16 , in the specific example 3, only the switching element SW2 among the four switching elements SW1 to SW4 is set to the off state, and the remaining three switching elements SW1, SW3, and SW4 are set to the on state.

[0243] In the case of the specific example 3, the two capacitance elements C1 and C2 are connected in parallel between the output terminal of the buffer 50 and the gate electrode of the input transistor PT 11 , a first capacitor 51 is formed, and the two capacitance elements C3 and C4 on the reference potential node side are connected in parallel between the gate electrode of the input transistor PT 11 and the reference potential node, a second capacitor 52 is formed. Therefore, in a case where only the switching element SW2 is turned off and the remaining three switching elements SW1, SW3, and SW4 are turned on, the capacitance attenuation ratio becomes 2 / 4.

[0244] (Specific example 4)

[0245] The specific example 4 is an example in a case where the capacitance attenuation ratio is 1 / 4. Figure 16 A circuit configuration example according to a specific example 4 of the capacitance attenuation ratio is shown.

[0246] As shown in Figure 18 , in the specific example 4, only the switching element SW1 connected to the output terminal of the buffer 50 among the four switching elements SW1 to SW4 is set to the off state, and the remaining three switching elements SW2 to SW4 are set to the on state.

[0247] In the case of the specific example 4, only one capacitive element C1 is connected between the output of the buffer 50 and the gate electrode of the input transistor PT 11 to form the first capacitor 51, and the remaining three capacitive elements C2 to C4 are connected in parallel between the gate electrode of the input transistor PT 11 and the reference potential node to form the second capacitor 52. Thus, when only the switching element SW1 is turned off and the remaining 3 switching elements SW2 to SW4 are turned on, the capacitance attenuation ratio becomes 1 / 4.

[0248] As described above, in the comparator 131 according to the embodiment 2, the attenuation amount (capacitance attenuation ratio) is set by switching the capacitive elements C1 to C4 to reduce the noise of the buffer 50 and the noise of the reference signal generation section 16 on the slope of the reference signal V RAMP .

[0249] [Embodiment 3]

[0250] The embodiment 3 is a modification of the embodiment 2, and is an example in which the analog gain of the analog-digital converter 130 is finely controlled. Figure 18 A circuit structure example of the comparator 131 according to the embodiment 3 is shown.

[0251] In the case of the comparator 131 according to the above-described embodiment 2, the attenuation amount can only be changed in a stepwise manner by switching the capacitive elements C1 to C4. Thus, in the comparator 131 according to the embodiment 3, the reference signal generation section 16 adjusts the slope of the slope of the reference signal V RAMP to continuously control the analog gain of the analog-digital converter 130. Thus, the analog gain can be finely controlled.

[0252] Specifically, as shown in Figure 35 , the analog gain control section 53 is provided, and under the control of the analog gain control section 53, the control of the analog gain of the analog-digital converter 130 and the control of the attenuation amount (capacitance attenuation ratio) are performed by switching the capacitive elements C1 to C4. Since the amplitude of the slope of the reference signal V RAMP is inversely proportional to the analog gain of the analog-digital converter 130, the analog gain control section 53 controls the analog gain with respect to the amplitude of the slope of the reference signal generation section 16 that generates the slope of the reference signal V RAMP .

[0253] For example, the analog gain control section 53 can also function as the control section 17 (refer to Figure 17A ) that controls the analog gain of the analog-digital converter 130 in accordance with the illuminance data that will be described later. As Figure 17B and Figure 19As shown, the analog gain control section 53 adjusts the amplitude of the ramp wave of the reference signal V RAMP by adjusting the reference signal V RAMP in a range where the capacitance value is not switched. Then, when the capacitance value is switched by one step, the attenuation amount is switched by one step, and thus the amplitude of the ramp wave and the capacitance values of the first capacitor 51 and the second capacitor 52 are controlled so that the amplitude of the ramp wave returns to the original value. With this control, when the capacitance value is switched, the amplitude of the ramp wave of the reference signal V RAMP is also discontinuously switched.

[0254] Note that the amplitude of the ramp wave of the reference signal V 11 is originally large on the low analog gain side, and thus the capacitive attenuation is hardly applied. However, since the quantization noise is large and the noise requirement is not as strict as when the analog gain is high, there is no problem. The effect of the capacitive attenuation can be greatly applied on the high analog gain side where the noise reduction is strictly required.

[0255] [Embodiment 4]

[0256] Embodiment 4 is an example in which a switching element is not provided on the reference potential node side. Figure 19 A circuit structure example of the comparator 131 according to Embodiment 4 is shown.

[0257] As shown, the comparator 131 according to Embodiment 4 has a configuration in which the first capacitor 51 and the second capacitor 52 include a combination of four capacitive elements C1 to C4 and three switching elements SW1 to SW3. Each of the four capacitive elements C1 to C4 has a first end connected to the gate electrode of the input transistor PT VSL . The three switching elements SW1 to SW3 are connected between second ends of the four capacitive elements C1 to C4.

[0258] Specifically, the switching element SW1 is connected between the second end of the capacitive element C1 and the second end of the capacitive element C2. The switching element SW2 is connected between the second end of the capacitive element C2 and the second end of the capacitive element C3. The switching element SW3 is connected between the second end of the capacitive element C3 and the second end of the capacitive element C4. Then, a common connection node between the capacitive element C4 and the switching element SW3 is connected to the reference potential node (for example, ground).

[0259] The comparator 131 according to Embodiment 4 having the above-described configuration has a circuit structure example in which a switching element is not provided on the reference potential node side, that is, a circuit structure example in which the switching element SW4 of the comparator 131 according to Embodiment 2 is omitted. In the case of the circuit structure example of Embodiment 4, it is difficult to realize the off (on) state of the switching element SW4 in Embodiment 2, that is, the state in which the capacitive attenuation ratio is 4 / 4 (no attenuation), but when the analog pixel signal V 11When the dynamic range is relatively small, this circuit structure example can be used, and it can reduce the area of ​​a switching element and control logic.

[0260] [Example 5]

[0261] Example 5 includes three capacitor elements and three switching elements. Figure 20 An example circuit structure of comparator 131 according to Example 5 is shown.

[0262] like Figure 21 As shown, the comparator 131 according to Example 5 has a configuration in which the first capacitor 51 and the second capacitor 52 comprise a combination of three capacitive elements C1 to C3 and three switching elements SW1 to SW3. Each of the three capacitive elements C1 to C3 is connected to the input transistor PT. 11 The first terminal of the gate electrode. Three switching elements SW1 to SW3 are connected between the second terminals of three capacitor elements C1 to C3.

[0263] Specifically, switching element SW1 is connected between the second terminal of capacitor element C1 and the second terminal of capacitor element C2. Switching element SW2 is connected between the second terminal of capacitor element C2 and the second terminal of capacitor element C3. Furthermore, switching element SW3 is connected between the reference potential node (e.g., ground) and the second terminal of capacitor element C3 located on the reference potential node side of the three capacitor elements C1 to C3.

[0264] In the comparator 131 with the above-described configuration according to Example 5, when switching elements SW1 and SW2 are turned on (closed) and switching element SW3 is turned off (opened), the capacitance attenuation ratio becomes 3 / 3 (no attenuation). When switching elements SW1 and SW3 are turned on and switching element SW2 is turned off, the capacitance attenuation ratio becomes 2 / 3. When switching element SW1 is turned off and switching elements SW2 and SW3 are turned on, the capacitance attenuation ratio becomes 1 / 3.

[0265] At the same time, when relative to the reference signal V RAMP When the input capacitance, including the first capacitor 51 and the second capacitor 52, is finely divided, the noise step before and after the analog gain point used to switch the capacitor elements becomes smaller, and the noise changes more smoothly relative to the change in analog gain. From this perspective, it can be said that the comparator 131 with four capacitor elements according to Embodiment 2 is superior to the comparator 131 with three capacitor elements according to Embodiment 5.

[0266] On the other hand, when the number of divisions of the input capacitance is made coarse, the number of switching elements decreases, the area decreases, the unit capacitance increases, and thus the gain variation due to mismatch also decreases. Incidentally, if there is a gain variation between pixel columns, it is displayed as vertical stripes. From this perspective, it can be said that the comparator 131 having three capacitance elements according to Embodiment 5 is superior to the comparator 131 having four capacitance elements according to Embodiment 2.

[0267] [Embodiment 6]

[0268] Embodiment 6 is a modification of Embodiment 5, and is an example in which the connection relationship between the capacitance elements and the switching elements is different. Figure 21 An example of the circuit structure of the comparator 131 according to Embodiment 6 is shown.

[0269] As Figure 22 shown, the comparator 131 according to Embodiment 6 has a circuit structure in which the first capacitor 51 and the second capacitor 52 include a combination of three capacitance elements C1 to C3 and three switching elements SW1 to W3, and the connection relationship between the capacitance elements C1 to C3 and the switching elements SW1 to SW3 is different from that of Embodiment 5.

[0270] Specifically, the three capacitance elements C1 to C3 are connected in series between the output terminal of the buffer 50 and a reference potential node (for example, ground). The switching elements SW1 to SW3 have a first terminal each connected to the output terminal of the capacitance elements C1 to C3, and a second terminal connected to the gate electrode of the input transistor PT 11 .

[0271] In the comparator 131 according to Embodiment 6 having the above-described configuration, the operation of switching the capacitance attenuation ratio is different from that of Embodiment 5. Specifically, when the switching element SW1 is turned on (closed) and the switching elements SW2 and SW3 are turned off (opened), the capacitance attenuation ratio becomes 2 / 3. When the switching element SW2 is turned on and the switching elements SW1 and SW3 are turned off, the capacitance attenuation ratio becomes 1 / 3.

[0272] With the comparator 131 according to Embodiment 6 having the above-described configuration, the advantage is that the load observed from the buffer 50 becomes constant, and the response difference when switching the capacitance elements C1 to C3 is less likely to become an output error.

[0273] [Embodiment 7]

[0274] Embodiment 7 is an example in which the circuit structure of the comparator 131 is different from that of Embodiments 1 to 6. Figure 22 An example of the circuit structure of the comparator 131 according to Embodiment 7 is shown.

[0275] AsFigure 23 The comparator 131 according to Embodiment 7 has a circuit structure in which an input-side cascode connection transistor PT 14 and an output-side cascode connection transistor PT 15 are further provided, as shown. For example, a P-channel MOS transistor can be used as the input-side cascode connection transistor PT 14 and the output-side cascode connection transistor PT 15 .

[0276] The input-side cascode connection transistor PT 14 is connected between the input transistor PT 11 and the input-side load current source I 11 . A predetermined bias voltage bias3 is applied to the gate electrode of the input-side cascode connection transistor PT 14 . The output-side cascode connection transistor PT 15 is connected between the output transistor PT 12 and the output-side load current source I 12 . A predetermined bias voltage bias4 is applied to the gate electrode of the output-side cascode connection transistor PT 15 .

[0277] With the comparator 131 according to Embodiment 7 having the above-described configuration, the influence of feedback can be reduced by further including the input-side cascode connection transistor PT 14 and the output-side cascode connection transistor PT 15 , and thus the interference between pixel columns can be reduced.

[0278] [Embodiment 8]

[0279] Embodiment 8 is an example applied to a CMOS image sensor having a function of suppressing power supply noise of a pixel power supply. Figure 23 An example of a circuit structure of an analog-digital converter 130 according to Embodiment 8 is shown.

[0280] In a CMOS image sensor, noise of a pixel power supply (hereinafter, in some cases, simply referred to as "power supply noise") sometimes rides on a signal line 32 that is an input of the analog-digital converter 130 via a parasitic capacitance C p , and the like of the pixel 20. The power supply noise on the signal line 32 is visually recognized as horizontal stripe-shaped noise as an image.

[0281] For example, in order to suppress such power supply noise, a power supply noise correction circuit 60 called a PSRR correction circuit is installed on the CMOS image sensor. Here, the power supply rejection ratio (PSRR) of the PSRR correction circuit is a performance index indicating how much power supply noise can be suppressed.

[0282] In the CMOS image sensor using a conventional comparator having a differential amplifier configuration, the power supply noise correction circuit 60 captures power supply noise from a pixel power supply, performs correction gain adjustment and frequency characteristic adjustment according to the power supply noise, and then converts to a correction current, and adds the correction current to the reference signal V RAMP of the ramp wave in the comparator 131. The correction current is added to the reference signal V Figure 23 of the ramp wave in the comparator 131. The correction current is added to the reference signal V

[0283] When the power supply noise suppression function in the case of the conventional comparator having the above-described differential amplifier configuration is directly applied to the single slope and ultra low power analog-digital converter 130 including the comparator 131 according to each of Embodiments 1 to 7, the correction gain adjustment range and the number of correction gain adjustment stages in the power supply noise correction circuit 60 greatly increase in order to cover the variation in the capacitance attenuation caused by switching the input capacitance of the comparator 131.

[0284] Therefore, in Embodiment 8, when the slope of the ramp wave of the reference signal V RAMP and the input capacitance of the comparator 131 are both switched in the analog gain control of the analog-digital converter 130, the additional gain provided to the power supply noise correction circuit 60 is switched in cooperation with the switching of the input capacitance. The correction current output from the power supply noise correction circuit 60 is supplied to the reference signal generation section 16.

[0285] In the present embodiment, as shown in Figure 4 , the reference signal generation section 16 has a current drive type digital-analog conversion circuit (DAC) configuration including a ramp wave generation digital signal generation section 161, a variable current source 162, and an output resistor 163. Then, the correction current output from the power supply noise correction circuit 60 flows into the output resistor 163 to be converted to a voltage, and is added to the reference signal V RAMP of the ramp wave.

[0286] The PSRR gain and frequency characteristics are adjusted and corrected by an adjustment function for correcting the gain and frequency characteristics initially included in the power supply noise correction circuit 60 (i.e., the PSRR correction circuit) until the power supply noise reaches the comparator 131 via the pixel 20 and the signal line 32. The control register for correcting the gain and frequency characteristics is, for example, built in the logic circuit section 14 of Figure 24 , and adjustment is performed to reach the optimum value as described below.

[0287] If there is a variation in the amount of the capacitive attenuation caused by the switching of the input capacitance of the comparator 131, it is difficult to eliminate the power supply noise on the signal line 32 only by the comparator 131. Therefore, in the power supply noise correction circuit 60, under the control of the analog gain control section 53, the additional gain switching circuit 70 performs a compensation operation of the amount of the capacitive attenuation in coordination with the switching of the input capacitance of the comparator 131. Specifically, in the additional gain switching circuit 70, the amount of the capacitive attenuation is compensated by switching the gain of the power supply noise correction circuit 60, more specifically, an additional gain other than the correction gain initially held by the power supply noise correction circuit 60, in coordination with the switching of the input capacitance of the comparator 131, i.e., in coordination with the switching of the capacitance values of each of the first and second capacitors 51 and 52.

[0288] In this way, it is possible to compensate the amount of the capacitive attenuation by switching the additional gain provided to the power supply noise correction circuit 60 in coordination with the switching of the input capacitance of the comparator 131, and therefore, it is possible to suppress the power supply noise on the signal line 32 while absorbing the influence of the switching of the input capacitance of the comparator 131.

[0289] Hereinafter, a specific operation example of the switching of the input capacitance of the comparator 131 and the gain control will be described.

[0290] (Operation Example 1)

[0291] Operation Example 1 is an operation example in the case where the capacitive attenuation ratio is 4 / 4 (no attenuation). Figure 25 An operation explanatory diagram of Operation Example 1 is shown.

[0292] The case where the capacitive attenuation ratio is 4 / 4 corresponds to Specific Example 1 of Embodiment 2, and only the switching element SW4 connected between the second terminal of the capacitive element C4 and the reference potential node among the four switching elements SW1 to SW4 is set to the off state, and the remaining three switching elements SW1 to SW3 are set to the on state. In this case, there is no attenuation, and therefore, under the control of the analog gain control section 53, a gain of one times is set in the additional gain switching circuit 70 of the power supply noise correction circuit 60.

[0293] (Operation Example 2)

[0294] Operation Example 2 is an operation example in a case where the capacitance attenuation ratio is 3 / 4. Figure 26 An operation explanatory diagram of Operation Example 2 is shown.

[0295] The case where the capacitance attenuation ratio is 3 / 4 corresponds to Specific Example 2 of Embodiment 2, and only the switching element SW3 among the four switching elements SW1 to SW4 is set to the off state, and the remaining three switching elements SW1, SW2, and SW4 are set to the on state. In this case, under the control of the analog gain control section 53, a gain of 4 / 3 corresponding to the 3 / 4 capacitance attenuation ratio is set in the additional gain switching circuit 70 of the power supply noise correction circuit 60. Therefore, it is possible to suppress the power supply noise on the signal line 32 while absorbing the influence of the switching of the input capacitance of the comparison circuit 131.

[0296] (Operation Example 3)

[0297] Operation Example 3 is an operation example in a case where the capacitance attenuation ratio is 2 / 4. Figure 27 An operation explanatory diagram of Operation Example 3 is shown.

[0298] The case where the capacitance attenuation ratio is 2 / 4 corresponds to Specific Example 3 of Embodiment 2, and only the switching element SW2 among the four switching elements SW1 to SW4 is set to the off state, and the remaining three switching elements SW1, SW3, and SW4 are set to the on state. In this case, under the control of the analog gain control section 53, a gain of two corresponding to the 2 / 4 capacitance attenuation ratio is set in the additional gain switching circuit 70 of the power supply noise correction circuit 60. Therefore, it is possible to suppress the power supply noise on the signal line 32 while absorbing the influence of the switching of the input capacitance of the comparison circuit 131.

[0299] (Operation Example 4)

[0300] Operation Example 4 is an operation example in a case where the capacitance attenuation ratio is 1 / 4. Figure 28 An operation explanatory diagram of Operation Example 4 is shown.

[0301] The case where the capacitance attenuation ratio is 1 / 4 corresponds to Specific Example 4 of Embodiment 2, and among the four switching elements SW1 to SW4, only the switching element SW1 connected to the output end of the buffer 50 is set to the off state, and the remaining three switching elements SW2 to SW4 are set to the on state. In this case, under the control of the analog gain control section 53, a gain of four corresponding to the 1 / 4 capacitance attenuation ratio is set in the additional gain switching circuit 70 of the power supply noise correction circuit 60. Therefore, it is possible to suppress the power supply noise on the signal line 32 while absorbing the influence of the switching of the input capacitance of the comparison circuit 131.

[0302] Note that the reference signal generating section 16 is not limited to the current drive type digital analog conversion circuit (DAC) configuration including the variable current source 162 and the output resistor 163. For example, as shown in Figure 29 , a circuit structure in which an adder 80 is provided and a correction current output from the power supply noise correction circuit 60 is added to the reference signal V RAMP ref generated by the reference signal generating section 16 can also be employed.

[0303] [Embodiment 9]

[0304] Embodiment 9 is an example of a circuit structure of the power supply noise correction circuit 60. Figure 29 An exemplary circuit structure of the power supply noise correction circuit 60 according to Embodiment 9 is shown.

[0305] As shown in Figure 23 , the power supply noise correction circuit 60 includes, in addition to the conductance fixed bias section 61, the input sensing section 62, the first bias section 63, the frequency characteristic adjustment section 64, the correction gain adjustment section 65, and the second bias section 66, an additional gain switching circuit 70.

[0306] The conductance fixed bias section 61 includes two P-channel MOS transistors PT 71 and PT 72 with a common gate electrode, two N-channel MOS transistors NT 71 and NT 72 with a common gate electrode, and a resistance element R 71 . The P-channel MOS transistors PT 72 and the N-channel MOS transistors NT 71 all have a diode connection configuration in which the gate electrode and the drain electrode are short-circuited.

[0307] The P-channel MOS transistors PT 71 and the N-channel MOS transistors NT 71 are connected in series between a high-potential side power supply and a low-potential side power supply (e.g., ground). The P-channel MOS transistors PT 72 , the N-channel MOS transistors NT 72 , and the resistance element R 71 are connected in series between the high-potential side power supply and the low-potential side power supply.

[0308] The input sensing section 62 includes a switching element SW 71 , a capacitance element C 71 , and N-channel MOS transistors NT 73 . The switching element SW 71 has the N-channel MOS transistors NT 71 and NT 72the first ends of the gate electrodes of each of the P-channel MOS transistors PT 73 and the second end of the gate electrode of the N-channel MOS transistor NT 71 The capacitor element C 71 is connected between the power supply terminal T 73 connected to the pixel power supply and the gate electrode of the N-channel MOS transistor NT 72 .

[0309] The first biasing section 63 includes a switching element SW 72 , a capacitor element C 73 , and a P-channel MOS transistor PT 72 . The switching element SW 71 has the first ends of the gate electrodes of each of the P-channel CMOS transistors PT 72 and PT 73 connected to the conductance fixed biasing section 61, and the second end of the gate electrode of the P-channel MOS transistor PT 72 . The capacitor element C 73 is connected between the high-potential-side power supply and the gate electrode of the P-channel MOS transistor PT

[0310] The P-channel MOS transistor PT 73 of the first biasing section 63 and the N-channel MOS transistor NT 73 of the input sensing section 62 are connected in series between the high-potential-side power supply and the low-potential-side power supply. Here, a node common to the drain of the P-channel MOS transistor PT 73 and the N-channel MOS transistor NT 73 is defined as a node N 71 .

[0311] The frequency characteristic adjustment section 64 includes a variable capacitor element VC 71 having a variable capacitance value, and connected between the high-potential-side power supply and the node N 71 , that is, in parallel with the P-channel MOS transistor PT 73 of the first biasing section 63. The frequency characteristic adjustment section 64 is configured to be able to adjust the frequency characteristic by adjusting the capacitance value of the variable capacitor element VC 71 .

[0312] The correction gain adjustment section 65 includes a size-adjustable P-channel MOS transistor PT 74 . Here, for example, the size of the size-adjustable P-channel MOS transistor PT 74 can be adjusted by changing the number of MOS transistors in parallel. Then, the correction gain adjustment section 65 can adjust the correction gain by adjusting the size of the P-channel MOS transistor PT 74 .

[0313] The second bias portion 66 includes a switching element SW 73 , a capacitor element C 73 , and an N-channel MOS transistor NT 74 . The switching element SW 73 has a first terminal connected to the gate electrode of each of the N-channel MOS transistors NT 71 and NT 72 connected to the gate electrode of the N-channel MOS transistor NT 74 . The capacitor element C 73 is connected between the gate electrode of the N-channel MOS transistor NT 74 and the low-potential side power supply.

[0314] The additional gain switching circuit 70 includes five P-channel MOS transistors PT 75 to PT 79 and four switching elements SW 74 to SW 77 . The P-channel MOS transistors PT 75 have a diode connection configuration in which the gate electrode and the drain electrode are connected, and are directly connected to the N-channel MOS transistors NT 74 of the second bias portion 66 between the high-potential side power supply and the low-potential side power supply.

[0315] The switching element SW 74 is connected between the gate electrodes of the P-channel MOS transistors PT 75 and PT 76 . The switching element SW 75 is connected between the gate electrodes of the P-channel MOS crystals PT 76 and PT 77 . The switching element SW 76 is connected between the gate electrodes of the P-channel MOS transistors PT 77 and PT 78 . The switching element SW 77 is connected between the gate electrodes of the P-channel MOS transistors PT 78 and PT 79 .

[0316] As described above, the P-channel MOS transistors PT 75 and PT 76 to PT 79 form a current mirror circuit. The P-channel MOS transistor PT 75 is a transistor into which a current is injected, and the P-channel MOS transistors PT 79It is a transistor in the output stage mirror source.

[0317] Four switching elements SW 74 To SW 77 It is an additional gain switching switch, and is controlled by the analog gain control unit 53 (see reference). Figure 29 The switching control signal controls the on (closed) / off (open) state, and changes the number of parallel transistors of the injected current source and the number of parallel transistors of the output stage mirror source according to the analog gain.

[0318] In the power supply noise correction circuit 60 having the above-described circuit structure, noise is generated from the power supply terminal T. 71 via capacitor element C 71 The power supply noise of the input pixel power supply is converted into a current signal in the input sensing unit 62, and the current signal having a frequency characteristic adjusted by the frequency characteristic adjustment unit 64 flows into the additional gain switching circuit 70. This current is also added to the constant bias current used to operate the circuit. Then, in the additional gain switching circuit 70, the current obtained by subtracting the current flowing to the injected current source from the current flowing through the frequency characteristic adjustment unit 64 flows to the output stage mirror source.

[0319] Note that the circuit structures of the power supply noise correction circuit 60 and the additional gain switching circuit 70 shown here are merely examples, and the present invention is not limited to these circuit structures. For example, the number of transistors and switching elements in the additional gain switching circuit 70 is not limited to... Figure 30 The number of switching stages and the size of the additional gain are not limited to this.

[0320] The following section will describe a specific example of gain control for the additional gain switching circuit 70 of the power supply noise correction circuit 60.

[0321] (Example 1 of gain control)

[0322] Gain control example 1 is a control example with an additional gain of one. Figure 31 An operational illustration diagram for example 1 of gain control is shown.

[0323] When the additional gain is 1x, assume the number of parallel transistors in the injected current source is zero, and the number of parallel diodes in the output stage mirror source is 4. Specifically, assume that in the four switching elements SW 74 To SW 77 In the middle, the switching element SW 74 It is in the open state, and the other three switching elements SW 75 SW 76 and SW 77 It is connected.

[0324] (Example 2 of gain control)

[0325] Gain control example 2 is a control example when the additional gain is 4 / 3 times. Figure 32 An operation explanatory diagram of gain control example 2 is shown.

[0326] When the additional gain is 4 / 3 times, it is assumed that the number of parallel transistors of the injection current source is 1, and the number of parallel diodes of the mirror source of the output stage is 3. Specifically, it is assumed that among the four switching elements SW 74 to SW 77 , the switching element SW 75 is in an off state, and the remaining three switching elements SW 74 , SW 76 , and SW 77 are in an on state.

[0327] (Gain control example 3)

[0328] Gain control example 3 is a control example when the additional gain is two times. Figure 33 An operation explanatory diagram of gain control example 3 is shown.

[0329] When the additional gain is two times, it is assumed that the number of parallel transistors of the injection current source is 2, and the number of parallel diodes of the mirror source of the output stage is 2. Specifically, it is assumed that among the four switching elements SW 74 to SW 77 , the switching element SW 76 is in an off state, and the remaining three switching elements SW 74 , SW 75 , and SW 77 are in an on state.

[0330] (Gain control example 4)

[0331] Gain control example 4 is a control example when the additional gain is four times. Figure 34 An operation explanatory diagram of gain control example 4 is shown.

[0332] When the additional gain is four times, it is assumed that the number of parallel transistors of the injection current source is 3, and the number of parallel diodes of the mirror source of the output stage is 1. Specifically, it is assumed that among the four switching elements SW 74 to SW 77 , the switching element SW 77 is in an off state, and the remaining three switching elements SW 74 , SW 75 , and SW 76 are in an on state.

[0333] As mentioned above, for example, assuming the number of parallel transistors in the injected current source is 3 and the number of parallel transistors in the output stage mirror source is 1, an additional gain of four times is achieved. The reason is as follows.

[0334] First, by changing the number of parallel transistors in the injected current source and the number of parallel transistors in the output stage mirror source, the bias current flowing to the output stage mirror source becomes 1 / 4. On the other hand, all noise components of the pixel power supply, converted into a current signal, flow to the output stage mirror source, and therefore their magnitude remains unchanged. At this point, similar to the parallelism, the transconductance g of the output stage mirror source... m It is 1 / 4.

[0335] In the output stage mirror source, the flowing current is 1 / g m The ratio is converted to the gate voltage. Therefore, the gate voltage of the output stage mirror source remains unchanged as a bias component, but the power supply noise component on it becomes four times the original. This is then converted back into current by the output stage current source and output.

[0336] [Example 10]

[0337] Example 10 is a variation of Example 8 and is applicable to a MOS image sensor using a reference voltage in pixel 20. Figure 34 An example circuit structure of analog-to-digital converter 130 according to Example 10 is shown.

[0338] Example 8 is an example of suppressing pixel power supply noise. Besides pixel power supply noise, when a reference voltage is used in pixel 20, noise applied to the reference voltage may also occur via… Figure 35 Parasitic capacitance C in pixel 20 shown p And so on, riding on signal line 32. Even in this case, similar to the case of power supply noise, the noise on signal line 32 is visually identified as horizontal stripe noise in the image. A reference voltage is applied, for example, to the anode electrode of photodiode 21.

[0339] Therefore, in the analog-to-digital converter 130 according to Embodiment 10, the reference voltage of pixel 20 is monitored by the power supply noise correction circuit 60 to suppress noise caused by the reference voltage of pixel 20. Here, for convenience, the noise correction circuit that suppresses noise on the reference voltage is referred to as the power supply noise correction circuit 60. The construction, operation, etc. of the power supply noise correction circuit 60 and the additional gain switching circuit 70 included therein are the same as those in Embodiments 8 and 9, and overlap with them; therefore, their description will be omitted here.

[0340] Similarly, in the case of the analog-digital converter 130 according to Embodiment 10, the additional gain provided to the power supply noise correction circuit 60 is switched in coordination with the switching of the input capacitance of the comparator 131 in accordance with the same principle as the analog-digital converter 130 according to Embodiment 8. Therefore, it is possible to compensate for the amount of capacitance attenuation accompanying the switching of the input capacitance of the comparator 131, and thus, it is possible to suppress the noise on the reference voltage of the pixel 20 while absorbing the influence of the switching of the input capacitance of the comparator 131.

[0341] [Embodiment 11]

[0342] Embodiment 11 is an example in which the slope of the ramp wave of the reference signal V RAMP and the input capacitance of the comparator 131 are switched in the analog gain control of the analog-digital converter 130, and the reference signal setting signal (hereinafter, referred to as "DAC setting signal") and the switch setting signal are set.

[0343] Figure 35 is a block diagram schematically showing an outline of the system configuration of the CMOS image sensor according to Embodiment 11 having a function of setting the DAC setting signal and the switch setting signal at the time of analog gain control.

[0344] In the CMOS image sensor 1 according to Embodiment 11, the logic circuit section 14 acquires the illuminance using all or part of the pixel signals of the pixel array section 11, and generates illuminance data. The calculation unit for the generation of the illuminance data can be configured to obtain a statistical value, such as an average value, a median value, and a mode value, of predetermined pixel signals, or can be configured to perform an arbitrary linear / nonlinear calculation before and after the statistical value is obtained.

[0345] Note that, as a variation of the illuminance acquisition, a pixel dedicated for the measurement of the illuminance can be provided, or a pixel configured to be able to switch between imaging and the measurement of the illuminance can be provided.

[0346] As shown in Figure 12 , the CMOS image sensor 1 according to Embodiment 11 includes a control section 17 that sets the DAC setting signal and the switch setting signal at the time of analog gain control. The logic circuit section 14 generates illuminance data based on the data after the analog-digital conversion by the analog-digital converter 130, and supplies the illuminance data to the control section 17.

[0347] The control section 17 outputs the switch setting signal to control the on / off of the switch element for switching the input capacitance of the comparator 131, and outputs the DAC setting signal to control the slope of the ramp wave of the reference signal V RAMP based on at least one of the setting data written in the register 18 or the illuminance data input from the logic circuit section 14. For example, the switch element for switching the input capacitance corresponds to Figure 36The luminance data and the setting data can be associated with the switch setting signal by a calculation hardware, a calculation software, and a look-up table.

[0348] Note that the logic circuit section 14 and the control section 17 can be provided in the same pixel chip as the pixel array section 11, or a part of the logic circuit section 14 and the control section 17 can be provided outside the pixel chip.

[0349] Next, an example of a process of setting the DAC setting signal and the switch setting signal at the time of analog gain control in the CMOS image sensor 1 according to Embodiment 11 will be described with reference to a flowchart of Figure 36

[0350] Figure 37 The flowchart of Fig. 9 shows a read sequence of one imaging frame in the case of a rolling shutter.

[0351] First, a read row is set under the drive of the row selection section 12 (step Sll), and then exposure and pixel signal output are performed on the set read row (step S12). Next, the A / D conversion section 13 performs A / D conversion (analog-digital conversion) of the read row (step S13), and then outputs data after the A / D conversion (step S14).

[0352] Next, if the read row is not the last row (NO in step S15), the process returns to step Sll. If the read row is the last row, luminance data is generated in the logic circuit section 14 (step S16), and then the generated luminance data is output to the control section 17 (step S17).

[0353] Next, the control section 17 outputs a switch setting signal to control the on / off of the switch element for switching the input capacitance of the comparator 131 and a DAC setting signal to control the slope of the ramp wave of the reference signal V RAMP of Fig. 8 based on the setting data written in the register 18 and the luminance data input from the logic circuit section 14 (step S18).

[0354] The DAC setting signal and the switch setting signal at the time of analog gain control are set by the above-described one process, and then a normal imaging operation is performed. Thus, imaging can be performed using the optimum analog gain for each imaging frame.

[0355] As a variation of the generation of the luminance data, the exposure for imaging can also be used as the exposure for luminance acquisition, so that the luminance data is generated based on the generation of the image data. Further, the exposure sequence for imaging and the exposure sequence for luminance acquisition are not necessarily alternate. For example, the exposure sequence for luminance acquisition can be performed once in several frames.

[0356] <Modification Example>​

[0357] Although the technology according to the present application has been described above based on the preferred embodiments, the technology according to the present application is not limited to this embodiment. The configuration and structure of the imaging device described in the above-described embodiment are exemplary, and can be changed as appropriate.

[0358] For example, the circuit structure of the comparator 131 of each of the above-described examples is exemplary, and the present application is not limited to these circuit structures. Specifically, the comparator 131 according to Embodiment 1, the comparator 131 according to Embodiment 2, or the comparator 131 according to Embodiment 7 can employ a circuit structure in which at least one of the capacitance element C 12 , the input-side clamp transistor PT 13 , the input-side clamp transistor NT 11 , or the output-side clamp transistor NT 12 is omitted.

[0359] Further, according to the precision required by the product, a new element can be added to the comparator 131. Figure 37 is a circuit diagram showing a first modification example of the comparator. Figure 9 The example of ADJ shows that the capacitance C Figure 10 to Figure 34 is added to the comparator 131 according to the embodiment of the present application shown in Figure 37 . Note that the internal configuration of the first capacitor 51 and the second capacitor 52 can be designed as appropriate as described above, and can include the configuration example described in

[0360] The capacitance C ADJ is connected between the gate electrode and the source electrode of the input-side clamp transistor NT 11 . That is, the first terminal of the capacitance C ADJ is connected to the gate electrode of the input-side clamp transistor NT 11 , and the second terminal of the capacitance C ADJ is connected to the drain electrode of the input transistor. As shown in Figure 9 , by connecting the capacitance C ADJ , it is possible to suppress defects, such as noise, based on the voltage input to the gate electrode of the input-side clamp transistor NT 11 .

[0361] Further, the capacitance C ADJ may be variable, and it is possible to adjust the voltage input to the gate electrode of the input-side clamp transistor NT 11 to more effectively suppress defects based on the voltage by adjusting the capacitance of the capacitance C ADJ . Further, the analog gain of the analog-digital converter 130 set based on the control signal generated by the analog gain control section 53 can adjust the capacitance C ADJNote that there is no problem even if the capacitance of the capacitor C ADJ is set to zero because the configuration is the same as that of the example of Figure 37 .

[0362] Further, similarly to the input-side load current source I Figure 38 in 11 and the input-side load current source I 12 , a signal line (VSS wiring) configured to connect the terminals of each element to the low-potential side power supply can be shared by multiple elements. For example, the second capacitor 52 of each comparator 131 can be connected to the same VSS wiring.

[0363] Figure 38 is a circuit diagram showing a second modified example of a comparator. Figure 37 The example of Figure 37 differs in arrangement from the example of Figure 38 , and the capacitor C ADJ is connected between the gate electrode and the source electrode of the output-side clamp transistor NT 12 . The remaining portions are similar to those of the example of Figure 38 . Even in the example of Figure 5 , the voltage input to the gate electrode of the output-side clamp transistor NT ADJ can be adjusted by adjusting the capacitance of the capacitor C 12 . Thus, it is possible to suppress a defect based on the voltage.

[0364] Further, the comparator 131 can include not only the input-side clamp transistor NT 11 and the output-side clamp transistor NT 12 but also three or more clamp transistors. In this case, the capacitor C ADJ may be provided for one or more of the three or more clamp transistors.

[0365] Note that the present embodiment reduces the noise of the input to the gate electrode of the input transistor PT11 of the buffer 50 by using the capacitor attenuation of the voltage division by the capacitance between the first capacitor 51 and the second capacitor 52, but the addition of the capacitor C ADJ to the configuration of the conventional configuration example shown in Figure 39 and the like is also effective in adjusting the voltage input to the gate electrode of the clamp transistor. Figure 40 A configuration example in which the capacitor C ADJ is added to the conventional configuration example is shown.

[0366] <APPLICATION EXAMPLE>

[0367] As shown in Figure 41As shown, the imaging apparatus according to the above-described embodiment can be used for various devices that sense light such as visible light, infrared rays, ultraviolet rays, and X-rays. Specific examples of the various devices are listed below.

[0368] An apparatus that captures an image for appreciation, such as a digital camera or a portable device with a camera function;

[0369] An apparatus for transportation, such as a car-mounted sensor that captures an image of the front, rear, surroundings, interior, or the like of a car, a monitoring camera that monitors a traveling vehicle and a road, or a distance measuring sensor that measures an inter-vehicle distance, for safe driving such as automatic parking, recognition of the state of a driver, or the like;

[0370] An apparatus for a home appliance such as a television, a refrigerator, and an air conditioner, that captures an image of a user's gesture and operates the appliance according to the gesture;

[0371] An apparatus for medical and health care, such as an endoscope or an apparatus that performs angiography by receiving infrared light;

[0372] An apparatus for security, such as a monitoring camera for preventing crime or a camera for personal authentication applications;

[0373] An apparatus for beauty care, such as a skin measuring instrument that captures an image of skin or a microscope that captures an image of a scalp;

[0374] An apparatus for sports, such as a sports camera or a wearable camera for sports applications or the like;

[0375] An apparatus for agriculture, such as a camera for monitoring a field and a crop condition;

[0376] <Examples of Application According to the Technology of the Invention>

[0377] The technology according to the present invention can be applied to various products. Hereinafter, more specific examples of application will be described.

[0378] [Electronic Apparatus of the Invention]

[0379] Here, a case where the present invention is applied to an imaging system such as a digital camera or a video camera, a mobile terminal apparatus with an imaging function such as a cell phone, and an electronic apparatus such as a copier that uses an imaging apparatus as an image reader will be described.

[0380] (Example of Imaging System)

[0381] Figure 41 is a block diagram showing a configuration example of an imaging system that is an example of an electronic apparatus of the present invention.

[0382] As Figure 42As shown, the imaging system 100 according to the present example includes an imaging optical system 101 including a lens group and the like, an imaging section 102, a digital signal processor (DSP) circuit 103, a frame memory 104, a display device 105, a recording device 106, an operation system 107, a power supply system 108, and the like. Then, the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are configured to be connected to each other via a bus 109.

[0383] The imaging optical system 101 captures incident light (image light) from a subject and forms an image on an imaging surface of the imaging section 102. The imaging section 102 converts an amount of incident light forming an image on the imaging surface by the optical system 101 into an electric signal in units of pixels and outputs the electric signal as a pixel signal. The DSP circuit 103 performs general camera signal processing such as white balance processing, demosaicing processing, gamma correction processing, and the like.

[0384] The frame memory 104 is appropriately used to store data in the signal processing process of the DSP circuit 103. The display device 105 includes a panel display device such as a liquid crystal display device or an organic electroluminescence (EL) display device and displays a moving image or a still image imaged by the imaging section 102. The recording device 106 records a moving image or a still image imaged by the imaging section 102 on a recording medium such as a portable semiconductor memory, an optical disk, or a hard disk drive (HDD).

[0385] The operation system 107 issues operation commands for various functions of the imaging system 100 under user operation. The power supply system 108 appropriately supplies various power sources of operation power as power supply targets of the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107.

[0386] In the imaging system 100 having the above-described configuration, the imaging device according to the above-described embodiment can be used as the imaging section 102. According to the imaging device, it is possible to reduce the power consumption of the analog-digital converter, and thus it is possible to reduce the power consumption of the imaging device. Further, even in the single-slope analog-digital converter, in the case where a buffer is provided in front of the capacitive element for absorbing offset so as to increase the driving force of the reference signal of the ramp wave and reduce the output impedance, it is possible to reduce the noise of the buffer without connecting the output terminal of the buffer between the pixel columns, and thus it is possible to obtain an imaged image having high image quality.

[0387] <Mobile body application example>

[0388] The technology according to the present invention (the technology) can be applied to a variety of products. For example, the technology according to the present invention can be implemented as an imaging device installed on any type of mobile body such as automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobile devices, airplanes, drones, ships, robots, construction machinery, and agricultural machinery (tractors).

[0389] Figure 42 This is a block diagram illustrating a schematic configuration example of a vehicle control system that is an example of a mobile body control system capable of applying the technology according to the present invention.

[0390] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 42 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, an audio / visual output unit 12052, and an in-vehicle network interface (I / F) 12053, which are functional configurations of the integrated control unit 12050, are shown.

[0391] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various types of programs. For example, the drive system control unit 12010 is used as a control device for devices such as internal combustion engines, drive motors and other drive force generating devices for generating vehicle driving force, drive force transmission mechanisms for transmitting driving force to the wheels, steering mechanisms for adjusting the vehicle's steering angle, and braking devices for generating vehicle braking force.

[0392] The vehicle body system control unit 12020 controls the operation of various types of devices installed on the vehicle body according to various types of programs. For example, the vehicle body system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, reversing lights, brake lights, turn signals, and fog lights. In this case, radio waves or signals from various types of switches sent from a keyless entry device can be input to the vehicle body system control unit 12020. The vehicle body system control unit 12020 receives these radio waves or signal inputs and controls the vehicle's door locks, power windows, lights, etc.

[0393] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle that includes the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected with an imaging section 12031. The vehicle exterior information detection unit 12030 causes the imaging section 12031 to image an image of the outside of the vehicle, and receives the imaged image. Based on the received image, the vehicle exterior information detection unit 12030 can execute processing of detecting an object such as a person, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance to the above-described object.

[0394] The imaging section 12031 is an optical sensor that receives light and outputs an electric signal corresponding to the amount of light received. The imaging section 12031 can output the electric signal as an image, or can output the electric signal as information about a measured distance. Furthermore, the light received by the imaging section 12031 can be visible light, or can be invisible light such as infrared rays.

[0395] The vehicle interior information detection unit 12040 detects information about the interior of the vehicle. The vehicle interior information detection unit 12040 is connected with, for example, a driver state detection section 12041 that detects a state of a driver. The driver state detection section 12041 includes, for example, a camera that photographs the driver, and based on detection information input from the driver state detection section 12041, the vehicle interior information detection unit 12040 can calculate a degree of fatigue of the driver or a degree of concentration of the driver, or can determine whether the driver is dozing off.

[0396] The microcomputer 12051 can calculate a control target value of a driving force generation device, a steering mechanism, or a braking device based on information about the interior and the exterior of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can execute cooperative control aimed at realizing functions of an advanced driver assistance system (ADAS) including collision avoidance or impact mitigation for the vehicle, following driving based on a following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, and the like.

[0397] Furthermore, by controlling the driving force generation device, the steering mechanism, the braking device, and the like based on information about the surroundings of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can execute cooperative control aimed at realizing automatic driving and the like that enables the vehicle to travel autonomously without relying on the operation of the driver.

[0398] Further, based on information about the outside of the vehicle acquired by the outside information detecting unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can perform cooperative control intended to prevent glare by controlling the headlamp to change from high beam to low beam in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside information detecting unit 12030.

[0399] The sound image output section 12052 transmits an output signal of at least one of sound or an image to an output device capable of visually or aurally notifying a passenger of the vehicle or information outside the vehicle. In Figure 43 examples, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 can include at least one of a vehicle-mounted display or a head-up display, for example.

[0400] Figure 43 is a schematic view that illustrates an example of a mounting position of the imaging section 12031.

[0401] In Figure 43 , the vehicle 12100 includes an imaging section 12101, an imaging section 12102, an imaging section 12103, an imaging section 12104, and an imaging section 12105 as the imaging section 12031.

[0402] The imaging section 12101, the imaging section 12102, the imaging section 12103, the imaging section 12104, and the imaging section 12105 are provided at positions on the front nose, the side mirror, the rear bumper, and the rear door of the vehicle 12100 and a position on the upper portion of the windshield in the vehicle, for example. The imaging section 12101 provided on the front nose and the imaging section 12105 provided on the upper portion of the windshield in the vehicle mainly acquire images of the front of the vehicle 12100. The imaging section 12102 and the imaging section 12103 provided on the side mirror mainly acquire images of both sides of the vehicle 12100. The imaging section 12104 provided on the rear bumper or the rear door mainly acquires an image of the rear of the vehicle 12100. The images of the front acquired by the imaging section 12101 and the imaging section 12105 are mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, and the like.

[0403] Note that ​Exemplary imaging ranges of the imaging sections 12101 to 12104 are shown. The imaging range 12111 represents an imaging range of the imaging section 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively represent imaging ranges of the imaging section 12102 and the imaging section 12103 provided at the side mirrors. The imaging range 12114 represents an imaging range of the imaging section 12104 provided on the rear bumper or the rear cover. A bird's-eye image of the vehicle 12100 viewed from above can be obtained, for example, by superimposing image data imaged by the imaging sections 12101 to 12104.

[0404] At least one of the imaging sections 12101 to 12104 can have a function of acquiring distance information. For example, at least one of the imaging sections 12101 to 12104 can be a stereo camera composed of a plurality of imaging elements, or can be an imaging element having pixels for phase difference detection.

[0405] For example, based on the distance information acquired from the imaging sections 12101 to 12104, the microcomputer 12051 can determine the distance of each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change of the distance (relative speed with respect to the vehicle 12100), and thereby extract, as a preceding vehicle, the closest three-dimensional object that is particularly on a travel path of the vehicle 12100 and that travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or greater than 0 km / h). Further, the microcomputer 12051 can set a following distance to be maintained with the preceding vehicle in advance, and perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. Thus, cooperative control aimed at automatic driving and the like of the vehicle not depending on the operation of the driver can be performed.

[0406] For example, based on distance information acquired from the imaging sections 12101 to 12104, the microcomputer 12501 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of obstacles. For example, the microcomputer 12051 classifies obstacles around the vehicle 12100 into obstacles that the driver of the vehicle 12100 can visually recognize and obstacles that the driver of the vehicle 12100 cannot visually recognize. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a case where the collision risk is equal to or higher than a set value and thus there is a possibility of collision, the microcomputer 12051 issues a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or evasive steering by the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collision.

[0407] At least one of the imaging sections 12101 to 12104 can be an infrared camera that detects infrared rays. The microcomputer 12051 can recognize a pedestrian, for example, by determining whether a pedestrian is present in the captured images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is performed, for example, by a step of extracting feature points in the captured images of the imaging sections 12101 to 12104 as infrared cameras and a step of performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. If the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging sections 12101 to 12104 and thus recognizes the pedestrian, the sound image output section 12052 controls the display section 12062 so that a square outline for emphasis is displayed superimposed on the recognized pedestrian. In addition, the sound image output section 12052 can also control the display section 12062 so as to display an icon or the like representing a pedestrian at a desired position.

[0408] An example of a vehicle control system to which the technology according to the present application can be applied has been described above. For example, the technology according to the present application can be applied to the imaging section 12031 and the like in the above-described configuration. In addition, by applying the technology according to the present application to the imaging section 12031 and the like, low power consumption of the analog-digital converter can be achieved, and ultimately low power consumption of the imaging device, and thus low power consumption of the vehicle control system can be facilitated. Furthermore, even in the single-slope analog-digital converter, in the case where a buffer is provided in front of the capacitive element for absorbing offset to increase the driving force of the reference signal of the ramp wave and reduce the output impedance, the noise of the buffer can be reduced without connecting the output terminal of the buffer between the pixel columns, and thus an imaging image with high image quality can be obtained.

[0409] <Configuration that the present application can adopt>

[0410] Note that the present technology can also have the following configuration.

[0411] <<A. Imaging device>>

[0412] [A-01] An imaging device comprising:

[0413] a load current source;

[0414] a comparator including an input transistor connected between a signal line that transmits a signal read from a pixel and the load current source;

[0415] a first capacitor that inputs a predetermined reference signal to a gate electrode of the input transistor; and

[0416] a second capacitor connected between the gate electrode of the input transistor and a reference potential node.

[0417] [A-02] The imaging device according to the above-described [A-01], wherein

[0418] the first capacitor and the second capacitor attenuate the predetermined reference signal input to the gate electrode of the input transistor by capacitive voltage division.

[0419] [A-03] The imaging device according to the above-described [A-02], wherein

[0420] each of the first capacitor and the second capacitor includes a variable capacitive element having a variable capacitance value.

[0421] [A-04] The imaging device according to the above-described [A-03], wherein

[0422] The capacitance value of each of the first and second capacitors can vary depending on an analog gain of an analog-to-digital converter including the comparator.

[0423] [A-05] The imaging device according to the above-described [A-02], wherein

[0424] The first and second capacitors include a plurality of capacitive elements each having a first terminal connected to the gate electrode of the input transistor, and a plurality of switching elements each connected between second terminals of the plurality of capacitive elements.

[0425] [A-06] The imaging device according to the above-described [A-05], wherein

[0426] The switching element is further provided between a reference potential node and a second terminal of a capacitive element of the plurality of capacitive elements located on the reference potential node side.

[0427] [A-07] The imaging device according to any one of the above-described [A-01] to [A-06], wherein

[0428] The predetermined reference signal is a voltage of a ramp waveform that linearly varies with a predetermined slope.

[0429] [A-08] The imaging device according to the above-described [A-07], wherein

[0430] The comparator compares the voltage of the signal line with the voltage of the ramp waveform.

[0431] [A-09] The imaging device according to the above-described [A-08], wherein

[0432] An amplitude of the voltage of the ramp waveform is attenuated by using a capacitive division of the first and second capacitors.

[0433] [A-10] The imaging device according to the above-described [A-09], further comprising:

[0434] a reference signal generation section that generates the voltage of the ramp waveform, wherein

[0435] The reference signal generation section sets an amplitude of the voltage of the ramp waveform to be large in advance so that the amplitude after the capacitive division becomes a desired amplitude.

[0436] [A-11] The imaging device according to any one of the above-described [A-07] to [A-10], further comprising:

[0437] an analog gain control section that controls an analog gain of an analog-digital converter by adjusting an amplitude of the voltage of the ramp waveform.

[0438] [A-12] The imaging device according to the above-mentioned [A-11], wherein

[0439] The analog gain control section controls the amplitude of the voltage of the ramp waveform and capacitance values of the first capacitor and the second capacitor.

[0440] [A-13] The imaging device according to any one of the above-mentioned [A-01] to [A-12], wherein

[0441] The load current source includes an input-side load current source and an output-side load current source,

[0442] The input transistor is connected between the signal line and the input-side load current source, and

[0443] The comparator includes an output transistor connected between the signal line and the output-side load current source and using an output of the input transistor as a gate input.

[0444] [A-14] The imaging device according to the above-mentioned [A-13], wherein

[0445] The comparator includes an input-side cascode transistor connected between the input transistor and the input-side load current source, and an output-side cascode transistor connected between the output transistor and the output-side load current source.

[0446] [A-15] The imaging device according to any one of the above-mentioned [A-01] to [A-14], further comprising:

[0447] a noise correction circuit that superimposes a correction voltage corresponding to noise of a pixel power supply on a reference signal generated by a reference signal generation section, wherein

[0448] The noise correction circuit switches a gain for generating the correction voltage in accordance with switching of the capacitance values of each of the first capacitor and the second capacitor.

[0449] [A-16] The imaging device according to the above-mentioned [A-15], wherein

[0450] The noise correction circuit superimposes a noise correction voltage riding on a reference voltage used in the pixel on the reference signal generated by the reference signal generation section.

[0451] [A-17] The imaging device according to any one of the above [A-04] to [A-16], further comprising:

[0452] a control section that sets a reference signal setting signal for generating the reference signal by the reference signal generating section and a switch setting signal for switching the plurality of switching elements when controlling the analog gain of the analog-digital converter.

[0453] [A-18] The imaging device according to the above [A-17], further comprising:

[0454] a logic circuit section that generates illuminance data based on data that is analog-digital converted by the analog-digital converter.

[0455] [A-19] The imaging device according to the above [A-18], wherein,

[0456] the control section sets the reference signal setting signal and the switch setting signal based on the illuminance data generated by the logic circuit section.

[0457] [A-20] The imaging device according to any one of the above [A-01] to [A-19], wherein,

[0458] the comparator further comprises:

[0459] an output transistor whose source electrode is connected to the source electrode of the input transistor and whose gate electrode is connected to the drain electrode of the input transistor;

[0460] a clamp transistor whose drain electrode is connected to the source electrode of the input transistor and whose source electrode is connected to the drain electrode of the input transistor; and

[0461] a third capacitor whose first end is connected to the gate electrode of the clamp transistor and whose second end is connected to the drain electrode of the input transistor.

[0462] [A-21] The imaging device according to any one of the above [A-01] to [A-20], wherein,

[0463] the comparator further comprises:

[0464] an output transistor whose source electrode is connected to the source electrode of the input transistor and whose gate electrode is connected to the drain electrode of the input transistor;

[0465] a clamp transistor whose drain electrode is connected to the source electrode of the input transistor and whose source electrode is connected to the drain electrode of the output transistor; and

[0466] a third capacitor having a first end connected to the gate electrode of the clamp transistor and a second end connected to the drain electrode of the output transistor.

[0467] [A-22] The imaging device according to any one of the above [A-20] to [A-21], wherein

[0468] a capacitance value of the third capacitor is varied depending on an analog gain of an analog-to-digital converter including the comparator.

[0469] <<B. Electronic device>>

[0470] [B-01] An electronic device including an imaging device, the imaging device comprising:

[0471] a load current source;

[0472] a comparator including an input transistor connected between a signal line transmitting a signal read from a pixel and the load current source;

[0473] a first capacitor inputting a predetermined reference signal to a gate electrode of the input transistor; and

[0474] a second capacitor connected between the gate electrode of the input transistor and a reference potential node.

[0475] [B-02] The electronic device according to the above [B-01], wherein

[0476] the first capacitor and the second capacitor attenuate the predetermined reference signal input to the gate electrode of the input transistor by capacitive voltage division.

[0477] [B-03] The electronic device according to the above [B-02], wherein

[0478] each of the first capacitor and the second capacitor includes a variable capacitance element having a variable capacitance value.

[0479] [B-04] The electronic device according to the above [B-03], wherein

[0480] the capacitance value of each of the first capacitor and the second capacitor is variable depending on an analog gain of an analog-to-digital converter including the comparator.

[0481] [B-05] The electronic device according to the above [B-02], wherein

[0482] The first capacitor and the second capacitor include a plurality of capacitor elements each having a first end connected to the gate electrode of the input transistor, and a plurality of switching elements each connected between second ends of the plurality of capacitor elements.

[0483] [B-06] The electronic device according to the above [B-05], wherein

[0484] The switching element is further provided between a reference potential node and a second end of a capacitor element of the plurality of capacitor elements located on the reference potential node side.

[0485] [B-07] The electronic device according to any one of the above [B-01] to [B-06], wherein

[0486] The predetermined reference signal is a voltage of a ramp waveform that linearly changes with a predetermined slope.

[0487] [B-08] The electronic device according to the above [B-07], wherein

[0488] The comparator compares a voltage of the signal line with a voltage of the ramp waveform.

[0489] [B-09] The electronic device according to the above [B-08], wherein

[0490] An amplitude of the voltage of the ramp waveform is attenuated by using a capacitance division of the first capacitor and the second capacitor.

[0491] [B-10] The electronic device according to the above [B-09], further comprising:

[0492] a reference signal generation section that generates the voltage of the ramp waveform, wherein

[0493] The reference signal generation section sets an amplitude of the voltage of the ramp waveform to be large in advance so that the amplitude after being attenuated by the capacitance division becomes a desired amplitude.

[0494] [B-11] The electronic device according to any one of the above [B-07] to [B-10], further comprising:

[0495] an analog gain control section that controls an analog gain of an analog-digital converter by adjusting the amplitude of the voltage of the ramp waveform.

[0496] [B-12] The electronic device according to the above [B-11], wherein

[0497] The analog gain control section controls the amplitude of the voltage of the ramp waveform and the capacitance values of the first capacitor and the second capacitor.

[0498] [B-13] The electronic device according to any one of [B-01] to [B-12] above, wherein

[0499] The load current source includes an input-side load current source and an output-side load current source,

[0500] The input transistor is connected between the signal line and the input-side load current source, and

[0501] The comparator includes an output transistor connected between the signal line and the output-side load current source and using the output of the input transistor as a gate input.

[0502] [B-14] The electronic device according to [B-13] above, wherein

[0503] The comparator includes an input-side cascode transistor connected between the input transistor and the input-side load current source, and an output-side cascode transistor connected between the output transistor and the output-side load current source.

[0504] [B-15] The electronic device according to any one of [B-01] to [B-14] above, further comprising:

[0505] a noise correction circuit that superimposes a correction voltage corresponding to noise of a pixel power supply on a reference signal generated by a reference signal generation section, wherein

[0506] The noise correction circuit switches a gain for generating the correction voltage in accordance with switching of the capacitance values of each of the first capacitor and the second capacitor.

[0507] [B-16] The electronic device according to [B-15] above, wherein

[0508] The noise correction circuit superimposes a noise correction voltage riding on a reference voltage used in the pixel on the reference signal generated by the reference signal generation section.

[0509] [B-17] The electronic device according to any one of [B-04] to [B-16] above, further comprising:

[0510] a control section that sets a reference signal set signal for generating the reference signal by the reference signal generation section and a switch set signal for switching the plurality of switching elements when controlling the analog gain of the analog-digital converter.

[0511] The electronic device according to the above [B-17], further comprising:

[0512] a logic circuit section that generates illuminance data based on data that is analog-digital converted by the analog-digital converter.

[0513] The electronic device according to the above [B-18], wherein

[0514] The control section sets the reference signal setting signal and the switch setting signal based on the illuminance data generated by the logic circuit section.

[0515] The electronic device according to any one of the above [B-01] to [B-19], wherein

[0516] The comparator further includes:

[0517] an output transistor whose source electrode is connected to the source electrode of the input transistor and whose gate electrode is connected to the drain electrode of the input transistor;

[0518] a clamp transistor whose drain electrode is connected to the source electrode of the input transistor and whose source electrode is connected to the drain electrode of the input transistor; and

[0519] a third capacitor whose first end is connected to the gate electrode of the clamp transistor and whose second end is connected to the drain electrode of the input transistor.

[0520] The electronic device according to any one of the above [B-01] to [B-20], wherein

[0521] The comparator further includes:

[0522] an output transistor whose source electrode is connected to the source electrode of the input transistor and whose gate electrode is connected to the drain electrode of the input transistor;

[0523] a clamp transistor whose drain electrode is connected to the source electrode of the input transistor and whose source electrode is connected to the drain electrode of the output transistor; and

[0524] a third capacitor whose first end is connected to the gate electrode of the clamp transistor and whose second end is connected to the drain electrode of the output transistor.

[0525] The electronic device according to the above [B-20] or [B-21], wherein

[0526] A capacitance value of the third capacitor varies according to an analog gain of an analog-digital converter including the comparator.

[0527] List of reference numerals

[0528] 1 CMOS image sensor

[0529] 11 Pixel array section

[0530] 12 Row selection section

[0531] 13 Analog-digital conversion section

[0532] 14 Logic circuit section (signal processing section)

[0533] 15 Timing control section

[0534] 16 Reference signal generation section

[0535] 20 Pixel

[0536] 21 Photodiode

[0537] 22 Transfer transistor

[0538] 23 Reset transistor

[0539] 24 Amplification transistor

[0540] 25 Selection transistor

[0541] 31 (311 to 31 m ) Pixel control line

[0542] 32 (321 to 32 n ) Signal line

[0543] 50 Buffer

[0544] 51 First capacitor

[0545] 52 Second capacitor

[0546] 53 Analog gain control section

[0547] 60 Power supply noise correction circuit

[0548] 70 Additional gain switching circuit

[0549] 130 Analog-digital converter

[0550] 131 Comparator

[0551] 132 Counter

[0552] C 11 , C 12 , C13 , C ADJ Capacitive element

[0553] I 11 Input-side load current source

[0554] I 12 Output-side load current source

[0555] PT 11 Input transistor

[0556] PT 12 Output transistor

[0557] V ss Low potential

Claims

1. An imaging device, comprising: Load current source; A comparator includes an input transistor connected between a signal line transmitting a signal read from a pixel and the load current source; A first capacitor inputs a predetermined reference signal to the gate electrode of the input transistor; as well as A second capacitor is connected between the gate electrode of the input transistor and the reference potential node.

2. The imaging device according to claim 1, wherein, The first capacitor and the second capacitor attenuate the predetermined reference signal input to the gate electrode of the input transistor by capacitive voltage division.

3. The imaging device according to claim 2, wherein, Each of the first capacitor and the second capacitor includes a variable capacitor element having a variable capacitance value.

4. The imaging device according to claim 3, wherein, The capacitance values ​​of the first capacitor and the second capacitor can vary depending on the analog gain of the analog-to-digital converter including the comparator.

5. The imaging device according to claim 2, wherein, The first capacitor and the second capacitor include a plurality of capacitive elements and a plurality of switching elements. The plurality of capacitive elements each have a first end connected to the gate electrode of the input transistor, and the plurality of switching elements are respectively connected between the second ends of the plurality of capacitive elements.

6. The imaging apparatus according to claim 5, wherein, The switching element is also disposed between the reference potential node and the second end of the capacitor element located on the reference potential node side among the plurality of capacitor elements.

7. The imaging apparatus according to any one of claims 1 to 6, wherein, The predetermined reference signal is a voltage of a ramp waveform that varies linearly with a predetermined slope.

8. The imaging apparatus according to claim 7, wherein, The comparator compares the voltage of the signal line with the voltage of the ramp waveform.

9. The imaging apparatus according to claim 8, wherein, The amplitude of the voltage of the ramp waveform is attenuated by using the capacitive voltage divider of the first capacitor and the second capacitor.

10. The imaging apparatus according to claim 9, further comprising: A reference signal generation unit generates the voltage of the ramp waveform, wherein... The reference signal generation unit pre-sets the voltage amplitude of the ramp waveform to be large, so that the amplitude after being attenuated by the capacitor voltage divider becomes the desired amplitude.

11. The imaging apparatus according to claim 7, further comprising: The analog gain control unit controls the analog gain of the analog-to-digital converter by adjusting the amplitude of the voltage of the ramp waveform.

12. The imaging apparatus according to claim 11, wherein, The analog gain control unit controls the amplitude of the voltage of the ramp waveform and the capacitance values ​​of the first capacitor and the second capacitor.

13. The imaging apparatus according to any one of claims 1 to 6, wherein, The load current source includes an input-side load current source and an output-side load current source. The input transistor is connected between the signal line and the input-side load current source, and The comparator includes an output transistor connected between the signal line and the output-side load current source and uses the output of the input transistor as the gate input.

14. The imaging apparatus according to claim 13, wherein, The comparator includes: an input-side cascode transistor connected between the input transistor and the input-side load current source; and an output-side cascode transistor connected between the output transistor and the output-side load current source.

15. The imaging apparatus according to any one of claims 1 to 6, wherein, The comparator further includes: An output transistor, the source electrode of which is connected to the source electrode of the input transistor, and the gate electrode of which is connected to the drain electrode of the input transistor; A clamping transistor, wherein its drain electrode is connected to the source electrode of the input transistor, and its source electrode is connected to the drain electrode of the input transistor; and A third capacitor has its first end connected to the gate electrode of the clamping transistor and its second end connected to the drain electrode of the input transistor.

16. The imaging apparatus according to any one of claims 1 to 6, wherein, The comparator further includes: An output transistor, the source electrode of which is connected to the source electrode of the input transistor, and the gate electrode of which is connected to the drain electrode of the input transistor; A clamping transistor, the drain of which is connected to the source of the input transistor, and the source of which is connected to the drain of the output transistor; and A third capacitor has its first end connected to the gate electrode of the clamping transistor and its second end connected to the drain electrode of the output transistor.

17. The imaging apparatus according to claim 15, wherein, The capacitance value of the third capacitor varies according to the analog gain of the analog-to-digital converter, which includes the comparator.

18. The imaging apparatus according to any one of claims 1 to 6, further comprising: The noise correction circuit superimposes a correction voltage corresponding to the noise of the pixel power supply onto the reference signal generated by the reference signal generation unit, wherein... The noise correction circuit switches the gain used to generate the correction voltage based on the switching of the capacitance values ​​of the first capacitor and the second capacitor.

19. The imaging apparatus according to claim 18, wherein, The noise correction circuit superimposes a noise correction voltage, which is based on the reference voltage used in the pixel, onto the reference signal generated by the reference signal generation unit.

20. The imaging apparatus according to claim 4, further comprising: The control unit sets a reference signal setting signal for generating a reference signal by the reference signal generation unit and a switch setting signal for switching multiple switching elements when the analog gain of the analog-to-digital converter is controlled.

21. The imaging apparatus according to claim 20, further comprising: The logic circuit section generates illuminance data based on the data converted from analog to digital by the analog-to-digital converter.

22. The imaging apparatus according to claim 21, wherein, The control unit sets the reference signal setting signal and the switch setting signal based on the illuminance data generated by the logic circuit unit.

23. An electronic device including an imaging apparatus, said imaging apparatus being the imaging apparatus as claimed in any one of claims 1 to 22.

Images