External device management method and apparatus, device, and storage medium

Abstract

The application provides an external device management method and device, equipment and storage medium, relates to the field of device management, and comprises the following steps: determining the topology mode of a PCIe switch, so as to determine the level state of a general input and output GPIO according to the topology mode of the PCIe switch; in the case where the level state is a high level, binding the serial number of an external device connected to the downlink port of the PCIe switch according to the mapping relationship between the downlink port number of the PCIe switch and the serial number of the external device in a first mapping table; and in the case where the level state is a low level, binding the serial number of an external device connected to the downlink port of the PCIe switch according to the mapping relationship between the downlink port number of the PCIe switch and the serial number of the external device in a second mapping table. The application can flexibly call the mapping table, realize dynamic alignment of the serial number of the external device, and does not need human intervention or replacement of a hardware board.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of device management, and in particular to an external device management method and device, apparatus and storage medium. BACKGROUND

[0002] The bandwidth of a bus exchange chip (Peripheral Component Interconnect express Switch, PCIe Switch) of a high-speed serial computer expansion bus standard needs to be changed according to different requirements, but the mapping relationship of the PCIe Switch uplink and downlink ports will change under different PCIe Switch uplink bandwidth modes, thereby causing confusion in the corresponding relationship between the external device and the physical slot number (Physical Slot Number, PSN) in device asset management, and failing to ensure that the serial number of the external device in the device asset management is consistent with the serial number of the external device under the operating system application. SUMMARY

[0003] The present application provides an external device management method, device, apparatus and storage medium, to solve the technical problems in the prior art that in order to ensure that the serial number of the external device in the device asset management is consistent with the serial number of the external device under the operating system application, artificial intervention or replacement of the hardware board card is required, thereby causing an increase in cost and an error-prone assembly.

[0004] In a first aspect, the present application provides an external device management method, comprising:

[0005] obtaining the level state of a general purpose input output (GPIO);

[0006] in the case where the level state is a high level, binding the serial number of the external device connected to the downlink port of each PCIe Switch according to the mapping relationship between the downlink port number of each PCIe Switch and the serial number of the external device in a first mapping table;

[0007] in the case where the level state is a low level, binding the serial number of the external device connected to the downlink port of each PCIe Switch according to the mapping relationship between the downlink port number of each PCIe Switch and the serial number of the external device in a second mapping table;

[0008] The topology mode of the PCIe Switch includes a double uplink mode and a single uplink mode.

[0009] The level state of the general input and output GPIO is determined by the bus switching chip PCIe Switch according to a topology mode of the bus switching chip PCIe Switch.

[0010] According to the external device management method provided by the application, the PCIe Switch includes a first PCIe Switch, a second PCIe Switch, a third PCIe Switch and a fourth PCIe Switch.

[0011] The serial number of the external device includes at least a first serial number, a second serial number, a third serial number, a fourth serial number, a fifth serial number, a sixth serial number and a seventh serial number.

[0012] In the first mapping table, the second downstream port of the second PCIe Switch corresponds to the third serial number, the first downstream port of the second PCIe Switch corresponds to the fourth serial number, the second downstream port of the third PCIe Switch corresponds to the fifth serial number, and the first downstream port of the third PCIe Switch corresponds to the sixth serial number.

[0013] In the second mapping table, the second downstream port of the second PCIe Switch corresponds to the fourth serial number, the first downstream port of the second PCIe Switch corresponds to the third serial number, the second downstream port of the third PCIe Switch corresponds to the sixth serial number, and the first downstream port of the third PCIe Switch corresponds to the fifth serial number.

[0014] According to the external device management method provided by the application, the level state of the general input and output GPIO is obtained, including:

[0015] The bus switching chip PCIe Switch detects the connection state of the upstream port in all bus switching chips PCIe Switch, and in the case that both upstream ports of the PCIe Switch have a connection relationship with the central processing unit CPU, the topology mode of the PCIe Switch is determined as a double-upstream mode; in the case that one port of the two upstream ports of the PCIe Switch is connected with the central processing unit CPU, the topology mode of the PCIe Switch is determined as a single-upstream mode.

[0016] In the double-upstream mode, the level state of the general input and output GPIO is determined as a high level.

[0017] In the single-upstream mode, the level state of the general input and output GPIO is determined as a low level.

[0018] The external device management method provided by the application comprises the following steps:

[0019] The step of constructing the connection relationship between each port in each PCIe Switch and the CPU and the step of constructing the connection relationship between each port in each PCIe Switch and the external device specifically comprise the following steps:

[0020] In the first PCIe Switch, the connection relationship between the first uplink port and the first downlink port in the first CPU is constructed, the connection relationship between the second uplink port and the second downlink port in the first CPU is constructed, the connection relationship between the first downlink port and the external device with the first serial number is constructed, and the connection relationship between the second downlink port and the external device with the second serial number is constructed.

[0021] In the second PCIe Switch, the connection relationship between the second uplink port and the third downlink port in the first CPU is constructed, the connection relationship between the first uplink port and the fourth downlink port in the first CPU is constructed, the connection relationship between the second downlink port and the external device with the third serial number is constructed, and the connection relationship between the first downlink port and the external device with the fourth serial number is constructed.

[0022] In the third PCIe Switch, the connection relationship between the first uplink port and the first downlink port in the second CPU is constructed, the connection relationship between the second uplink port and the second downlink port in the second CPU is constructed, the connection relationship between the second downlink port and the external device with the fifth serial number is constructed, and the connection relationship between the first downlink port and the external device with the sixth serial number is constructed.

[0023] In the fourth PCIe Switch, the connection relationship between the second uplink port and the third downlink port in the second CPU is constructed, the connection relationship between the first uplink port and the fourth downlink port in the second CPU is constructed, the connection relationship between the first downlink port and the external device with the seventh serial number is constructed, and the connection relationship between the second downlink port and the external device with the eighth serial number is constructed.

[0024] The first CPU is connected to the second CPU through the UPI.

[0025] The external device management method provided by the application further comprises the following steps after the first mapping table in the double uplink mode is generated:

[0026] interrupting the connection relationship between the second uplink port and the second downlink port in the first CPU in the first PCIe Switch, interrupting the connection relationship between the first uplink port and the fourth downlink port in the first CPU in the second PCIe Switch, interrupting the connection relationship between the second uplink port and the second downlink port in the second CPU in the third PCIe Switch, and interrupting the connection relationship between the first uplink port and the fourth downlink port in the second CPU in the fourth PCIe Switch, so as to switch the topology mode of the PCIe Switch to the single-uplink mode;

[0027] establishing the connection relationship between the first uplink port and the CPU in each PCIe Switch, and establishing the connection relationship between each port and the external device in each PCIe Switch, to generate the second mapping table in the single-uplink mode.

[0028] According to the external device management method provided by the application, the connection relationship between the first uplink port and the CPU in each PCIe Switch is established, and the connection relationship between each port and the external device in each PCIe Switch is established, which comprises:

[0029] In the first PCIe Switch, the connection relationship between the first uplink port and the first downlink port in the first CPU is established, the connection relationship between the first downlink port and the external device with the first serial number is established, and the connection relationship between the second downlink port and the external device with the second serial number is established.

[0030] In the second PCIe Switch, the connection relationship between the second uplink port and the third downlink port in the first CPU is established, the connection relationship between the second downlink port and the external device with the fourth serial number is established, and the connection relationship between the first downlink port and the external device with the third serial number is established.

[0031] In the third PCIe Switch, the connection relationship between the first uplink port and the first downlink port in the second CPU is established, the connection relationship between the second downlink port and the external device with the sixth serial number is established, and the connection relationship between the first downlink port and the external device with the fifth serial number is established.

[0032] In the fourth PCIe Switch, the connection relationship between the second uplink port and the third downlink port in the second CPU is established, the connection relationship between the first downlink port and the external device with the seventh serial number is established, and the connection relationship between the second downlink port and the external device with the eighth serial number is established.

[0033] According to the external device management method provided by the application, after the connection relationship between each port of each PCIe Switch and the CPU is constructed, the connection relationship between each port of each PCIe Switch and the external device is constructed, and then the corresponding relationship between each port of each PCIe Switch and the physical slot identification number PSN is constructed, the physical slot identification number PSN includes a first identification number, a second identification number, a third identification number, a fourth identification number, a fifth identification number, a sixth identification number, a seventh identification number and an eighth identification number numbered in ascending order;

[0034] The corresponding relationship between each port of each PCIe Switch and the physical slot identification number PSN is constructed, and specifically includes:

[0035] In the first PCIe Switch, the corresponding relationship between the first downstream port and the first identification number is constructed, and the connection relationship between the second downstream port and the second identification number is constructed;

[0036] In the second PCIe Switch, the connection relationship between the second downstream port and the third identification number is constructed, and the connection relationship between the first downstream port and the fourth identification number is constructed;

[0037] In the third PCIe Switch, the connection relationship between the second downstream port and the fifth identification number is constructed, and the connection relationship between the first downstream port and the sixth identification number is constructed;

[0038] In the fourth PCIe Switch, the connection relationship between the first downstream port and the seventh identification number is constructed, and the connection relationship between the second downstream port and the eighth identification number is constructed.

[0039] According to the external device management method provided by the application, the external device includes at least one of a high-speed serial computer expansion bus standard PCIe device, a fan, a power supply and a hard disk, and the PCIe device includes a graphics processor GPU.

[0040] In a second aspect, the application further provides an external device management apparatus, which includes:

[0041] The acquisition unit is configured to acquire the level state of the general input and output GPIO;

[0042] The first binding unit is configured to, when the level state is high, bind the serial number of the external device connected by the downstream port of each PCIe Switch according to the mapping relationship between the downstream port number of each PCIe Switch and the serial number of the external device in the first mapping table;

[0043] The second binding unit is configured to bind the serial number of the external device connected to the downstream port of each PCIe Switch according to the mapping relationship between the serial number of the external device and the downstream port number of each PCIe Switch in the second mapping table when the level state is low.

[0044] The topology mode of the PCIe Switch includes a double-uplink mode and a single-uplink mode.

[0045] The level state of the general input and output GPIO is determined by the topology mode of the bus exchange chip PCIe Switch.

[0046] In a third aspect, an electronic device is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the external device management method when executing the program.

[0047] In a fourth aspect, a non-transitory computer readable storage medium is provided, which stores a computer program, and the computer program is executable on a processor to implement the external device management method.

[0048] The application provides an external device management method, device, equipment and storage medium, the level state of the general input and output GPIO is determined according to the topology mode of the PCIe Switch, different mapping tables are called according to the difference between high level and low level to bind the serial number of each external device, so that the serial number of the external device of the out-of-band asset management and the serial number of the external device of the in-band system software are kept consistent, thereby avoiding applying multiple different PCIe Switch firmware boards, thereby reducing the cost of production, storage and assembly, the application can flexibly call different mapping tables, solve the problem of using multiple PCIe Switch firmware in different topology modes, realize dynamic alignment of the serial number of the external device, and do not need human intervention or replace the hardware board. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the application or prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0050] Figure 1 is one of the flowcharts of the external device management method provided by the application;

[0051] Figure 2Figure 2 is a flowchart of a method for managing an external device according to an embodiment of the present application;

[0052] Figure 3 Figure 3 is a flowchart of a method for managing an external device according to an embodiment of the present application;

[0053] Figure 4 Figure 4 is a flowchart of a method for managing an external device according to an embodiment of the present application;

[0054] Figure 5 Figure 5 is a flowchart of a method for managing an external device according to an embodiment of the present application;

[0055] Figure 6 Figure 6 is a connection diagram of a method for managing an external device according to an embodiment of the present application;

[0056] Figure 7 Figure 7 is a flowchart of a method for managing an external device according to an embodiment of the present application;

[0057] Figure 8 Figure 8 is a structural diagram of a device for managing an external device according to an embodiment of the present application;

[0058] Figure 9 Figure 9 is a structural diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some embodiments of the present application, but not all embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0060] Figure 1 Figure 1 is a flowchart of a method for managing an external device according to an embodiment of the present application. In the field of servers, a server usually has many external devices, the external devices including at least one of a Peripheral Component Interconnect Express (PCIe) device, a fan, a power supply and a hard disk, the PCIe device including a Graphics Processing Unit (GPU), and the number of each type of external device is usually greater than 1. Therefore, the external devices need to be numbered and monitored and managed in a Bus Master Controller (BMC), such as the number of devices, the health status, the device information, the maintenance record, etc. This process is called asset management.

[0061] An important part of asset management is the unification of device numbers, which needs to ensure that the device number silk screen, hardware number and BMC asset management list number on the case are consistent, so that when an external device is abnormal, maintenance personnel can quickly and accurately identify the target device and perform maintenance and replacement.

[0062] In an artificial intelligence (AI) server, the PCIe device includes a graphics processing unit (GPU), and the application will be described in detail with the GPU as a specific embodiment. According to different application requirements, the number of GPUs equipped is 4, 8, 16, etc., that is, the GPUs are usually numbered and managed in the manner of GPU0, GPU1, GPU2. In order to expand a sufficient number of GPUs or network cards, the AI server usually uses a PCIe switch to expand the PCIe.

[0063] Although the operation work in the AI server is mainly completed in the GPU, the CPU still bears part of the computing work, for example, GPU virtualization technology. In this application environment, the communication rate of the CPU and the downstream device is also greatly increased, so it is necessary to increase the uplink bandwidth of the PCIe switch. The PCIe switch usually uses a synthetic mode. In this mode, the uplink bandwidth of the PCIe switch can be configured in a dual-uplink mode of X16+X16.

[0064] In order to better describe the technical solutions of the application, the AI server with 8 GPUs is taken as an example. At this time, 4 PCIe switches need to be equipped, so a total of 8 CPU ports are occupied. For the platform server 2S EagleSteam, only 1 port is left for each CPU. Such a configuration cannot meet the demand of directly connecting the non-volatile memory host controller interface specification (NVMe) SSD, network card OCP or smart network card to the CPU. Therefore, it is necessary to reduce the uplink bandwidth of the PCIe switch to release more CPU ports for directly connecting the NVMe SSD, network card OCP or smart network card.

[0065] In order to realize flexible asset management of the AI server under different PCIe switch uplink bandwidth modes and solve the problem of using multiple PCIe switch firmware under different topologies, the application provides an external device management method, and the execution subject is a general input-output-to-paging channel (PCH). The method comprises the following steps:

[0066] Obtaining the level state of the general input-output (GPIO);

[0067] In the case that the level state is high, according to the mapping relationship between the downlink port number of each PCIe Switch and the serial number of the external device in the first mapping table, the serial number of the external device connected by the downlink port of each PCIe Switch is bound;

[0068] In the case that the level state is low, according to the mapping relationship between the downlink port number of each PCIe Switch and the serial number of the external device in the second mapping table, the serial number of the external device connected by the downlink port of each PCIe Switch is bound;

[0069] The topology mode of the PCIe Switch includes a double-uplink mode and a single-uplink mode.

[0070] The level state of the general input and output GPIO is determined by the bus switching chip PCIe Switch according to the topology mode of the bus switching chip PCIe Switch.

[0071] In step 101, the level state of the general input and output GPIO is obtained, and those skilled in the art understand that, as shown in the following table:

[0072] GPIO state PCIe Switch topology mode High Dual Uplink Low Single Uplink

[0073] In the initialization process of the PCIe Switch, the link state of the port is read, the register detects the link state of all ports, when detecting that the uplink port is double-uplink, the output GPIO is high, and when detecting that the uplink port is single-uplink, the output GPIO is low.

[0074] In an optional embodiment, the level state of the general input and output GPIO is obtained, including:

[0075] The bus switching chip PCIe Switch detects the connection state of the uplink port in all bus switching chips PCIe Switch, in the case that both uplink ports of the PCIe Switch have a connection relationship with the central processing unit CPU, the topology mode of the PCIe Switch is determined as double-uplink mode; in the case that one of the two uplink ports of the PCIe Switch has a connection relationship with the central processing unit CPU, the topology mode of the PCIe Switch is determined as single-uplink mode.

[0076] In the double-uplink mode, the level state of the general input and output GPIO is determined as high;

[0077] In the single-uplink mode, the level state of the general input and output GPIO is determined as low.

[0078] Specifically, the connection state of the uplink port in all bus exchange chips PCIe Switch is detected, and in the case that both uplink ports of the PCIe Switch are connected with the central processing unit CPU, that is, the PCIe Switch has two uplink ports, and each uplink port is connected with the CPU, it is determined that the topology mode of the PCIe Switch is a double uplink mode.

[0079] In the case that one of the two uplink ports of the PCIe Switch is connected with the central processing unit CPU, if only one port is connected with the CPU, it is determined that the topology mode of the PCIe Switch is a single uplink mode.

[0080] In the double uplink mode, the level state of the general input and output GPIO is determined to be high, so that in the following embodiment, the serial number of the external device, that is, the GPU, will be bound according to the mapping table corresponding to the high level. In the single uplink mode, the level state of the general input and output GPIO is determined to be low, so that in the following embodiment, the serial number of the external device, that is, the GPU, will be bound according to the mapping table corresponding to the low level.

[0081] In step 102, in the case that the level state is high, according to the mapping relationship between the downlink port number of each PCIe Switch and the serial number of the external device in the first mapping table, the serial number of the external device connected with the downlink port of each PCIe Switch is bound. The topology mode of the PCIe Switch includes a double uplink mode and a single uplink mode, and in different topology modes, different mapping tables are called.

[0082] The PCIe Switch includes a first PCIe Switch, a second PCIe Switch, a third PCIe Switch, and a fourth PCIe Switch;

[0083] The serial number of the external device includes at least a first serial number, a second serial number, a third serial number, a fourth serial number, a fifth serial number, a sixth serial number, a seventh serial number, and an eighth serial number.

[0084] In the first mapping table, the second downlink port of the second PCIe Switch corresponds to the third serial number, the first downlink port of the second PCIe Switch corresponds to the fourth serial number, the second downlink port of the third PCIe Switch corresponds to the fifth serial number, and the first downlink port of the third PCIe Switch corresponds to the sixth serial number.

[0085] In the second mapping table, the second downstream port of the second PCIe Switch corresponds to the fourth serial number, the first downstream port of the second PCIe Switch corresponds to the third serial number, the second downstream port of the third PCIe Switch corresponds to the sixth serial number, and the first downstream port of the third PCIe Switch corresponds to the fifth serial number.

[0086] In an optional embodiment, the PCIe Switches include a first PCIe Switch, a second PCIe Switch, a third PCIe Switch, and a fourth PCIe Switch, and in other embodiments, more PCIe Switches can be included. In this case, the serial numbers of the external devices include at least a first serial number, a second serial number, a third serial number, a fourth serial number, a fifth serial number, a sixth serial number, a seventh serial number, and an eighth serial number. The serial numbers of the external devices are bound and replaced according to different topology modes to dynamically meet the management of GPU serial numbers in different topology modes.

[0087] In the first mapping table, the first downstream port of the first PCIe Switch corresponds to the first serial number, the second downstream port of the first PCIe Switch corresponds to the second serial number, the first downstream port of the fourth PCIe Switch corresponds to the seventh serial number, and the second downstream port of the fourth PCIe Switch corresponds to the eighth serial number.

[0088] For the second PCIe Switch and the third PCIe Switch, the correspondence between the downstream ports of the PCIe Switches and the serial numbers in the mapping table is adjusted according to different topology modes. Specifically, in the first mapping table, the second downstream port of the second PCIe Switch corresponds to the third serial number, the first downstream port of the second PCIe Switch corresponds to the fourth serial number, the second downstream port of the third PCIe Switch corresponds to the fifth serial number, and the first downstream port of the third PCIe Switch corresponds to the sixth serial number.

[0089] In step 103, the following table shows:

[0090] PCIe Switch port Physical slot identification number First mapping table Second mapping table First PCIe Switch S1 100 GPU0 GPU0 First PCIe Switch S2 101 GPU1 GPU1 Second PCIe Switch S2 102 GPU2 GPU3 Second PCIe Switch S1 103 GPU3 GPU2 Third PCIe Switch S5 104 GPU4 GPU5 Third PCIe Switch S0 105 GPU5 GPU4 Fourth PCIe Switch S0 106 GPU6 GPU6 Fourth PCIe Switch S5 107 GPU7 GPU7

[0091] The first PCIe switch S1 is a first downlink port of the first PCIe switch, the first PCIe switch S2 is a second downlink port of the first PCIe switch, the second PCIe switch S2 is a second downlink port of the second PCIe switch, the second PCIe switch S1 is a first downlink port of the second PCIe switch, the third PCIe switch S5 is a second downlink port of the third PCIe switch, the third PCIe switch S0 is a first downlink port of the third PCIe switch, the fourth PCIe switch S0 is a first downlink port of the fourth PCIe switch, and the fourth PCIe switch S5 is a second downlink port of the fourth PCIe switch.

[0092] The GPU0 corresponds to a first serial number, the GPU1 corresponds to a second serial number, the GPU2 corresponds to a third serial number, the GPU3 corresponds to a fourth serial number, the GPU4 corresponds to a fifth serial number, the GPU5 corresponds to a sixth serial number, the GPU6 corresponds to a seventh serial number, and the GPU7 corresponds to an eighth serial number.

[0093] In the second mapping table, the first downlink port of the first PCIe switch corresponds to the first serial number, the second downlink port of the first PCIe switch corresponds to the second serial number, the first downlink port of the fourth PCIe switch corresponds to the seventh serial number, and the second downlink port of the fourth PCIe switch corresponds to the eighth serial number. However, for the second PCIe switch and the third PCIe switch, the corresponding relationship between the downlink port of the PCIe switch and the serial number in the mapping table is adjusted according to different topological modes. Specifically, the second downlink port of the second PCIe switch corresponds to the fourth serial number, the first downlink port of the second PCIe switch corresponds to the third serial number, the second downlink port of the third PCIe switch corresponds to the sixth serial number, and the first downlink port of the third PCIe switch corresponds to the fifth serial number.

[0094] The application provides an external device management method, device and equipment and a storage medium.

[0095] Figure 2 The application provides a flowchart of the external device management method, and before the level state of the general input and output GPIO is acquired, the connection relationship between each port in each PCIe Switch and a CPU is constructed, the connection relationship between each port in each PCIe Switch and an external device is constructed, and the first mapping table in a double-uplink mode is generated. Figure 2 The application provides a flowchart of the external device management method, and before the level state of the general input and output GPIO is acquired, the connection relationship between each port in each PCIe Switch and a CPU is constructed, the connection relationship between each port in each PCIe Switch and an external device is constructed, and the first mapping table in a double-uplink mode is generated.

[0096] In the first PCIe Switch, the connection relationship between the first uplink port and the first downlink port in the first CPU is constructed, the connection relationship between the second uplink port and the second downlink port in the first CPU is constructed, the connection relationship between the first downlink port and the external device with the first serial number is constructed, and the connection relationship between the second downlink port and the external device with the second serial number is constructed.

[0097] In the second PCIe Switch, the connection relationship between the second uplink port and the third downlink port in the first CPU is constructed, the connection relationship between the first uplink port and the fourth downlink port in the first CPU is constructed, the connection relationship between the second downlink port and the external device with the third serial number is constructed, and the connection relationship between the first downlink port and the external device with the fourth serial number is constructed.

[0098] In the third PCIe Switch, the connection relationship between the first uplink port and the first downlink port in the second CPU is constructed, the connection relationship between the second uplink port and the second downlink port in the second CPU is constructed, the connection relationship between the second downlink port and the external device with the fifth serial number is constructed, and the connection relationship between the first downlink port and the external device with the sixth serial number is constructed.

[0099] In the fourth PCIe Switch, a connection relationship between the second uplink port and the third downlink port in the second CPU is established, a connection relationship between the first uplink port and the fourth downlink port in the second CPU is established, a connection relationship between the first downlink port and the seventh serial number external device is established, and a connection relationship between the second downlink port and the eighth serial number external device is established.

[0100] The first CPU is connected to the second CPU through the UPI.

[0101] In step 201, the connection relationships between the ports in the first PCIe Switch and the uplink CPU and the downlink external device are mainly described. Specifically, in the double uplink mode, the first uplink port is connected to the first downlink port in the first CPU, the second uplink port is connected to the second downlink port in the first CPU, the first downlink port is connected to the first serial number external device, and the second downlink port is connected to the second serial number external device.

[0102] In step 202, in the second PCIe Switch, the second uplink port is connected to the third downlink port in the first CPU, the first uplink port is connected to the fourth downlink port in the first CPU, the second downlink port is connected to the third serial number external device, and the first downlink port is connected to the fourth serial number external device.

[0103] In step 203, in the third PCIe Switch, the first uplink port is connected to the first downlink port in the second CPU, the second uplink port is connected to the second downlink port in the second CPU, the second downlink port is connected to the fifth serial number external device, and the first downlink port is connected to the sixth serial number external device.

[0104] In step 204, in the fourth PCIe Switch, the second uplink port is connected to the third downlink port in the second CPU, the first uplink port is connected to the fourth downlink port in the second CPU, the first downlink port is connected to the seventh serial number external device, and the second downlink port is connected to the eighth serial number external device.

[0105] The first CPU is connected to the second CPU through the UPI to form a 2S server, wherein four downlink ports exist in each CPU, and then the first mapping table is generated according to the above connection relationships.

[0106] Figure 3 is the third flowchart of the external device management method provided by the application, after the first mapping table in the double uplink mode is generated, the method further includes:

[0107] the connection between the second uplink port and the second downlink port in the first CPU is disconnected in the first PCIe Switch, the connection between the first uplink port and the fourth downlink port in the first CPU is disconnected in the second PCIe Switch, the connection between the second uplink port and the second downlink port in the second CPU is disconnected in the third PCIe Switch, and the connection between the first uplink port and the fourth downlink port in the second CPU is disconnected in the fourth PCIe Switch, so as to switch the topology mode of the PCIe Switch to the single-uplink mode.

[0108] The connection between the first uplink port and the CPU in each PCIe Switch is constructed, the connection between each port in each PCIe Switch and the external device is constructed, and the second mapping table in the single-uplink mode is generated.

[0109] In step 301, in the case of adjusting from the double-uplink mode to the single-uplink mode, since the binding relationship between the physical slot identification number of the basic input output system (BIOS) and the identification sequence number of the GPU device is no longer consistent with the identification sequence number in the double-uplink mode in the asset management, it is necessary to correct the binding of the identification sequence number according to the second mapping table, and if the correction is not performed, the asset management will be chaotic.

[0110] In the single-uplink mode, each PCIe Switch has only one uplink port connected with any CPU, at this time, it is necessary to disconnect the connection between one of the uplink ports and the CPU, so the connection between the second uplink port and the second downlink port in the first CPU is disconnected in the first PCIe Switch, the connection between the first uplink port and the fourth downlink port in the first CPU is disconnected in the second PCIe Switch, the connection between the second uplink port and the second downlink port in the second CPU is disconnected in the third PCIe Switch, and the connection between the first uplink port and the fourth downlink port in the second CPU is disconnected in the fourth PCIe Switch, after the connection between one of the uplink ports in all the PCIe Switches and the corresponding CPU is disconnected, the topology mode of the PCIe Switch is switched to the single-uplink mode.

[0111] In step 302, the connection relationship between the first uplink port in each PCIe switch and the CPU is constructed, the connection relationship between each port in each PCIe switch and the external device is constructed, and the second mapping table in the single uplink mode is generated, so that the serial number of the GPU in the out-of-band asset management and the serial number of the GPU in the OS application remain consistent without human intervention or replacement of the hardware board, and in order to obtain the second mapping table in the single uplink mode, the connection relationship between the first uplink port in each PCIe switch and the CPU under the condition of ensuring the consistency of the serial number of the GPU is simulated, the connection relationship between each port in each PCIe switch and the external device is simulated, and then the second mapping table is extracted according to the above connection relationship.

[0112] Figure 4 Figure four is a flowchart of the external device management method provided by the application, and the connection relationship between the first uplink port in each PCIe switch and the CPU is constructed, and the connection relationship between each port in each PCIe switch and the external device is constructed.

[0113] In the first PCIe switch, the connection relationship between the first uplink port and the first downlink port in the first CPU is constructed, the connection relationship between the first downlink port and the external device with the first serial number is constructed, and the connection relationship between the second downlink port and the external device with the second serial number is constructed.

[0114] In the second PCIe switch, the connection relationship between the second uplink port and the third downlink port in the first CPU is constructed, the connection relationship between the second downlink port and the external device with the fourth serial number is constructed, and the connection relationship between the first downlink port and the external device with the third serial number is constructed.

[0115] In the third PCIe switch, the connection relationship between the first uplink port and the first downlink port in the second CPU is constructed, the connection relationship between the second downlink port and the external device with the sixth serial number is constructed, and the connection relationship between the first downlink port and the external device with the fifth serial number is constructed.

[0116] In the fourth PCIe switch, the connection relationship between the second uplink port and the third downlink port in the second CPU is constructed, the connection relationship between the first downlink port and the external device with the seventh serial number is constructed, and the connection relationship between the second downlink port and the external device with the eighth serial number is constructed.

[0117] In step 3021, in the first PCIe switch, the first uplink port in the first PCIe switch is connected with the first downlink port in the first CPU, the first downlink port in the first PCIe switch is connected with the external device with the first serial number, and the second downlink port in the first PCIe switch is connected with the external device with the second serial number.

[0118] In step 3022, in the second PCIe Switch, the second uplink port in the second PCIe Switch is connected with the third downlink port in the first CPU, the second downlink port in the second PCIe Switch is connected with the fourth serial number external device, and the first downlink port in the second PCIe Switch is connected with the third serial number external device.

[0119] In step 3023, in the third PCIe Switch, the first uplink port in the third PCIe Switch is connected with the first downlink port in the second CPU, the second downlink port in the third PCIe Switch is connected with the sixth serial number external device, and the first downlink port in the third PCIe Switch is connected with the fifth serial number external device.

[0120] In step 3024, in the fourth PCIe Switch, the second uplink port in the fourth PCIe Switch is connected with the third downlink port in the second CPU, the first downlink port in the fourth PCIe Switch is connected with the seventh serial number external device, and the second downlink port in the fourth PCIe Switch is connected with the eighth serial number external device.

[0121] Figure 5 is the fifth flowchart of the external device management method provided by the application, after the connection relationship between each port in each PCIe Switch and the CPU is constructed, and the connection relationship between each port in each PCIe Switch and the external device is constructed, the corresponding relationship between each port in each PCIe Switch and the physical slot identification number PSN is constructed, the physical slot identification number PSN includes the first identification number, the second identification number, the third identification number, the fourth identification number, the fifth identification number, the sixth identification number, the seventh identification number and the eighth identification number numbered in ascending order;

[0122] The construction of the corresponding relationship between each port in each PCIe Switch and the physical slot identification number PSN specifically includes:

[0123] In the first PCIe Switch, the corresponding relationship between the first downlink port and the first identification number is constructed, and the connection relationship between the second downlink port and the second identification number is constructed;

[0124] In the second PCIe Switch, the connection relationship between the second downlink port and the third identification number is constructed, and the connection relationship between the first downlink port and the fourth identification number is constructed;

[0125] In the third PCIe Switch, the connection relationship between the second downlink port and the fifth identification number is constructed, and the connection relationship between the first downlink port and the sixth identification number is constructed;

[0126] In the fourth PCIe Switch, the first downstream port is connected with the seventh identification number, and the second downstream port is connected with the eighth identification number.

[0127] In step 401, the physical slot identification number (PSN) is determined by the developer in the PCIe configuration space standard register Slot Capability Register, and the asset management of the GPU type device by the BIOS and BMC is located by the physical slot identification number. If the PCIe device is hung under the digital signal processing DSP of the PCIe Switch, it is set by the firmware of the PCIe Switch. No matter what device is connected, the physical slot identification number is constant. In the server asset management operation, the BIOS sends the physical slot identification number of the downstream device, the serial number of the external device and other state information to the BMC, and displays them on the web page of the BMC. Usually, the GPU serial number information displayed on the BMC and the system application, such as the cross-platform tool Nvidia-smi or the program NVqual of NVIDIA, should be consistent, so as to avoid confusion.

[0128] In the first PCIe Switch, the first downstream port corresponds to the first identification number, and the second downstream port corresponds to the second identification number. No matter whether it is a double-up mode or a single-up mode, the corresponding relationship between the first downstream port and the first identification number and the corresponding relationship between the second downstream port and the second identification number will not change, and only the serial number of the GPU connected under the downstream port of the PCIe Switch will change.

[0129] In step 402, in the second PCIe Switch, the connection relationship between the second downstream port and the third identification number is not changed, and the connection relationship between the first downstream port and the fourth identification number is not changed.

[0130] In step 403, in the third PCIe Switch, the connection relationship between the second downstream port and the fifth identification number is not changed, and the connection relationship between the first downstream port and the sixth identification number is not changed.

[0131] In step 404, in the fourth PCIe Switch, the connection relationship between the first downstream port and the seventh identification number is not changed, and the connection relationship between the second downstream port and the eighth identification number is not changed.

[0132] Figure 6 is a connection diagram of the external device management method provided by the application, asFigure 6 As shown, the central processing unit 0 is a first CPU, and the central processing unit 1 is a second CPU. The central processing unit 0 and the central processing unit 1 are interconnected through a fast channel interconnection UPI to form a 2S server. In this embodiment, the central processing unit 0 and the central processing unit 1 each have four PCIE ports, which are respectively P0, P2, P3, and P4. In the dual-uplink topology mode, the total of eight ports of the central processing unit 0 and the central processing unit 1 are all connected to the eight uplink ports of four PCIe Switches, wherein each PCIe Switch has two uplink ports. In the single-uplink topology, the port P2 and the port P4 are not connected to the uplink ports of the PCIe Switch, which are marked by a dashed line in the figure. Figure 6

[0133] As shown in FIG. 6, the bus exchange chip A, the bus exchange chip B, the bus exchange chip C, and the bus exchange chip D are respectively PCIe Switches. For the convenience of description, the topology is simplified, and only the ports Station used are shown. Each port Station has an X16 bandwidth. The uplink of the PCIe Switch is connected to the CPU through two or one port Station. The downlink of the PCIe Switch is connected to the GPU. In this application, a total of eight GPUs are supported. Figure 6 The PCIe Switch is configured in a synthetic mode. Therefore, the uplink of each PCIe Switch has two groups of X16 bandwidths connected to the CPU. Taking the bus exchange chip A as an example, S6 and S7 are its uplink ports, which are respectively connected to P0 and P2 of the central processing unit 0. The downlink ports of the bus exchange chip A are S1 and S2, which are respectively connected to the image processor 0 and the image processor 1.

[0134] The S6 and the S1 of the bus exchange chip A have a mapping relationship, and the S7 and the S2 have a mapping relationship. The mapping relationship is configured through the firmware of the PCIe Switch. In the training process of the PCIe at startup, the basic input / output system (BIOS) performs a depth-first scan in the order of the CPU ports from small to large, and allocates bus / device / function (Bus / Dev / Fun) and memory resources for the downstream PCIe devices. Since the image processor 0 corresponds to the port P0 of the central processing unit 0, and the image processor 1 corresponds to the port P2 of the central processing unit 0, the Bus / Dev / Fun of the image processor 0 is the smallest, and the same applies to the image processor 7. The application software of the system, such as the cross-platform tool Nvidia-smi of NVIDIA or the program NVqual, also processes the image processor serial number in the order from small to large. Therefore, the image processor 0 is the first GPU, and the image processor 7 is the eighth GPU.

[0135] Figure 6 ​​The serial numbers of the image processors in the figure are named in the order of the port numbers of the image processors, i.e. Bus / Dev / Fun from small to large, which are image processor 0, image processor 1, image processor 2, image processor 3, image processor 4, image processor 5, image processor 6 and image processor 7, respectively, corresponding to the first serial number, the second serial number, the third serial number, the fourth serial number, the fifth serial number, the sixth serial number, the seventh serial number and the eighth serial number of the serial numbers of the external devices, respectively.

[0136] However, if the uplink bandwidth of the PCIe Switch is changed, i.e. each PCIe Switch is connected to only one X16 to the CPU, i.e. the topology mode is changed to the single uplink bandwidth mode at this time. In such an embodiment, taking bus switch chip A as an example, the port S6 of the bus switch chip A is connected to the port P0 of the central processing unit 0, and the ports S1 and S2 of the bus switch chip A are connected to the image processor 0 and the image processor 1 through their downlink ports. In the training process of PCIe, the Bus / Dev / Fun of the PCIe Switch is enumerated in the order of S0, S1, S2, S5, S6 and S7 from small to large in the figure. Figure 6 The Bus / Dev / Fun of the ports S0, S1, S2, S5, S6 and S7 in the figure is enumerated in the order from small to large, i.e. the Bus / Dev / Fun corresponding to the port S1 is smaller, and the Bus / Dev / Fun corresponding to the port S2 is larger. The bus switch chip A is not affected. However, for the bus switch chip B and the bus switch chip C, the Bus / Dev / Fun of the image processors connected by their downlink ports will change.

[0137] Specifically, the Bus / Dev / Fun of the port S1 of the bus switch chip B is smaller than that of the port S2 after the enumeration, so the system application such as the Nvidia-smi or nvqual of NVIDIA will sort the image processors connected by the port S1 of the bus switch chip B as the image processor 2, and the image processors connected by the port S2 as the image processor 3. In this case, when facing asset management, the binding relationship between the physical slot identification number of the basic input / output system (BIOS) and the identifier of the GPU device, such as the identifier of the representative device name of the image processor 0 and the image processor 1, is no longer consistent with that in the double uplink mode, and if not corrected, the asset management of the image processor 2, the image processor 3, the image processor 4 and the image processor 5 will be chaotic.

[0138] In order to overcome the technical problems of confusion in asset management, the physical slot identification number of the digital signal processing DSP of the PCIe Switch is allocated according to the table in step 103, and each physical slot identification number corresponds to a GPU serial number, and the application constructs a mapping table in which two physical slot identification numbers and the serial number of the image processor exist in a corresponding relationship, as shown in Figure 6 As shown in the table in step 101, in the initialization process of the PCIe Switch, the link state of all ports is detected by reading the Link Status register of the port, and when it is detected that the uplink port is double uplink, the GPIO is output as high level, and the BIOS binds the GPU serial number according to the first mapping table; when it is detected that the uplink port is single uplink, the GPIO is output as low level, and the BIOS binds the GPU serial number according to the second mapping table. Therefore, the paging channel PCH calls different mapping relationship tables of the physical slot identification number and the identifier of the image processor device according to the GPIO state, realizes dynamic alignment, so as to ensure that the serial number of the image processor in the out-of-band asset management and the serial number of the image processor under the application of the operating system always remain consistent, without human intervention or replacement of the hardware board.

[0139] Figure 7 It is the sixth flowchart of the external device management method provided by the application, specifically, the PCIe Switch reads the uplink state through the Link Status register of the port, and when it is in the double uplink mode, it is determined that the GPIO output by the PCIe Switch is high level, and the first mapping table binds the GPU serial number; when it is detected that the uplink port is single uplink, the GPIO is output as low level, and the BIOS binds the GPU serial number according to the second mapping table, and after binding the GPU serial number, the BIOS sends asset information to the BMC to realize the management of the GPU by the application under the operating system.

[0140] The application provides an external device management method, device, equipment and storage medium, the level state of the general input and output GPIO is determined according to the topology mode of the PCIe Switch, different mapping tables are called respectively according to the difference between high level and low level to bind the serial number of each external device, so that the serial number of the external device in the out-of-band asset management and the serial number of the external device in the in-band system software remain consistent, so as to avoid applying multiple different PCIe Switch firmware boards, thereby reducing the cost of production, storage and assembly, the application can flexibly call different mapping tables, solve the problem of using multiple PCIe Switch firmware in different topology modes, realize dynamic alignment of the serial number of the external device, and do not need human intervention or replacement of the hardware board.

[0141] Figure 8 is the structural schematic diagram of the external device management apparatus provided by the application, the application provides an external device management apparatus, comprising an acquisition unit 1: for acquiring the level state of general input and output GPIO, the working principle of the acquisition unit 1 can refer to the preceding step 101, and here is not repeated.

[0142] The external device management apparatus further comprises a first binding unit 2: for binding the serial number of the external device connected by the downstream port of each PCIe Switch according to the mapping relationship between the serial number of the external device and the downstream port number of each PCIe Switch in the first mapping table when the level state is high, and the working principle of the first binding unit 2 can refer to the preceding step 102, and here is not repeated.

[0143] The external device management apparatus further comprises a second binding unit 3: for binding the serial number of the external device connected by the downstream port of each PCIe Switch according to the mapping relationship between the serial number of the external device and the downstream port number of each PCIe Switch in the second mapping table when the level state is low, and the working principle of the second binding unit 3 can refer to the preceding step 103, and here is not repeated.

[0144] The topology mode of the PCIe Switch comprises a double-uplink mode and a single-uplink mode;

[0145] The level state of the general input and output GPIO is determined by the bus exchange chip PCIe Switch according to the topology mode of the bus exchange chip PCIe Switch.

[0146] The application provides an external device management method, apparatus and device and storage medium, the level state of general input and output GPIO is determined according to the topology mode of the PCIe Switch, different mapping tables are called according to the difference between high level and low level to bind the serial number of each external device, so that the serial number of the external device of the out-of-band asset management and the serial number of the external device of the in-band system software remain consistent, thereby avoiding applying multiple different PCIe Switch firmware boards, thereby reducing the cost of production and storage, assembly, the application can flexibly call different mapping tables, solve the problem of using multiple PCIe Switch firmware under different topology modes, realize dynamic alignment of the serial number of the external device, and do not need artificial intervention or replacement of hardware boards.

[0147] Figure 9 is the structural schematic diagram of the electronic device provided by the application. Figure 9As shown, the electronic device can include a processor 910, a communications interface 920, a memory 930, and a communications bus 940, wherein the processor 910, the communications interface 920, and the memory 930 complete mutual communication through the communications bus 940. The processor 910 can invoke a logical instruction in the memory 930 to execute an external device management method, which includes: acquiring a level state of a general input and output GPIO; in a case where the level state is a high level, binding a serial number of an external device connected to a downlink port of each PCIe Switch according to a mapping relationship between the downlink port number of each PCIe Switch and the serial number of the external device in a first mapping table; in a case where the level state is a low level, binding the serial number of the external device connected to the downlink port of each PCIe Switch according to the mapping relationship between the downlink port number of each PCIe Switch and the serial number of the external device in a second mapping table; the topology mode of the PCIe Switch includes a double-uplink mode and a single-uplink mode; and the level state of the general input and output GPIO is determined by the bus switching chip PCIe Switch according to the topology mode of the bus switching chip PCIe Switch.

[0148] In addition, the logical instruction in the memory 930 described above can be implemented in the form of a software functional unit and sold or used as an independent product, and can be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the present application essentially or in part or part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various program code storage media.

[0149] In another aspect, the present application also provides a computer program product, which comprises a computer program, the computer program being stored in a non-transitory computer readable storage medium, and the computer program being executable by a processor to enable the computer to perform the external device management method provided by any of the above methods, the method comprising: obtaining a level state of a general input-output GPIO; in a case where the level state is a high level, binding a serial number of an external device connected to a downstream port of each PCIe Switch according to a mapping relationship between the serial number of the external device and a downstream port number of each PCIe Switch in a first mapping table; in a case where the level state is a low level, binding the serial number of the external device connected to the downstream port of each PCIe Switch according to a mapping relationship between the serial number of the external device and the downstream port number of each PCIe Switch in a second mapping table; the topology mode of the PCIe Switch comprising a double-uplink mode and a single-uplink mode; and the level state of the general input-output GPIO being determined by a bus switch chip PCIe Switch according to the topology mode of the bus switch chip PCIe Switch.

[0150] In another aspect, the present application also provides a non-transitory computer readable storage medium, which stores a computer program, the computer program being executable by a processor to implement the external device management method provided by any of the above methods, the method comprising: obtaining a level state of a general input-output GPIO; in a case where the level state is a high level, binding a serial number of an external device connected to a downstream port of each PCIe Switch according to a mapping relationship between the serial number of the external device and a downstream port number of each PCIe Switch in a first mapping table; in a case where the level state is a low level, binding the serial number of the external device connected to the downstream port of each PCIe Switch according to a mapping relationship between the serial number of the external device and the downstream port number of each PCIe Switch in a second mapping table; the topology mode of the PCIe Switch comprising a double-uplink mode and a single-uplink mode; and the level state of the general input-output GPIO being determined by a bus switch chip PCIe Switch according to the topology mode of the bus switch chip PCIe Switch.

[0151] The device embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the present embodiment scheme according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0152] Those skilled in the art can clearly understand the implementation of the embodiments by means of software and necessary general hardware platforms through the description of the above embodiments, and of course, the embodiments can also be implemented by hardware. Based on such understanding, the above technical solutions can be embodied in the form of a software product, and the computer software product can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0153] Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacement for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An external device management method, characterized by, The GPIO is applied to a general input / output-to-paging channel (GPIO-to-PCH). There is one GPIO-to-PCH for each PCIe switch. The GPIO-to-PCH calls different mapping tables according to the level state of the GPIO, including: obtaining the level state of the GPIO; in the case that the level state is high, binding the serial number of the external device connected to the downstream port of each PCIe switch according to the mapping relationship between the serial number of the external device and the downstream port number of each PCIe switch in the first mapping table; in the case that the level state is low, binding the serial number of the external device connected to the downstream port of each PCIe switch according to the mapping relationship between the serial number of the external device and the downstream port number of each PCIe switch in the second mapping table; the topology mode of the PCIe switch includes a double-uplink mode and a single-uplink mode; the level state of the GPIO is determined by the PCIe switch according to the topology mode of the PCIe switch; the obtaining of the level state of the GPIO includes: the PCIe switch detects the connection state of the uplink port in all PCIe switches. In the case that both uplink ports of the PCIe switch are connected to the CPU, the topology mode of the PCIe switch is determined to be the double-uplink mode. In the case that one of the two uplink ports of the PCIe switch is connected to the CPU, the topology mode of the PCIe switch is determined to be the single-uplink mode; in the double-uplink mode, the level state of the GPIO is determined to be high; in the single-uplink mode, the level state of the GPIO is determined to be low.

2. The external device management method of claim 1, wherein, the PCIe switch includes a first PCIe switch, a second PCIe switch, a third PCIe switch, and a fourth PCIe switch; the serial number of the external device includes at least a first serial number, a second serial number, a third serial number, a fourth serial number, a fifth serial number, a sixth serial number, a seventh serial number, and an eighth serial number; in the first mapping table, the second downstream port of the second PCIe switch corresponds to the third serial number, the first downstream port of the second PCIe switch corresponds to the fourth serial number, the second downstream port of the third PCIe switch corresponds to the fifth serial number, and the first downstream port of the third PCIe switch corresponds to the sixth serial number; In the second mapping table, the second downstream port of the second PCIe Switch corresponds to the fourth serial number, the first downstream port of the second PCIe Switch corresponds to the third serial number, the second downstream port of the third PCIe Switch corresponds to the sixth serial number, and the first downstream port of the third PCIe Switch corresponds to the fifth serial number. 3.The external device management method of claim 1, wherein, Before acquiring the level state of the general input and output GPIO, the connection relationship between each port in each PCIe Switch and the CPU is constructed, the connection relationship between each port in each PCIe Switch and the external device is constructed, and the first mapping table in the double-up mode is generated. The connection relationship between each port in each PCIe Switch and the CPU is constructed, and the connection relationship between each port in each PCIe Switch and the external device is constructed, and specifically includes: In the first PCIe Switch, the connection relationship between the first upstream port and the first downstream port in the first CPU is constructed, the connection relationship between the second upstream port and the second downstream port in the first CPU is constructed, the connection relationship between the first downstream port and the first serial number external device is constructed, and the connection relationship between the second downstream port and the second serial number external device is constructed. In the second PCIe Switch, the connection relationship between the second upstream port and the third downstream port in the first CPU is constructed, the connection relationship between the first upstream port and the fourth downstream port in the first CPU is constructed, the connection relationship between the second downstream port and the third serial number external device is constructed, and the connection relationship between the first downstream port and the fourth serial number external device is constructed. In the third PCIe Switch, the connection relationship between the first upstream port and the first downstream port in the second CPU is constructed, the connection relationship between the second upstream port and the second downstream port in the second CPU is constructed, the connection relationship between the second downstream port and the fifth serial number external device is constructed, and the connection relationship between the first downstream port and the sixth serial number external device is constructed. In the fourth PCIe Switch, the connection relationship between the second upstream port and the third downstream port in the second CPU is constructed, the connection relationship between the first upstream port and the fourth downstream port in the second CPU is constructed, the connection relationship between the first downstream port and the seventh serial number external device is constructed, and the connection relationship between the second downstream port and the eighth serial number external device is constructed. The first CPU is connected to the second CPU through the quick channel interconnection UPI.

4. The external device management method of claim 3, wherein, After the first mapping table in the double-up mode is generated, it further includes: interrupting the connection relationship between the second uplink port and the second downlink port in the first CPU in the first PCIe Switch, interrupting the connection relationship between the first uplink port and the fourth downlink port in the first CPU in the second PCIe Switch, interrupting the connection relationship between the second uplink port and the second downlink port in the second CPU in the third PCIe Switch, and interrupting the connection relationship between the first uplink port and the fourth downlink port in the second CPU in the fourth PCIe Switch, so as to switch the topology mode of the PCIe Switch to the single-uplink mode; constructing the connection relationship between the first uplink port and the CPU in each PCIe Switch, and constructing the connection relationship between each port and the external device in each PCIe Switch, to generate the second mapping table in the single-uplink mode.

5. The external device management method of claim 4, wherein, The method for constructing the connection relationship between the first uplink port and the CPU in each PCIe Switch and the connection relationship between each port and the external device in each PCIe Switch comprises: in the first PCIe Switch, constructing the connection relationship between the first uplink port and the first downlink port in the first CPU, constructing the connection relationship between the first downlink port and the external device of the first serial number, and constructing the connection relationship between the second downlink port and the external device of the second serial number; in the second PCIe Switch, constructing the connection relationship between the second uplink port and the third downlink port in the first CPU, constructing the connection relationship between the second downlink port and the external device of the fourth serial number, and constructing the connection relationship between the first downlink port and the external device of the third serial number; in the third PCIe Switch, constructing the connection relationship between the first uplink port and the first downlink port in the second CPU, constructing the connection relationship between the second downlink port and the external device of the sixth serial number, and constructing the connection relationship between the first downlink port and the external device of the fifth serial number; in the fourth PCIe Switch, constructing the connection relationship between the second uplink port and the third downlink port in the second CPU, constructing the connection relationship between the first downlink port and the external device of the seventh serial number, and constructing the connection relationship between the second downlink port and the external device of the eighth serial number.

6. The external device management method of claim 3, wherein, After constructing the connection relationship between each port and the CPU in each PCIe Switch and the connection relationship between each port and the external device in each PCIe Switch, a corresponding relationship between each port and a physical slot identification number PSN is constructed, the physical slot identification number PSN comprising a first identification number, a second identification number, a third identification number, a fourth identification number, a fifth identification number, a sixth identification number, a seventh identification number and an eighth identification number numbered in ascending order; The method for constructing the corresponding relationship between each port and the physical slot identification number PSN in each PCIe Switch comprises: in the first PCIe Switch, constructing the corresponding relationship between the first downlink port and the first identification number, and constructing the connection relationship between the second downlink port and the second identification number; In the second PCIe Switch, a connection relationship between the second downstream port and the third identification number is established, and a connection relationship between the first downstream port and the fourth identification number is established; In the third PCIe Switch, a connection relationship between the second downstream port and the fifth identification number is established, and a connection relationship between the first downstream port and the sixth identification number is established; In the fourth PCIe Switch, a connection relationship between the first downstream port and the seventh identification number is established, and a connection relationship between the second downstream port and the eighth identification number is established. 7.The external device management method of claim 1, wherein, The external device includes at least one of a Peripheral Component Interconnect Express (PCIe) device, a fan, a power supply, and a hard disk, and the PCIe device includes a Graphics Processing Unit (GPU).

8. An external device management apparatus characterized by comprising: The GPIO is applied to a General Purpose Input Output (GPIO) to a Paging Channel (PCH), wherein each PCIe Switch has one GPIO to PCH, and the GPIO to PCH calls different mapping tables according to the level state of the GPIO, including: An acquisition unit configured to acquire a level state of a General Purpose Input Output (GPIO); A first binding unit configured to, in a case where the level state is high, bind a serial number of an external device connected to a downstream port of each PCIe Switch according to a mapping relationship between the downstream port number of each PCIe Switch and the serial number of the external device in a first mapping table; A second binding unit configured to, in a case where the level state is low, bind a serial number of an external device connected to a downstream port of each PCIe Switch according to a mapping relationship between the downstream port number of each PCIe Switch and the serial number of the external device in a second mapping table; The topology mode of the PCIe Switch includes a double-uplink mode and a single-uplink mode; The level state of the GPIO is determined by the bus switch chip PCIe Switch according to the topology mode of the bus switch chip PCIe Switch; The acquisition of the level state of the GPIO includes: The bus switch chip PCIe Switch detects the connection state of the uplink port in all bus switch chips PCIe Switches, and in a case where both uplink ports of the PCIe Switch have a connection relationship with the Central Processing Unit (CPU), the topology mode of the PCIe Switch is determined to be the double-uplink mode; in a case where one of the two uplink ports of the PCIe Switch has a connection relationship with the CPU, the topology mode of the PCIe Switch is determined to be the single-uplink mode; In the double-uplink mode, the level state of the GPIO is determined to be high; In the single-uplink mode, the level state of the GPIO is determined to be low.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the external device management method of any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the external device management method of any one of claims 1 to 7.

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