Synchronous boost circuit, floating gate voltage control method, chip, and electronic device

Abstract

The application discloses a synchronous boosting circuit, a floating gate voltage control method, a chip and electronic equipment, which can prevent the floating ground potential from being pulled to be too high due to excessive instantaneous current, and cause circuit logic error. The synchronous boosting circuit comprises a power output module, the power output module comprises a rectifier power tube, one end of the rectifier power tube is coupled to an input voltage end of the power output module, and the other end is coupled to an output voltage end of the power output module; a floating control module, the floating control module uses the output voltage as a working power supply, uses a floating ground power supply as a ground end signal, is used for floating control of a gate voltage of the rectifier power tube, discharges a gate charge of the rectifier power tube, and clamps the gate-source voltage of the rectifier power tube to be within a withstand voltage value.

Description

Technical Field

[0001] This application relates to the field of power supplies, specifically to synchronous boost circuits, floating gate voltage control methods, chips, and electronic devices. Background Technology

[0002] Synchronous boost circuits typically use rectifier PMOS power transistors to boost the output voltage. If the final output voltage is too high, it will cause the gate-source or gate-drain terminals of the rectifier PMOS transistor to be subjected to excessively high voltage, which will lead to abnormal operation of the rectifier PMOS transistor.

[0003] To keep the gate-source or gate-drain voltage of the rectifier PMOS transistor within a safe range, one approach is to use a clamping circuit to clamp the gate voltage potential of the PMOS power transistor. However, this clamping method increases the power consumption of the synchronous boost circuit. Another approach is to use a floating ground power supply to drive the rectifier PMOS transistor. This requires specific design requirements for the floating ground power supply, at least ensuring it has sufficient current sinking capability to prevent excessively high potentials caused by sudden surges in current, which could lead to circuit logic errors. Summary of the Invention

[0004] In view of this, this application provides a synchronous boost circuit, a floating gate voltage control method, a chip, and an electronic device, which can prevent the floating ground potential from being pulled too high due to excessive instantaneous current, thus preventing circuit logic errors.

[0005] This application provides a synchronous boost circuit, comprising: a power output module, the power output module including a rectifier power transistor, one end of the rectifier power transistor being coupled to the input voltage terminal of the power output module, and the other end being coupled to the output voltage terminal of the power output module; and a float control module, the float control module using the output voltage as the operating power supply and a floating ground power supply as the ground terminal signal, for float control of the gate voltage of the rectifier power transistor, for discharging the gate charge of the rectifier power transistor, and for clamping the gate-source voltage of the rectifier power transistor to within the withstand voltage value.

[0006] Optionally, the floating control module includes a driving unit, which includes: an eleventh inverter for acquiring the driving signal and inverting the driving signal; a first transistor with its source connected to the source of the rectifier power transistor and its gate connected to the output of the eleventh inverter; a first inverter and a second inverter connected in series, the input of the first inverter being used to acquire the driving signal and its output being connected to the second inverter, and the output of the second inverter being connected to the gate of the rectifier power transistor; and a second transistor with its drain grounded, its gate being used to acquire the driving signal, and its source being connected to the drain of the first transistor.

[0007] Optionally, the floating control module further includes a second floating control unit. The input terminal of the second floating control unit is connected to a drive signal, and the output terminal is connected to the input terminal of the first inverter and the gate of the second transistor, so as to perform floating control on the gate voltage of the second transistor and clamp the gate-source voltage of the second transistor to within the withstand voltage value of the second transistor.

[0008] Optionally, the second floating control unit includes a second control subunit; the second control subunit includes: a second inverter group, including an even number of inverters connected in series; a second release transistor, the source of which is connected to the output terminal of the second inverter group, the gate of which is connected to the input terminal of the second inverter group, and the drain of which is grounded; the inverters in the second inverter group are composed of MOS transistors, and the size of the MOS transistors is smaller than the size of the second release transistor.

[0009] Optionally, the second floating control unit includes several second control subunits, and the inverter groups of each second control subunit are connected in series to form a second inverter group series path. The input terminal of the second inverter group series path is used to connect to the drive signal, and the output terminal is connected to the gate of the second transistor.

[0010] Optionally, the floating control module further includes a first floating control unit, the input terminal of which is connected to the output terminal of the eleventh inverter, and the output terminal is connected to the gate of the first transistor, for floating control of the gate voltage of the first transistor, clamping the gate-source voltage of the first transistor to within the withstand voltage value of the first transistor.

[0011] Optionally, the first floating control unit includes a first control subunit; the first control subunit includes: a first inverter group, including an even number of inverters connected in series; a first release transistor, the source of which is connected to the output terminal of the first inverter group, the gate of which is connected to the input terminal of the first inverter group, and the drain of which is grounded; the inverters in the first inverter group are composed of MOS transistors, and the size of the MOS transistors is smaller than the size of the first release transistor.

[0012] Optionally, the first floating control unit includes several first control subunits, and the first inverter groups of each first control subunit are connected in series to form a first inverter group series path. The input terminal of the first inverter group series path is used to connect to the drive signal, and the output terminal is connected to the gate of the first transistor.

[0013] Optionally, the floating control module further includes: a level conversion unit, used to receive a drive signal, convert the level value of the drive signal to a voltage range between the output voltage and the floating ground power supply, and output it to the first floating control unit and the second floating control unit.

[0014] Optionally, the rectifier power transistor is a PMOS power transistor; the power output module further includes an inductor connected in series between the drain of the PMOS power transistor and the input voltage terminal, and the source of the PMOS power transistor is connected to the output voltage terminal.

[0015] This application also provides a floating gate voltage control method, applied to any of the above-mentioned synchronous boost circuits, comprising the following steps:

[0016] The gate voltage of the rectifier power transistor is controlled by floating.

[0017] The gate charge of the rectifier power transistor is discharged to clamp the gate-source voltage of the rectifier power transistor to within the withstand voltage value.

[0018] This application also provides a chip including any of the above-described synchronous boost circuits.

[0019] This application also provides an electronic device, including any of the above-described synchronous boost circuits or any of the above-described chips.

[0020] The synchronous boost circuit in this application uses a floating control module to control the gate voltage of the rectifier power transistor and discharge the gate charge of the rectifier power transistor, clamping the gate-source voltage of the rectifier power transistor to within the withstand voltage value. This can prevent the floating ground potential from being pulled too high due to excessive instantaneous current, which could cause circuit logic errors.

[0021] Furthermore, by using an inverter to provide a gate voltage to the gate of the rectifier power transistor, the gate voltage amplitude of the PMOS rectifier power transistor can be increased, ensuring full turn-on and simplifying the structure. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the synchronous boost circuit described in one embodiment of this application.

[0024] Figure 2This is a schematic diagram of the structure of the floating control module in one embodiment of this application.

[0025] Figure 3 This is a schematic diagram of the circuit structure of the floating control module in one embodiment of this application. Detailed Implementation

[0026] The synchronous boost circuit, floating gate voltage control method, chip, and electronic device will be further described below with reference to the accompanying drawings and embodiments.

[0027] Please see Figure 1 This is a schematic diagram of the synchronous boost circuit described in an embodiment of the present invention.

[0028] In this embodiment, the synchronous boost circuit includes a power output module, which includes a rectifier power transistor MP0. One end of the rectifier power transistor MP0 is coupled to the input voltage terminal of the power output module to receive the input voltage VIN, and the other end is coupled to the output voltage terminal of the power output module to output the voltage VOUT.

[0029] The synchronous boost circuit further includes a floating control module 100, which uses the output voltage VOUT as the working power supply and the floating ground power supply FGND as the ground terminal signal to clamp the gate-source voltage of the rectifier power transistor MP0 to within the withstand voltage value.

[0030] In this embodiment, the rectifier power transistor MP0 is a PMOS power transistor; the power output module further includes an inductor L, which is connected in series between the drain of the rectifier power transistor MP0 and the input voltage terminal, and the source of the rectifier power transistor MP0 is connected to the output voltage terminal.

[0031] The floating control module 100 is connected at one end to the source of the rectifier power transistor MP0 to obtain the output voltage VOUT output from the source of the rectifier power transistor MP0, and at the other end to the floating ground power supply FGND. The output terminal is connected to the gate of the rectifier power transistor MP0 to perform floating control on the gate voltage of the PMOS power transistor and clamp the gate-source voltage of the rectifier power transistor MP0 to within the withstand voltage value.

[0032] Please refer to Figure 2This is a schematic diagram of a synchronous boost circuit according to another embodiment of this application. In this embodiment, the floating control module includes a drive unit 102, which includes: an eleventh inverter INV11 for acquiring a drive signal and inverting the drive signal; a first transistor MP1, with its source connected to the source of the rectifier power transistor MP0 and its gate connected to the output of the eleventh inverter INV11; a first inverter INV1 and a second inverter INV2 connected in series, with the input of the first inverter INV1 for acquiring the drive signal and its output connected to the second inverter INV2, and the output of the second inverter INV2 connected to the gate of the rectifier power transistor MP0; and a second transistor MP2 with its drain grounded, its gate for acquiring the drive signal, and its source connected to the drain of the first transistor MP1. The first inverter INV1 and the second inverter INV2 also use a floating ground power supply as the ground potential, and the low level output is the potential of the ground power supply, i.e., the floating ground potential.

[0033] The driving unit 102 is used to control the on / off state of the first transistor MP1 and the second transistor MP2 according to the driving signal. Specifically, the first transistor MP1, the second transistor MP2, and the rectifier power transistor MP0 are all turned on when the gate voltage is low. Therefore, for the rectifier power transistor MP0 to be turned on, only one of the first transistor MP1 and the second transistor MP2 can be turned on.

[0034] In this embodiment, the floating control module 100 further includes a level conversion unit 101, which is used to receive a drive signal and convert the level value of the drive signal to the voltage range between the output voltage VOUT and the floating ground power supply FGND, so as to match the operating voltage domain of other devices in the floating control module 100.

[0035] The level conversion unit can be directly implemented using a level shifter.

[0036] In fact, if the level of the drive signal itself matches the operating voltage domain of the floating control module 100, the level conversion unit can be omitted, which simplifies the structure and reduces power consumption.

[0037] When the drive signal is low, the level conversion unit 101 outputs a low level, which is then output as a low level (floating ground potential) to the rectifier power transistor MP0 after passing through the first inverter INV1 and the second inverter INV2. At this time, the rectifier power transistor MP0 is in the conducting state. At the same time, the eleventh inverter INV11 outputs a high level signal, and the first transistor MP1 is in the off state.

[0038] When the drive signal flips from high to low, a low level is output via level conversion unit 101. The first transistor MP1 is turned off by the high level output of the eleventh inverter INV11, and the gate of the second transistor MP2 flips low, turning on and discharging the gate of the rectifier power transistor MP0 to ground. Subsequently, the first inverter INV1 and the second inverter INV2 drive the gate voltage of the rectifier power transistor MP0 to a low level (floating ground level), and turn off the second transistor MP2 when its gate-source voltage falls below a threshold. Throughout this process, the gate charge of the rectifier power transistor MP0 is mainly discharged to ground by the second transistor MP2, thereby mitigating the influence of the second inverter INV2 on the floating ground FGND. By discharging current through the second transistor MP2, the potential of the floating ground power supply is prevented from being pulled high, thus ensuring the accuracy of the circuit logic. Furthermore, the gate of the rectifier power transistor MP0 is clamped to the floating ground, achieving a gate clamping effect for the rectifier power transistor MP0.

[0039] In this embodiment, a larger second transistor MP2 and smaller inverters INV1 and INV2 can be used to drive the gate potential of the rectifier power transistor MP0 to the floating ground potential. A large instantaneous current flows through the second transistor MP2. When MP2 is turned off, the smaller inverters INV1 and INV2 restore the gate potential of the rectifier power transistor MP0 to the floating ground potential.

[0040] It should be noted that since the rectifier power transistor MP0 requires a large drive current, the first transistor MP1 and the second transistor MP2 are both large in size. Floating gate voltage control is also required for these MOSFETs to prevent excessive gate-source voltage.

[0041] In some embodiments, the first inverter INV1 and the second inverter INV2 are CMOS inverters, which are formed by interconnecting the drain and source of PMOS and NMOS transistors. Therefore, in some embodiments, a floating control unit can also be provided for the first inverter INV1 and the second inverter INV2 to provide floating gate voltage protection for the gates of these inverters.

[0042] Please see Figure 3 This is a schematic diagram of the circuit structure of the floating control module 100 in one embodiment of this application.

[0043] exist Figure 3 In the illustrated embodiment, the floating control module 100 further includes a floating control unit for connecting to the first transistor MP1 and / or the second transistor MP2, and for performing floating gate voltage control on the first transistor MP1 and / or the second transistor MP2.

[0044] The floating control module 100 includes a first floating control unit 310. The input terminal of the first floating control unit 310 is connected to the output terminal of the eleventh inverter INV11, and the output terminal is connected to the gate of the first transistor MP1. It is used to float control the gate voltage of the first transistor MP1 and clamp the gate-source voltage of the first transistor MP1 to within the withstand voltage value of the first transistor MP1.

[0045] The floating control module 100 further includes a second floating control unit 320. The input terminal of the second floating control unit 320 is connected to a drive signal, and the output terminal is connected to the input terminal of the first inverter INV1 and the gate of the second transistor MP2, so as to perform floating control on the gate voltage of the second transistor MP2 and clamp the gate-source voltage of the second transistor MP2 to within the withstand voltage value of the second transistor MP2.

[0046] In this embodiment, the input terminals of the first floating control unit 310 and the second floating control unit 320 are both connected to the output terminal of the level conversion unit 101 to receive the drive signal after level conversion.

[0047] Furthermore, the second floating control unit 320 and the first floating control unit 310 can also provide floating ground potentials for the first transistor MP1, the second transistor MP2, the first inverter INV1, and the second inverter INV2 to prevent the gate-source voltage from being too high when the source voltage of the first transistor MP1, the second transistor MP2, the first inverter INV1, and the second inverter INV2 is too high, which could cause the corresponding MOS transistors to break down.

[0048] The first floating control unit includes a first control subunit; the first control subunit includes: a first inverter group, including an even number of inverters connected in series; a first release transistor, the source of which is connected to the output terminal of the first inverter group, the gate of which is connected to the input terminal of the first inverter group, and the drain of which is grounded; the inverters in the first inverter group are composed of MOS transistors, and the size of the MOS transistors is smaller than the size of the first release transistor.

[0049] In this embodiment, the first floating control unit includes several first control subunits, specifically first control subunits 311, 312, and 313. The inverter groups of each first control subunit are connected in series to form a first inverter group series path. The input terminal of the first inverter group series path is connected to a drive signal, and the output terminal is connected to the gate of the first transistor MP1. First control subunit 311 includes two series-connected ninth inverters INV9 and INV10, and a seventh transistor MP7. The gate of the seventh transistor MP7 is connected to the input terminal of the ninth inverter INV9, its drain is grounded, and its source is connected to the output terminal of the inverter INV10. Similarly, first control subunit 313 includes two series-connected seventh inverters INV7 and INV8, and a fifth transistor MP5. The seventh inverters INV7 to the tenth inverter INV10 are connected in series to form a first inverter path, used to output the drive signal buffered by the inverters. In this embodiment, the eighth inverter INV8 and the ninth inverter INV9 are also multiplexed to form the first floating control unit 312 together with the sixth transistor MP6. In this embodiment, the fifth transistor MP5, the sixth transistor MP6, and the seventh transistor MP7 are all PMOS transistors.

[0050] Within each first floating control unit, in the circuit path direction from the drive signal to the rectifier power transistor, the preceding first control subunit can quickly release the accumulated charge on the gate of the inverter and the first release transistor in the following first control subunit, thereby enhancing the driving capability. The output terminal of the tenth inverter INV10 is connected to the gate of the first transistor MP1. The first control subunit 311 is used to release the gate charge of the first transistor MP1, specifically by discharging the accumulated charge on the gate of the first transistor MP1 through the seventh transistor MP7.

[0051] Similarly, the first control subunit 313 is used to discharge the gate charge of the seventh transistor MP7, specifically through the fifth transistor MP5 for current discharge. The gate charge of the seventh transistor MP7 is grounded via MP5 and rapidly discharged to a threshold voltage one MP5 higher than the floating ground power supply. The voltage output by the eighth inverter INV8 provides the gate voltage for the seventh transistor MP7, further lowering the gate voltage of the seventh transistor MP7 to prevent insufficient turn-on of the seventh transistor MP7, which would cause insufficient gate-source voltage of the first transistor MP1 and thus insufficient turn-on.

[0052] The output of the first control subunit 312 is connected to the tenth inverter INV10 to quickly discharge the gate charge of the tenth inverter INV10, thereby rapidly driving the tenth inverter INV10. The input charge in the tenth inverter INV10 is grounded through the sixth transistor MP6 and quickly discharged to a threshold voltage one MP6 transistor higher than the floating ground potential. The output of the ninth inverter INV9 provides the gate voltage for the PMOS transistor in the tenth inverter INV10, further pulling down the gate voltage of the seventh transistor MP7 to prevent insufficient input logic level of the tenth inverter INV10.

[0053] Optionally, as the driving capability requirements of each level of control subunit gradually increase, the sizes of MP5, MP6, and MP7 gradually increase, and the size of MP7 can also be smaller than the size of the first transistor MP1.

[0054] Optionally, the size of the NMOS transistor in each inverter of the first floating control unit 310 is smaller than the size of each first release transistor.

[0055] The second floating control unit 320 includes a second control subunit; the second control subunit includes: a second inverter group, including an even number of inverters connected in series; a second release transistor, the source of which is connected to the output terminal of the second inverter group, the gate of which is connected to the input terminal of the second inverter group, and the drain of which is grounded; the inverters in the second inverter group are composed of MOS transistors, and the size of the MOS transistors is smaller than the size of the second release transistor.

[0056] In this embodiment, the second floating control unit 320 includes several second control subunits, specifically first control subunits 321, 322, and 323. The inverter groups of each second control subunit are connected in series to form a second inverter group series path. The input terminal of the second inverter group series path is connected to the drive signal, and the output terminal is connected to the gate of the second transistor MP2. Second control subunit 321 includes two series-connected third inverters INV3 and INV4, and a third transistor MP3. The gate of the third transistor MP3 is connected to the input terminal of the third inverter INV3, its drain is grounded, and its source is connected to the output terminal of the fourth inverter INV4. Similarly, second control subunit 323 includes two series-connected fifth inverters INV5 and INV6, and a fourth transistor MP4. Inverters INV5, INV6, INV3, and INV4 are connected in series to form a second inverter path, used to output the drive signal buffered by the inverters. In this embodiment, the sixth inverter INV6 and the third inverter INV3 are also multiplexed to form a second floating control unit 322 together with the eighth transistor MP8. In this embodiment, the third transistor MP3, the fourth transistor MP4, and the eighth transistor MP8, which serve as the second release transistors, are all PMOS transistors.

[0057] The third transistor MP3 is used to release the gate charge of the second transistor MP2, and the gate charge of the third transistor MP3 is released to ground through the second control subunit of the previous stage.

[0058] The size of the third transistor MP3 is smaller than the size of the second transistor MP2. The size of the fourth transistor MP4 is smaller than the size of the third transistor MP3, and the size of the MOS transistors in the fifth inverter INV5 and the sixth inverter INV6 is smaller than the size of the fourth transistor MP4.

[0059] The gate charge of the third transistor MP3 is grounded by the fourth transistor MP4 and is quickly discharged to a threshold voltage of one MP4 transistor higher than the floating ground power supply. The voltage output by the sixth inverter INV6 provides the gate voltage of the third transistor MP3, further pulling down the gate voltage of MP3 to prevent the gate-source voltage of the third transistor MP3 from being insufficient and not fully turned on.

[0060] exist Figure 3In the illustrated embodiment, a second control subunit 322 is also configured for the fourth inverter INV4 to quickly drive the input terminal of the fourth inverter INV4 to ground. The second control subunit 322 includes a multiplexed sixth inverter INV6, a third inverter INV3, and an eighth transistor MP8. The input terminal of the sixth inverter INV6 serves as the input terminal of the second inverter group, used to acquire the output signal of the fifth inverter INV5. The output terminal of the third inverter INV3 serves as the output terminal of the second inverter group and is connected to the input terminal of the fourth inverter INV4. The source of the eighth transistor MP8 is connected to the input terminal of the fourth inverter INV4, the gate is connected to the input terminal of the sixth inverter INV6, and the drain is grounded.

[0061] The size of the eighth transistor MP8 is smaller than the size of the MOS transistor in the fourth inverter INV4, and the sizes of the MOS transistors in the sixth inverter INV6 and the third inverter INV3 are also smaller than the size of the eighth transistor MP8.

[0062] The charge at the input terminal of the fourth inverter INV4 is grounded by the eighth transistor MP8 and is quickly discharged to a threshold voltage of one MP8 transistor higher than the floating ground power supply. The output terminal of the third inverter INV3 provides the gate voltage to the input terminal of the fourth inverter INV4, further pulling down the input terminal voltage of the fourth inverter INV4.

[0063] It should be noted that both the first control subunit 313 and the second control subunit 322 discharge the corresponding PMOS transistor to ground only when the drive signal is high. When the drive signal is low, the release transistors in the first control subunit 313 and the second control subunit 322 are turned off.

[0064] Embodiments of this application also provide a floating gate voltage control method, applied to the synchronous boost circuit described in any of the above embodiments, comprising the following steps:

[0065] The gate voltage of the rectifier power transistor is controlled by floating.

[0066] The gate charge of the rectifier power transistor is discharged to clamp the gate-source voltage of the rectifier power transistor to within the withstand voltage value.

[0067] Embodiments of this application also provide a chip having a synchronous boost circuit as described in any of the above embodiments.

[0068] The embodiments of this application also provide an electronic device, including the synchronous boost circuit or the chip described in any of the above embodiments.

[0069] The synchronous boost circuit, floating gate voltage control method, chip, and electronic device in this application use a floating control module to control the gate voltage of the rectifier power transistor and discharge the gate charge of the rectifier power transistor, clamping the gate-source voltage of the rectifier power transistor within its withstand voltage value. This prevents the floating ground potential from being pulled too high due to excessive instantaneous current, which could cause circuit logic errors. Furthermore, by using an inverter to provide a gate voltage to the gate of the rectifier power transistor, the gate voltage amplitude of the PMOS rectifier power transistor can be increased, ensuring full turn-on and simplifying the structure.

[0070] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A synchronous boost circuit, characterized in that, include: A power output module, the power output module including a rectifier power transistor, one end of the rectifier power transistor being coupled to the input voltage terminal of the power output module, and the other end being coupled to the output voltage terminal of the power output module; A floating control module, which uses the output voltage as the working power supply and the floating ground power supply as the ground terminal signal, is used to control the floating of the gate voltage of the rectifier power transistor, discharge the gate charge of the rectifier power transistor, and clamp the gate-source voltage of the rectifier power transistor to within the withstand voltage value. The floating control module includes a drive unit, the drive unit comprising: The eleventh inverter is used to acquire the drive signal and invert the drive signal. The first transistor has its source connected to the source of the rectifier power transistor and its gate connected to the output of the eleventh inverter. A first inverter and a second inverter are connected in series. The input terminal of the first inverter is used to obtain the drive signal, and the output terminal is connected to the second inverter. The output terminal of the second inverter is connected to the gate of the rectifier power transistor. The second transistor has its drain grounded, its gate used to acquire the drive signal, and its source connected to the drain of the first transistor.

2. The synchronous boost circuit according to claim 1, characterized in that, The floating control module further includes a second floating control unit. The input terminal of the second floating control unit is connected to the drive signal, and the output terminal is connected to the input terminal of the first inverter and the gate of the second transistor, so as to perform floating control on the gate voltage of the second transistor and clamp the gate-source voltage of the second transistor to within the withstand voltage value of the second transistor.

3. The synchronous boost circuit according to claim 2, characterized in that, The second floating control unit includes a second control subunit; the second control subunit includes: The second inverter group consists of an even number of inverters connected in series. The source of the second release transistor is connected to the output terminal of the second inverter group, the gate of the second release transistor is connected to the input terminal of the second inverter group, and the drain is grounded. The inverters in the second inverter group are composed of MOS transistors, and the size of the MOS transistors is smaller than the size of the second release transistor.

4. The synchronous boost circuit according to claim 3, characterized in that, The second floating control unit includes several second control subunits. The inverter groups of each second control subunit are connected in series to form a second inverter group series path. The input terminal of the second inverter group series path is used to connect to the drive signal, and the output terminal is connected to the gate of the second transistor.

5. The synchronous boost circuit according to claim 2, characterized in that, The floating control module further includes a first floating control unit. The input terminal of the first floating control unit is connected to the output terminal of the eleventh inverter, and the output terminal is connected to the gate of the first transistor. It is used to perform floating control on the gate voltage of the first transistor and clamp the gate-source voltage of the first transistor to within the withstand voltage value of the first transistor.

6. The synchronous boost circuit according to claim 5, characterized in that, The first floating control unit includes a first control subunit; the first control subunit includes: The first inverter group consists of an even number of inverters connected in series. The first release transistor has its source connected to the output terminal of the first inverter group, its gate connected to the input terminal of the first inverter group, and its drain grounded. The inverters in the first inverter group are composed of MOS transistors, and the size of the MOS transistors is smaller than the size of the first release transistor.

7. The synchronous boost circuit according to claim 6, characterized in that, The first floating control unit includes several first control subunits. The first inverter groups of each first control subunit are connected in series to form a first inverter group series path. The input terminal of the first inverter group series path is used to connect to the drive signal, and the output terminal is connected to the gate of the first transistor.

8. The synchronous boost circuit according to claim 5, characterized in that, The floating control module also includes: A level conversion unit is used to receive a drive signal, convert the level value of the drive signal to a voltage range between the output voltage and the floating ground power supply, and output it to the first floating control unit and the second floating control unit.

9. The synchronous boost circuit according to claim 1, characterized in that, The rectifier power transistor is a PMOS power transistor; the power output module also includes an inductor connected in series between the drain of the PMOS power transistor and the input voltage terminal, and the source of the PMOS power transistor is connected to the output voltage terminal.

10. A floating gate voltage control method, characterized in that, The synchronous boost circuit applied to any one of claims 1 to 9 comprises the following steps: The gate voltage of the rectifier power transistor is controlled by floating. The gate charge of the rectifier power transistor is discharged to clamp the gate-source voltage of the rectifier power transistor to within the withstand voltage value.

11. A chip, characterized in that, Includes the synchronous boost circuit as described in any one of claims 1 to 9.

12. An electronic device, characterized in that, Includes the synchronous boost circuit as described in any one of claims 1 to 9 or the chip as described in claim 11.

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