A signal transmission circuit, a circuit board and an electronic device

Abstract

Embodiments of the present application provide a signal transmission circuit, a circuit board and an electronic device. The signal transmission circuit comprises: a first circuit board, a second circuit board, a first connector, at least one first cable, and at least one second connector; the first connector is arranged on the first circuit board, the at least one second connector is arranged on the second circuit board, and the at least one second connector is connected with a PCIE device on the second circuit board; one end of each first cable is connected with the first connector, and the other end of each first cable is connected with a corresponding second connector; each first cable is used for transmitting a PCIE signal between a controller arranged on the first circuit board and a PCIE device connected with the corresponding second connector. By directly connecting the cable with the connector of the first circuit board and the connector of each PCIE device on the second circuit board, the transmission loss of the high-speed signal between the controller and the PCIE device can be effectively reduced, and the design flexibility of the circuit board is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, and in particular to a signal transmission circuit, a circuit board and an electronic device. BACKGROUND

[0002] With the rapid development of communication, computer and other technologies, the speed of high-speed serial computer expansion bus (peripheral component interconnect express, PCIE) signals has risen to PCIE5.0 version, and will continue to rise to 6.0, 7.0 and other higher versions in the future, which will make the requirement of transmission loss of the link higher and higher.

[0003] The PCIE signal is usually transmitted from the source (such as a controller) to the target connector through the circuit board. Taking the U.2 connector connected to the PCIE device (such as a hard disk) as an example, in the current circuit board design, the U.2 connector is usually welded on the backplane of the PCIE device, and high-speed connectors are welded on the mainboard and the backplane. The backplane of the PCIE device connects the high-speed connectors on the board to the U.2 connector through the PCB trace. When the PCIE signal and other high-speed signals between the controller and the PCIE device are transmitted on the PCIE device, the high-speed signals need to be transmitted to the U.2 connector through the PCB trace on the backplane of the PCIE device. However, the transmission through the PCB trace of the PCIE device will cause large transmission loss of the high-speed signals, and thus the layout design of the circuit board is limited and not flexible enough.

[0004] Therefore, how to reduce the transmission loss of high-speed signals between the controller and the PCIE device in the circuit board and improve the design flexibility of the circuit board has become a problem to be solved. SUMMARY

[0005] The embodiments of the present application provide a signal transmission circuit, a circuit board and an electronic device, which can effectively reduce the transmission loss of high-speed signals between the controller and the PCIE device in the circuit board and improve the design flexibility of the circuit board.

[0006] In a first aspect, the embodiments of the present application provide a signal transmission circuit, which comprises a first circuit board, a second circuit board, a first connector, at least one first cable and at least one second connector. The first connector is arranged on the first circuit board, the at least one second connector is arranged on the second circuit board, and the at least one second connector is connected to a PCIE device on the second circuit board.

[0007] One end of each first cable is connected to the first connector, and the other end of each first cable is connected to a corresponding second connector.

[0008] Each of the first cables is configured to transmit high-speed serial computer expansion bus (PCIE) signals between the controller disposed on the first circuit board and a corresponding second connector.

[0009] Optionally, the first cables include high-speed signal lines and low-speed signal lines.

[0010] The high-speed signal lines of each of the first cables are configured to transmit PCIE signals between the controller and the PCIE device connected to the corresponding second connector via high-speed signal pins of the first connector, high-speed signal pins of the corresponding second connector, and high-speed signal pins of the PCIE device connected to the corresponding second connector.

[0011] The low-speed signal lines of each of the first cables are configured to transmit low-speed signals via low-speed signal pins of the first connector, low-speed signal pins of the corresponding second connector, and low-speed signal pins of the PCIE device connected to the corresponding second connector.

[0012] Optionally, the low-speed signals include first bus signals, and the second circuit board further includes a first signal processing circuit.

[0013] The first bus signals output by the low-speed signal pins of the first connector are input to the first signal processing circuit via the low-speed signal lines of the first cables corresponding to a first target connector and the low-speed signal pins of the first target connector, the first target connector being any one of the at least one second connector.

[0014] The first signal processing circuit is configured to generate multiple bus signals from the first bus signals and input the multiple bus signals to the low-speed signal pins of each of the second connectors, respectively.

[0015] Optionally, the low-speed signals further include second bus signals, and the second circuit board further includes a second signal processing circuit.

[0016] The second bus signals output by the low-speed signal pins of the first connector are input to the second signal processing circuit via the low-speed signal lines of the first cables corresponding to a second target connector and the low-speed signal pins of the second target connector, the second target connector being any one of the at least one second connector, and the second target connector being different from the first target connector.

[0017] The second signal processing circuit is configured to generate multiple status indication signals from the second bus signals, the multiple status indication signals being used to indicate operating states of the PCIE devices connected to each of the second connectors.

[0018] Optionally, the low-speed signals further comprise PCIE device slot detection signals, and the second circuit board further comprises a plurality of third signal processing circuits, wherein:

[0019] Each of the third signal processing circuits is connected with a corresponding second connector.

[0020] Each of the third signal processing circuits is configured to generate a PCIE device slot detection signal of the corresponding second connector.

[0021] Each of the second connectors is configured to transmit the PCIE device slot detection signal of the corresponding second connector to a low-speed signal pin of the first connector through a low-speed signal line of a corresponding first cable, and the PCIE device slot detection signal is used to indicate whether a mounting slot of a PCIE device connected with the corresponding second connector is incorrect.

[0022] Optionally, the low-speed signals further comprise connector in-place signals, and wherein:

[0023] A third target connector transmits a connector in-place signal to a fourth target connector through a low-speed signal pin connected with the fourth target connector, and the third target connector and the fourth target connector are different connectors in the at least one second connector.

[0024] The low-speed signal pin of the fourth target connector is configured to transmit the connector in-place signal of the third target connector to the first connector through a low-speed signal line of a corresponding first cable of the fourth target connector, or to transmit the connector in-place signal of the third target connector and a connector in-place signal of the fourth target connector to the first connector.

[0025] Optionally, the low-speed signals further comprise reset signals, and wherein:

[0026] The low-speed signal pin of the first connector is configured to transmit a reset signal to a corresponding second connector through a low-speed signal line of each of the first cables.

[0027] Optionally, the low-speed signals further comprise PCIE device type signals, and wherein:

[0028] The low-speed signal pin of each of the second connectors is configured to transmit a PCIE device type signal to the first connector through a low-speed signal line of a corresponding first cable.

[0029] Optionally, the first cables further comprise power signal lines, and wherein:

[0030] A power signal line of each of the first cables is configured to transmit a power signal to a PCIE device connected to the corresponding second connector via a power pin of the first connector, a power pin of the corresponding second connector.

[0031] Optionally, each of the first cables is connected to the corresponding second connector by welding.

[0032] Optionally, each of the first cables is connected to the first connector in a pluggable manner.

[0033] Optionally, each of the second connectors is fixedly installed on the second circuit board by screws.

[0034] Optionally, the second connector includes a U.2 connector.

[0035] In a second aspect, an embodiment of the present application provides a circuit board, including at least one first cable and at least one second connector, wherein:

[0036] One end of each of the first cables is connected to the corresponding second connector, and the other end of each of the first cables includes a pluggable interface configured to connect to a first connector disposed on another circuit board.

[0037] Each of the first cables is configured to transmit a high-speed serial computer expansion bus (PCIE) signal between a PCIE device connected to the corresponding second connector and a controller on the other circuit board.

[0038] In a third aspect, an embodiment of the present application provides an electronic device including the signal transmission circuit of the first aspect or the circuit board of the second aspect.

[0039] The signal transmission circuit provided by the embodiment of the application comprises: a first connector, at least one first cable, and at least one second connector; the first connector is arranged on a first circuit board, the at least one second connector is arranged on a second circuit board, and the at least one second connector is connected with a PCIE device on the second circuit board, which can be that each second connector is connected with one PCIE device. One end of each first cable is connected with the first connector, and the other end is connected with the corresponding second connector. Each first cable is used for transmitting a high-speed serial computer expansion bus PCIE signal between a controller arranged on the first circuit board and the PCIE device connected with the corresponding second connector. The connector of the first circuit board and the connector of each PCIE device on the second circuit board are directly connected through the corresponding cable, and the PCIE signal between the controller on the first circuit board and each PCIE device on the second circuit board is transmitted through the cable, so that the transmission distance of the PCIE high-speed signal in the PCB wiring of the circuit board is shortened, thereby effectively reducing the transmission loss of the high-speed signal between the controller and each PCIE device, and the connector of the PCIE device on the first circuit board and the second circuit board is directly connected through the cable, and the relative position of the PCIE device and the controller can be flexibly designed, thereby improving the design flexibility of the circuit board. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0041] Figure 1 is a structural schematic diagram of a signal transmission circuit provided by the embodiment of the present application;

[0042] Figure 2a is a structural schematic diagram of a second circuit board provided by the embodiment of the present application;

[0043] Figure 2b is a structural schematic diagram of another second circuit board provided by the embodiment of the present application;

[0044] Figure 3 is a structural schematic diagram of another signal transmission circuit provided by the embodiment of the present application;

[0045] Figure 4 is a structural schematic diagram of another signal transmission circuit provided by the embodiment of the present application;

[0046] Figure 5 is a structural schematic diagram of another signal transmission circuit provided by the embodiment of the present application;

[0047] Figure 6 is a structural schematic diagram of another signal transmission circuit provided by an embodiment of the present application;

[0048] Figure 7 is a structural schematic diagram of another signal transmission circuit provided by an embodiment of the present application;

[0049] Figure 8 is a structural schematic diagram of a circuit board provided by an embodiment of the present application;

[0050] Figure 9 is a structural schematic diagram of an electronic device provided by an embodiment of the present application;

[0051] Figure 10 is a structural schematic diagram of another electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to better understand the technical solutions provided by the embodiments of the present application, the related embodiments of the present application are described below.

[0053] Please refer to Figure 1 is a structural schematic diagram of a signal transmission circuit provided by an embodiment of the present application, which comprises a first circuit board 10, a second circuit board 11, a first connector 102, at least one first cable 12, and at least one second connector 111. The first connector 102 is arranged on the first circuit board 10, the at least one second connector 111 is arranged on the second circuit board 11, and the at least one second connector 111 is connected with a PCIE device 112 on the second circuit board 11.

[0054] One end of each first cable 12 is connected with the first connector 102, and the other end is connected with a corresponding second connector 111.

[0055] Each first cable 12 is used for transmitting a high-speed serial computer expansion bus PCIE signal between a controller 101 arranged on the first circuit board 10 and a PCIE device 112 connected with the corresponding second connector 111.

[0056] The first connector 102 can be used for transmitting at least a high-speed signal, such as a PCIE signal.

[0057] In some embodiments, the first circuit board 10 can be a mainboard in a computing device, and the second circuit board 11 can be a backboard in the computing device.

[0058] In some possible embodiments, the controller 101 can include a processor, such as a central processing unit (CPU), a digital signal processor (DSP), or the like. The first connector 102 can be a full-function high-speed connector, such as a UBCDD connector, which can simultaneously provide high-speed signals, low-speed signals, and power signals; or the first connector 102 can be a non-full-function high-speed connector, such as an MCIO connector or a UBC connector, which can provide high-speed signals and low-speed signals, and in this case, a power connector can be used to provide power signals.

[0059] In some possible embodiments, the PCIE device 112 can be a hard disk, and the second circuit board 11 can be provided with one or more second connectors 111, each of which is connected to a hard disk.

[0060] In some possible embodiments, the second connector can be a U.2 connector, which can be used to connect a hard disk.

[0061] In some possible embodiments, each first cable 12 can be connected to the corresponding second connector 111 by welding, for example, each signal line in the first cable 12 can be welded to the corresponding pin of the second connector 111, such as each high-speed signal line in the first cable 12 can be welded to the corresponding high-speed signal pin of the second connector 111, and each low-speed signal line in the first cable 12 can be welded to the corresponding low-speed signal pin of the second connector 111.

[0062] In some possible embodiments, each first cable 12 can be connected to the first connector 102 by plugging. Specifically, one end of each first cable 12 includes a pluggable interface, and each first cable 12 is connected to the pluggable interface of the first connector 102 through the pluggable interface, such as the pluggable interface of the first cable 12 is a plug, and the pluggable interface of the first connector 102 is a socket; or the pluggable interface of the first cable 12 is a socket, and the pluggable interface of the first connector 102 is a plug, which is not limited in the present application. The first cable 12 is connected to the first connector 102 by plugging, so that the second circuit board and the first cable can be used as a flexible replacement circuit module, and the circuit module connected to the first circuit board can be replaced flexibly according to actual business needs.

[0063] In some possible embodiments, each first cable 12 can be connected to the first connector 102 and the second connector 111 by welding.

[0064] In some possible implementation manners, the controller 101 and the first connector 102 can be connected through the PCB traces on the first circuit board 10 or through a cable.

[0065] It can be seen that, in the embodiment of the application, the connector of the first circuit board can be directly connected with the connector of each PCIE device on the second circuit board through at least one cable, and the PCIE signals between the controller and the corresponding PCIE device are transmitted through the cable, so that the transmission distance of the PCIE high-speed signals in the PCB traces of the second circuit board is shortened, thereby effectively reducing the transmission loss of the high-speed signals between the controller and each PCIE device, and the connectors of the PCIE devices on the first circuit board and the second circuit board are directly connected through the cable, so that the relative positions of the PCIE devices and the controller can be flexibly designed, thereby improving the design flexibility of the circuit board.

[0066] In addition, since the material of the second circuit board also affects the transmission loss of the high-speed signals in the PCB traces, the embodiment of the application saves the high-speed signal transmission in the PCB traces of the second circuit board through the cable, greatly reduces the transmission loss of the high-speed signals, and therefore, under the requirement of transmission quality, the second circuit board can select a material with lower cost, thereby reducing the product cost.

[0067] In some possible implementation manners, the first cable 12 includes a high-speed signal line and a low-speed signal line.

[0068] The high-speed signal line of each first cable 12 is used to transmit high-speed signals between the controller 101 and the PCIE device 112 connected to the corresponding second connector 111 through the high-speed signal pins of the first connector 102, the high-speed signal pins of the corresponding second connector 111, and the high-speed signal pins of the PCIE device 112 connected to the corresponding second connector 111, and the high-speed signals can include PCIE signals and clock signals.

[0069] The low-speed signal line of each first cable 12 is used to transmit low-speed signals through the low-speed signal pins of the first connector 102, the low-speed signal pins of the corresponding second connector 111, and the low-speed signal pins of the PCIE device 112 connected to the corresponding second connector 111.

[0070] The signal transmission circuit provided by the embodiment of the present application can connect the high-speed signal line of the cable with the high-speed signal pin of the first connector of the first circuit board and the high-speed signal pin of the corresponding second connector on the second circuit board, and connect the low-speed signal line of the cable with the low-speed signal pin of the first connector of the first circuit board and the low-speed signal pin of the corresponding second connector on the second circuit board, so that the high-speed signal and the low-speed signal can be efficiently transmitted between the controller and each PCIE device, the transmission loss of the high-speed signal is effectively reduced, and thus the working requirements of each PCIE device on the second circuit board of the PCIE device are met.

[0071] In some possible embodiments, a structural schematic diagram of the second circuit board 11 can be as shown in Figure 2a Figure 2a It can be understood as a top view of the second circuit board 11. The second circuit board 11 further includes fixed screw holes 113, and each second connector 111 includes elastic pins 1111, so that each second connector 111 can be fixedly installed on the second circuit board 11 by means of the screw and the fixed screw hole 113.

[0072] After each second connector 111 is locked with the second circuit board 11 by using the screw, the elastic pin 1111 can be tightly attached to the contact of the second circuit board 11, for example, the elastic pin 1111 can be tightly connected to the contact on the second circuit board 11 by means of pressure welding or riveting; the elastic pin 1111 can guide the low-speed signal (such as bus signal, device slot detection signal, etc.) that needs to be processed on the second circuit board 11 into the second circuit board 11 for corresponding processing through the connected contact.

[0073] In some possible embodiments, the specific way in which the second connector 111 is fixedly installed on the second circuit board 11 can be as shown in Figure 2b Figure 2b It can be understood as a side view of the second circuit board 11. The second circuit board 11 is provided with screw holes 113, the second connector 111 can be fixed on the second circuit board 11 by screwing the screw 114 with the screw hole 113, and the elastic pin 1111 of the second connector 111 can also be tightly attached to the contact of the second circuit board 11.

[0074] It should be noted that the second circuit board can also not be used in the case where the second circuit board does not need to process the low-speed signal, but the second connector 111 can be directly fixed on the structural member, thereby further saving the cost.

[0075] In some possible embodiments, taking four second connectors 111 as an example, a structural schematic diagram of the corresponding signal transmission circuit can be as shown in Figure 3 ​​As shown, the first connector 102 is connected with four second connectors 111 through four first cables 12 respectively, and can transmit high-speed signals and low-speed signals to the corresponding PCIE devices 112 through the first cables 12.

[0076] In some possible embodiments, on the basis of Figure 3 the first connector 102 is a UBCDD connector and the second connector 111 is a U.2 connector, the UBCDD connector contains 30 low-speed signal pins, and by leading part of the low-speed signals (such as bus signals, device slot detection signals, etc.) into the second circuit board 11 for corresponding processing, the required low-speed signals can be provided to multiple U.2 connectors simultaneously to meet the working requirements of multiple PCIE devices (such as hard disks). Taking the PCIE device as a hard disk as an example, as shown in Figure 4 the first bus signal is an I2C bus signal for a baseboard management controller (BMC), including BMC I2C SDA and BMC I2C SCL two signals, the two signals are used for transmitting low-speed data between the controller and the PCIE device, I2C SDA refers to I2C serial data line (Serial Data, SDA), and I2C SCL refers to I2C serial clock line (Serial Clock Line, SCL), wherein:

[0077] The first bus signal output by the low-speed signal pin of the first connector 102 is input into the first signal processing circuit 115 through the low-speed signal line of the first cable 12 corresponding to the first target connector and the elastic pin 1111 of the first target connector, the first target connector is any one of the at least one second connector, and specifically can be any one of the four U.2 connectors in Figure 4 Figure 4 Taking the first U.2 connector from top to bottom as an example.

[0078] The first signal processing circuit 115 is configured to generate multiple bus signals according to the first bus signal, and input the multiple bus signals into the low-speed signal pins of each second connector 111 through the PCB traces on the second circuit board 11 respectively, and the expansion of the bus signals can meet the requirements of multiple PCIE devices on the I2C bus signal of the BMC.

[0079] wherein, Figure 4 ​In the embodiment, the first signal processing circuit 115 outputs 8 bus signals, including: BMC I2C SDA_0, BMC I2C SCL_0; BMC I2C SDA_1, BMC I2C SCL_1; BMC I2C SDA_2, BMC I2C SCL_2; BMC I2C SDA_3, BMC I2C SCL_3. Every 2 bus signals are input to the low-speed signal pins of the corresponding second connector 111 through the PCB traces on the second circuit board. Taking the first U.2 connector as an example, the first signal processing circuit 115 outputs two bus signals BMC I2C SDA_0 and BMC I2C SCL_0, which are connected to the two low-speed signal pins BMC I2C SDA_0 and BMC I2C SCL_0 of the first U.2 connector through the PCB traces on the second circuit board.

[0080] In the embodiment, the U.2 connector needs X4 PCIE high-speed signals and 1 group of clock signals, and the UBCDD connector contains X16 PCIE high-speed signals and 4 groups of 100M clock signals. Therefore, the UBCDD connector can support up to 4 U.2 connectors. The UBCDD connector uses three power supplies VCC_12V, VCC_3V3 and STBY_3V3, and the U.2 connector needs to be powered by 12V and STBY_3V3 when supporting the NVM Express (NVME) PCIE device. The two power supply pins VCC_12V and STBY_3V3 of the UBCDD connector can be directly connected, and the current meets the requirements.

[0081] In some possible embodiments, the first signal processing circuit 115 can specifically include a chip (such as a 9545 chip) supporting 4-way I2C communication expansion.

[0082] In some possible embodiments, the low-speed signal further includes a second bus signal, and the second circuit board 11 further includes a second signal processing circuit 116. The second bus signal can be specifically an I2C bus signal of a complex programmable logic device (CPLD), including two-way CPLD I2C SDA and CPLD I2C SCL signals. The two-way signals are used to expand the general-purpose input / output (GPIO) pins, and I2C SDA refers to I2C serial data line (Serial Data, SDA), and I2C SCL refers to I2C serial clock line (Serial Clock Line, SCL). Wherein:

[0083] The second bus signal output by the low-speed signal pin of the first connector 102 is input into the second signal processing circuit 116 through the low-speed signal line of the first cable 12 corresponding to the second target connector, and the elastic pin 111 of the second target connector. The second target connector is any one of the at least one second connector 111, and specifically can be Figure 4 Any one of the four U.2 connectors, Figure 4 Taking the second U.2 connector from top to bottom as an example, the second target connector is not the same connector as the first target connector.

[0084] The second signal processing circuit 116 is configured to generate a multi-path state indication signal according to the second bus signal, and the multi-path state indication signal is used to indicate the working state of the PCIE device 112 connected to each second connector 111.

[0085] Specifically, the second signal processing circuit 116 can expand a plurality of GPIO pins according to the second bus signal, and the expanded GPIO pins can be used to output an ACTIVE signal of the PCIE device, and can also be used to generate a multi-path state indication signal. The state indication signal can control the indicator light of the corresponding PCIE device, for example, the working state of the PCIE device 112 can be indicated by controlling the lighting / extinguishing of the indicator light, or by controlling the color of the indicator light. The indicator light can include a connector present state indicator light (PRSNT_LED), a fault indicator light (ACTIVE_LED and FAULT_LED are used in combination).

[0086] In some possible implementation manners, the second signal processing circuit 116 specifically can include a general-purpose parallel input / output expansion chip (such as a 9555 chip).

[0087] In some possible implementation manners, the low-speed signal further includes a device slot detection signal, and the second circuit board 11 further includes a plurality of third signal processing circuits 117, wherein:

[0088] Each third signal processing circuit 117 is connected to the corresponding second connector 111.

[0089] Each third signal processing circuit 117 is configured to generate a device slot detection signal connected to the corresponding second connector 111.

[0090] When the PCIE device is a hard disk, the device slot detection signal specifically can be a hard disk slot detection signal.

[0091] Each second connector 111 is configured to transmit, through a low-speed signal line of the corresponding first cable 12, a device slot detection signal of each second connector 111 to a low-speed signal pin of the first connector 102, the device slot detection signal being used to indicate whether the mounting slot of each second connector 111 is incorrect.

[0092] Specifically, taking Figure 4 for example, each U.2 connector 111 transmits the PCIE device slot detection signal of the corresponding PCIE device through three low-speed signal pins TYPE_A, TYPE_B, TYPE_C, taking the first U.2 connector from top to bottom as an example, the U.2 connector transmits the device slot detection signal of the corresponding PCIE device through TYPE0_A, TYPE0_B, TYPE0_C pins, and other U.2 connectors are the same. The third signal processing circuit 117 can specifically generate the PCIE device slot detection signal of the corresponding U.2 connector 111 through the pull-up circuit / pull-down circuit to distinguish different slots, for example, through the pull-up circuit, the TYPE0_A, TYPE0_B, TYPE0_C three pins can all input high level, that is, “111”, through the pull-down circuit, the three pins can all input low level, that is, “000”, and through the combination of the pull-up circuit and the pull-down circuit, the TYPE0_A, TYPE0_B, TYPE0_C three pins can respectively input high level or low level, for example, “101”, and the first circuit board side can determine whether the mounting slot of each second connector 111 is incorrect according to the PCIE device slot detection signal. For example, after the pull-up circuit / pull-down circuit corresponding to each U.2 connector on the second circuit board 11 is determined, the device slot detection signal corresponding to each U.2 connector is also determined, assuming Figure 4 that the device slot detection signals corresponding to the four U.2 connectors in the above are “001”, “010”, “011”, and “100” in turn, the controller of the first circuit board 10 can record these four device slot detection signals, which can be recorded in the Basic Input Output System (BIOS), if the U.2 connector is inserted in the wrong position, the device slot detection signal transmitted to the first circuit board 10 will be inconsistent with the record in the BIOS of the controller, at this time, it can be determined that the mounting slot is incorrect.

[0093] In some possible embodiments, the low-speed signal further includes a connector in position signal, wherein:

[0094] Any one of the plurality of second connectors 111 can transmit the connector in position signal to the first cable through the low-speed signal pin thereof.

[0095] The low-speed signal pin of the second connector can transmit multiple connector presence signals of the second connector 111 to the first connector 102 through the low-speed signal line of the first cable 12 corresponding to the second connector.

[0096] Specifically, taking at least one third target connector and a fourth target connector in the second connector 111 as examples, the third target connector is different from the fourth target connector. The third target connector transmits the connector presence signal of the third target connector to the fourth target connector through a low-speed signal pin connected to the fourth target connector.

[0097] The low-speed signal pin of the fourth target connector is used to transmit the connector presence signal of the third target connector to the first connector 102 via the low-speed signal line of the first cable 12 corresponding to the fourth target connector, or to transmit both the connector presence signal of the third target connector and the connector presence signal of the fourth target connector to the first connector 102. That is, some connectors in the second connector can transmit their connector presence signals to other connectors, which then transmit them to the first connector 102 on the first circuit board. These other connectors can also simultaneously transmit their own connector presence signals, along with the received connector presence signals, to the first connector 102 on the first circuit board.

[0098] For example, with Figure 4 For example, the low-speed signal pins (PRSNT0, PRSNT1) corresponding to the connector presence signals of the first and second U.2 connectors from top to bottom can be connected to the low-speed signal pin of the third U.2 connector from top to bottom. The third U.2 connector then transmits the connector presence signals of the first and second U.2 connectors to the first connector 102 via the corresponding low-speed signal line of the first cable 12. Similarly, the fourth U.2 connector transmits the connector presence signals of the third U.2 connector and itself (the fourth U.2 connector) to the first connector 102 via the corresponding low-speed signal line of the first cable 12.

[0099] It should be noted that, Figure 4 The corresponding pins between connectors on the second circuit board 11, and the corresponding pins between connectors and each signal processing circuit, can be connected via PCB traces on the second circuit board. The corresponding pins between the UBCDD connectors and each U.2 connector on the first circuit board 10 are connected via corresponding first cables 12.

[0100] In some feasible implementations, the low-speed signal also includes a reset signal, wherein:

[0101] The low-speed signal pins of the first connector 102 are used to transmit reset signals to the corresponding second connector 111 through the low-speed signal lines of each first cable 12. Figure 4 For example, the reset signals can be RST_0, RST_1, RST_2, RST_3 four-way reset signals, which can be specifically input into the reset pins of each U.2 connector 111 to realize the reset of the PCIE device (such as a hard disk) connected by the U.2 connector.

[0102] In some possible embodiments, the low-speed signals further include device type signals, wherein:

[0103] The low-speed signal pins of each second connector 111 are used to transmit device type signals to the first connector 102 through the low-speed signal lines of the corresponding first cable 12. Figure 4 For example, the device type signals are specifically hard disk type signals, and after each U.2 connector 111 is connected to a hard disk, the output pins of the corresponding hard disk type signals can generate hard disk type signals of the connected hard disk, such as the four-way hard disk type signals of IFDET_0, IFDET_1, IFDET_2, and IFDET_3 output by the pins of the four U.2 connectors 111.

[0104] In some possible embodiments, the first cable 12 further includes a power signal line, wherein:

[0105] The power signal line of each first cable 12 is used to transmit a power signal to the PCIE device 112 connected by the corresponding second connector 111 through the power pins of the first connector 102 and the power pins of the corresponding second connector 111. The embodiments of the present application do not need to additionally increase the power cable, and the high-speed signals, low-speed signals, and power signals required by the corresponding PCIE device can be transmitted through one cable.

[0106] In some possible embodiments, as shown in Figure 5 If the first connector 102 is a non-full-function high-speed connector, such as an MCIO connector or a UBC connector, the first circuit board 10 can further include a power connector 103, and the first cable 12 includes the high-speed signal line and the low-speed signal line 120, and further includes a power signal line 121, wherein:

[0107] One end of the power signal line 121 of each first cable 12 is connected to the power connector 103, and the other end is connected to the second connector 111.

[0108] The power signal line 121 of each first cable 12 is used to transmit a power signal to the PCIE device 112 through the power pins of the power connector 103 and the power pins of the corresponding second connector 111.

[0109] In some feasible implementations, such as Figure 6 As shown, if the first connector 102 is a non-full-function high-speed connector, such as an MCIO connector or a UBC connector, and the first cable 12 does not include a power signal line, then the first circuit board 10 may also include a power connector 103, and the signal transmission circuit may also include at least one second cable 13, wherein:

[0110] One end of each second cable 13 is connected to the power connector 103, and the other end is connected to the corresponding second connector 111.

[0111] Each second cable 13 is used to transmit power signals to the PCIe device 112 through the power pin of the power connector 103 and the power pin of the corresponding second connector 111.

[0112] In some feasible implementations, such as Figure 7 As shown, in Figure 6 Based on this, the second circuit board 11 can also be equipped with a power connector 118. The power connector 118 can be connected to the second connector 111 through PCB traces on the second circuit board 11, wherein:

[0113] One end of each second cable 13 is connected to power connector 103, and the other end is connected to power connector 118.

[0114] Each second cable 13 is used to transmit power signals to the PCIe device 112 through the power pins of the power connector 103, the power pins of the power connector 118, the PCB traces between the power connector 118 and the second connector 111, and the power pins of the corresponding second connector 111.

[0115] Please see Figure 8 This is a schematic diagram of a circuit board provided in an embodiment of this application. This circuit board can correspond to the second circuit board 11 described above. The circuit board includes at least one first cable 12 and at least one second connector 111, wherein:

[0116] One end of each first cable 12 is connected to a corresponding second connector 111, and the other end of each first cable 12 includes a plug-in interface 122 for connecting a first connector 102, which is disposed on another circuit board (such as the first circuit board 10 described above).

[0117] Each first cable 12 is used to transmit high-speed serial computer expansion bus (PCIE) signals between the PCIE device 112 connected to the corresponding second connector 111 and the controller on another circuit board.

[0118] The circuit board provided by the embodiment of the present application is characterized in that one end of each cable is directly connected to the connector of the corresponding PCIE device, the other end is connected to the connector of the first circuit board through the pluggable interface, the connector of the first circuit board is directly connected to the connector of each PCIE device on the second circuit board through the cable, the PCIE signal between the controller and the corresponding PCIE device is transmitted through the cable, the distance of transmission of the high-speed signal such as PCIE in the PCB wiring of the circuit board is shortened, the transmission loss of the high-speed signal between the controller and each PCIE device is effectively reduced, and the first circuit board and the second circuit board are connected through the pluggable interfaces of the cables, so that the second circuit board can be used as a flexible replacement circuit module, and the flexibility of the second circuit board is improved.

[0119] Referring to Figure 9 is a structural schematic diagram of an electronic device provided by the embodiment of the present application, and the electronic device comprises a cabinet and the signal transmission circuit described above.

[0120] The electronic device can be a computer device such as a server.

[0121] Referring to Figure 10 is a structural schematic diagram of another electronic device provided by the embodiment of the present application, and the electronic device comprises a cabinet and Figure 7 the first circuit board and / or the second circuit board shown in Figure 8 the circuit board shown in

[0122] The electronic device can be a computer device such as a server.

[0123] The above disclosure is only some embodiments of the present application, and of course cannot limit the scope of the rights of the present application, and those skilled in the art can understand that the above-mentioned all or part of the processes are implemented, and the equivalent changes made according to the claims of the present application still belong to the scope covered by the present application.

Claims

1. A signal transmission circuit, characterized by comprising: The signal transmission circuit comprises a first circuit board, a second circuit board, a first connector, a plurality of first cables and a plurality of second connectors; wherein the first connector is arranged on the first circuit board, the plurality of second connectors are arranged on the second circuit board, and the plurality of second connectors are connected with PCIE devices on the second circuit board; one end of each of the first cables is connected with the first connector, and the other end of each of the first cables is connected with a corresponding second connector; each of the first cables is used for transmitting high-speed serial computer expansion bus PCIE signals between a controller arranged on the first circuit board and a PCIE device connected with the corresponding second connector; the first cable comprises a high-speed signal line and a low-speed signal line, low-speed signals transmitted by the low-speed signal line comprise a first bus signal, and the second circuit board further comprises a first signal processing circuit, wherein: the first bus signal output by a low-speed signal pin of the first connector is input into the first signal processing circuit through a low-speed signal line of a first target connector corresponding to the first cable, a low-speed signal pin of the first target connector, the first target connector being any one of the plurality of second connectors; the first signal processing circuit is used for generating a plurality of bus signals according to the first bus signal and inputting the plurality of bus signals into low-speed signal pins of each of the second connectors respectively.

2. The signal transmission circuit according to claim 1, wherein: the high-speed signal line of each of the first cables is used for transmitting PCIE signals between the controller and the PCIE device connected with the corresponding second connector through a high-speed signal pin of the first connector, a high-speed signal pin of the corresponding second connector and a high-speed signal pin of the PCIE device connected with the corresponding second connector; the low-speed signal line of each of the first cables is used for transmitting low-speed signals through a low-speed signal pin of the first connector, a low-speed signal pin of the corresponding second connector and a low-speed signal pin of the PCIE device connected with the corresponding second connector.

3. The signal transmission circuit according to claim 1, characterized by the low-speed signals further comprise a second bus signal, and the second circuit board further comprises a second signal processing circuit, wherein: the second bus signal output by the low-speed signal pin of the first connector is input into the second signal processing circuit through a low-speed signal line of a second target connector corresponding to the first cable, a low-speed signal pin of the second target connector, the second target connector being any one of the plurality of second connectors and being different from the first target connector; the second signal processing circuit is used for generating a plurality of state indication signals according to the second bus signal, the plurality of state indication signals being used for indicating working states of the PCIE devices connected with each of the second connectors.

4. The signal transmission circuit of claim 1, wherein the low-speed signals further comprise PCIE device slot detection signals, and the second circuit board further comprises a plurality of third signal processing circuits, wherein: each of the third signal processing circuits is connected with a corresponding second connector; Each third signal processing circuit is configured to generate a PCIE device slot detection signal of the corresponding second connector. Each second connector is configured to transmit the PCIE device slot detection signal of the second connector to a low-speed signal pin of the first connector through a low-speed signal line of the corresponding first cable, and the PCIE device slot detection signal is used to indicate whether the mounting slot of the PCIE device connected to the second connector is incorrect.

5. The signal transmission circuit of claim 1, wherein, The low-speed signals further include a connector-in-place signal, wherein: A third target connector transmits a connector-in-place signal to a fourth target connector through a low-speed signal pin connected to the fourth target connector, and the third target connector and the fourth target connector are different connectors in the plurality of second connectors. The low-speed signal pin of the fourth target connector is configured to transmit the connector-in-place signal of the third target connector to the first connector through a low-speed signal line of the corresponding first cable of the fourth target connector, or transmit the connector-in-place signal of the third target connector and the connector-in-place signal of the fourth target connector to the first connector.

6. The signal transmission circuit of claim 1, wherein, The low-speed signals further include a reset signal, wherein: The low-speed signal pin of the first connector is configured to transmit the reset signal to the corresponding second connector through a low-speed signal line of each first cable.

7. The signal transmission circuit of claim 1, wherein The low-speed signals further include a PCIE device type signal, wherein: The low-speed signal pin of each second connector is configured to transmit the PCIE device type signal to the first connector through a low-speed signal line of the corresponding first cable.

8. The signal transmission circuit according to any one of claims 1 to 7, characterized by, The first cable further includes a power signal line, wherein: The power signal line of each first cable is configured to transmit a power signal to the PCIE device connected to the corresponding second connector through a power pin of the first connector and a power pin of the corresponding second connector.

9. The signal transmission circuit of claim 1, wherein, Each first cable is connected to the corresponding second connector by welding.

10. The signal transmission circuit of claim 1, wherein, Each first cable is connected to the first connector by plugging.

11. The signal transmission circuit of claim 1, wherein, Each second connector is fixedly installed on the second circuit board by a screw.

12. The signal transmission circuit of claim 1, wherein, The second connector includes a U.2 connector.

13. A circuit board, characterized by The circuit board includes a plurality of first cables and a plurality of second connectors, wherein: One end of each first cable is connected to the corresponding second connector, and the other end of each first cable includes a pluggable interface configured to be connected to a first connector arranged on another circuit board. Each first cable is configured to transmit a high-speed serial computer expansion bus (PCIE) signal between the PCIE device connected to the corresponding second connector and a controller on the other circuit board, and the first cable includes a high-speed signal line and a low-speed signal line, and the low-speed signal transmitted by the low-speed signal line includes a first bus signal, and the circuit board further includes a first signal processing circuit, wherein: The first bus signal output by the low-speed signal pin of the first connector is input to the first signal processing circuit through the low-speed signal line of the first cable corresponding to the first target connector, and the first target connector is any one of the plurality of second connectors; The first signal processing circuit is configured to generate a plurality of bus signals according to the first bus signal, and input the plurality of bus signals to the low-speed signal pins of each of the second connectors, respectively.

14. An electronic device, comprising: A signal transmission circuit according to any one of claims 1 to 12 or a circuit board according to claim 13.

Images