Port hierarchical control method, device, electronic device and readable storage medium

Abstract

The embodiment of the present application provides a port hierarchical control method, device, electronic device and readable storage medium, which relates to the field of Ethernet technology. The method includes: obtaining the respective states of MII, PCS and SerDes from top to bottom of the target port to obtain the current port state combination; judging whether a state change occurs according to the saved historical port state combination and the current port state combination; if yes, determining the target event corresponding to the state change, the target event is the top-level up event or the bottom-level down event in MII, PCS and SerDes; according to the target event, the receiving end of the upper layer module of the target module in the target event is reset or reset, wherein when the target event is the target module up event, the reset is performed, and when the target event is the target module down event, the reset is performed. In this way, the bit error rate can be reduced, and fragmented packets and abnormal packets can be reduced.

Description

Technical Field

[0001] The present application relates to the field of Ethernet technology, and in particular to a port hierarchical control method, device, electronic device and readable storage medium. Background Art

[0002] The IEEE802.3 standard defines the implementation from the MAC layer to the media layer. In practical applications, except for the media part, the remaining modules (i.e., each layer) are what the Ethernet chip needs to design and implement. For a port, after each module completes configuration and reset, it can send and receive messages normally. However, due to the different designs of the message data buffer and queue of each module, the current port control method generally leads to high bit error rate, fragmented packets, abnormal packets, etc. Summary of the invention

[0003] The embodiments of the present application provide a port hierarchical control method, device, electronic device and readable storage medium, which can reduce the bit error rate, reduce fragmented packets and abnormal packets, etc.

[0004] The embodiments of the present application can be implemented as follows:

[0005] In a first aspect, the present application provides a port hierarchical control method, wherein the port includes, from top to bottom, a medium independent interface MII, a physical coding sublayer PCS, and a deserializer SerDes, and the method includes:

[0006] Respectively obtain the states of the MII, PCS and SerDes of the target port to obtain the current port state combination of the target port;

[0007] Determine whether a state change occurs according to the saved historical port state combination and the current port state combination;

[0008] When a state change occurs, determining a target event corresponding to the state change, wherein the target event is an up event of the uppermost layer or a down event of the lowermost layer in the MII, PCS and SerDes;

[0009] According to the target event, the receiving end of the upper layer module of the target module in the target event is de-reset or reset, wherein when the target event is the target module up event, the de-reset is performed, and when the target event is the target module down event, the reset is performed.

[0010] In a second aspect, an embodiment of the present application provides a port hierarchical control device, wherein the port includes, from top to bottom: a medium independent interface MII, a physical coding sublayer PCS, and a deserializer SerDes, and the device includes:

[0011] A state collector, used to obtain the states of the MII, PCS and SerDes of the target port respectively, so as to obtain the current port state combination of the target port;

[0012] The state collector is further used to determine whether a state change occurs based on the saved historical port state combination and the current port state combination;

[0013] An event determiner, used for determining a target event corresponding to the state change when a state change occurs, wherein the target event is an up event of the uppermost layer or a down event of the lowermost layer in the MII, PCS and SerDes;

[0014] An event processor is used to, according to the target event, de-reset or reset the receiving end of the upper layer module of the target module in the target event, wherein when the target event is the up event of the target module, de-reset is performed, and when the target event is the down event of the target module, reset is performed.

[0015] In a third aspect, an embodiment of the present application provides an electronic device, including a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor can execute the machine executable instructions to implement the port hierarchical control method described in the aforementioned embodiment.

[0016] In a fourth aspect, an embodiment of the present application provides a readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the port hierarchical control method as described in the foregoing implementation manner.

[0017] The port hierarchical control method, device, electronic device and readable storage medium provided by the embodiments of the present application, when there is a state change between the current port state combination composed of the current states of the MII, PCS and SerDes of the target port and the saved historical port state combination, determine the target event corresponding to the state change; then, based on the target time, the receiving end of the upper layer module of the target module in the target event is reset or reset. Wherein, the target event is the up event of the upper layer or the down event of the lower layer in the MII, PCS and SerDes; wherein, when the target event is the up event of the target module, the reset is performed, and when the target event is the down event of the target module, the reset is performed. In this way, by enabling the upper module after the lower module is in the best working state, the bit error rate can be effectively reduced, and fragmented messages can be prevented from entering the chip, thereby reducing fragments and abnormal packets, and achieving the purpose of decoupling between layers and improving the stability of port operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 is a schematic diagram of an Ethernet communication system;

[0020] Figure 2 A block diagram of an electronic device provided in an embodiment of the present application;

[0021] Figure 3 One of the flow charts of the port hierarchical control method provided in the embodiment of the present application;

[0022] Figure 4 A schematic diagram of the distribution of MII, PCS and SerDes provided in an embodiment of the present application;

[0023] Figure 5 for Figure 3 One of the flowchart diagrams of the sub-steps included in step S110;

[0024] Figure 6 for Figure 3 2 is a flow chart of the sub-steps included in step S110;

[0025] Figure 7 for Figure 3 3. Flow chart of sub-steps included in step S110;

[0026] Figure 8 A jitter diagram of a port state combination provided in an embodiment of the present application;

[0027] Fig. 9 The second flowchart of the port hierarchical control method provided in the embodiment of the present application;

[0028] Fig.10 A schematic diagram of a steady-state port status combination provided in an embodiment of the present application;

[0029] Fig.11 for Figure 3 A schematic flow chart of the sub-steps included in step S140;

[0030] Fig.12 One of the state change schematic diagrams provided in the embodiment of the present application;

[0031] Fig.13 The second state change diagram provided in the embodiment of the present application;

[0032] Fig.14 A schematic diagram of actions corresponding to different events provided in an embodiment of the present application;

[0033] Fig.15 A block diagram of a port hierarchical control device provided in an embodiment of the present application.

[0034] Icon: 100 - electronic device; 110 - memory; 120 - processor; 130 - communication unit; 200 - port hierarchical control device; 210 - status collector; 220 - event determiner; 230 - event processor. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0036] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0037] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0038] The IEEE802.3 standard defines the implementation from the MAC (Media Access Control) layer to the media layer. The structures of ports with different rates are basically similar. Taking the 25G rate as an example, Figure 1As shown, the data of the MAC layer is connected to the PCS (Physical Coding Sublayer) and FEC (Forward Error Correction) below via 25GMII (Media Independent Interface), and reaches the medium through PMA (Physical Medium Attachment) and PMD (Physical Medium Dependent).

[0039] Among them, FEC is used to re-encode the data after PCS encoding, which can automatically correct a certain amount of bit errors and reduce the bit error rate.

[0040] Combination Figure 1 It can be seen that when a MAC data message is sent to the other end, the key nodes it passes through are:

[0041] 1.MAC, located at the data link layer, where user data is assembled into MAC frame format;

[0042] 2.MII, its function is to establish a connection from MAC to the physical layer, including two parts: passing the upper layer MAC data to PCS; link status control, which can detect link faults and errors;

[0043] 3. PCS, encodes the upper layer data according to a specific physical layer method; the message is divided into several blocks, and each block will add 2 bits in the header for synchronization; PCS also has basic error checking;

[0044] 4.PMA / PMD, PMA is mainly used to complete serial-to-parallel conversion. Data is parallel before being processed by PMA, and is processed into serial data by PMA. PMD performs transparent transmission at the data level, but provides some functions at the control level, such as training, TX, RX, SIGNAL_DETECT, etc. In addition, it also specifies some electrical characteristics, which are strongly related to the medium.

[0045] 5. Medium. Common high-speed Ethernet media include PCB traces, copper cables, optical fibers, AOC, etc.

[0046] In actual applications, except for the media part, the remaining modules (i.e., the remaining layers) are all designed and implemented by the Ethernet chip. For a port, after each module completes configuration and reset, it can send and receive messages normally. However, due to the different designs of message data buffers and queues of each module, reset and reset (enable and disable) must be performed in a certain order, and the queues of the upper and lower modules must be guaranteed to be empty, otherwise there may be residual messages in the queues before and after the reset module, and then fragmented messages will be stuck in the queue. Once a new message is sent to the queue, the fragments will be "sticky" with the normal messages behind, which will produce deformed (illegal) messages, and then cause unpredictable exceptions when the module is encoded and decoded. The configuration and reset of each module are generally completed by the chip driver.

[0047] Based on the above research, the inventors of the present application found that in the port driver of the Ethernet chip, it is necessary to ensure: 1. The enabling and disabling of each module are carried out in the order of the direction of data transmission; 2. Ensure that the queue is completely cleared when shutting down; 3. When enabling, the lower-level module ensures that everything is ready before enabling the upper-level module.

[0048] Currently, the following two methods are used for port control.

[0049] Method 1: The driver completes the enabling operation of each module at one time in a certain order, and waits for the ASIC (Application Specific Integrated Circuit) logic of each module to complete synchronization, alignment, locking and other operations by itself, and then starts to transmit messages.

[0050] Method 1 can only guarantee the order of enabling, but cannot guarantee that the queues of each module are completely cleared or in a fully ready state. Because the PMA / PMD is not tuned for the receiving end equalizer when the link loss is uncertain, the bit error rate may be too high; and because it cannot guarantee that the queues of each module are completely cleared, it is impossible to completely avoid fragmented messages. If there is still unfinished data in a queue when the port enable is switched to the closed state, it will cause problems.

[0051] Method 2: During port enabling, first release the PCS reset, but maintain the MII reset, let the PCS layer reach the SYNC state first, then perform SerDes equalizer tuning, and then release the MII reset after completion, and start sending and receiving user data.

[0052] Although the second method avoids the problem of too high bit error rate caused by not tuning the receiving end equalizer of PMA / PMD, it does not take into account that the PCS module also needs to be put into operation after the PMA / PMD has been tuned. Otherwise, fragmented packets and abnormal packets may still affect the operation of the PCS.

[0053] The internal module de-reset of the Ethernet chip port must be in a certain order, and the queues of the upper and lower modules must be kept empty, otherwise fragmented messages may appear. This fragmentation combined with the subsequent normal messages will produce deformed (illegal) messages, which will lead to unpredictable exceptions during module decoding.

[0054] In order to ensure that the enabling order of each module meets expectations and follows the principle of enabling the upper-level module after the lower-level module is in the best working state, thereby improving the stability of port operation, the embodiments of the present application provide a port layered control method, device, electronic device and readable storage medium based on event perception, which uses state and events as the driving force to enable each module to be restored and optimized before sending and receiving user data, so as to be in the most suitable working state, and can effectively prevent fragmented messages from entering the chip, thereby achieving the purpose of decoupling between layers and improving the stability of port operation.

[0055] It is worth noting that the defects existing in the above solutions are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed in the embodiments of this application below for the above problems should be the contributions made by the inventor to this application during the application process.

[0056] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0057] Please refer to Figure 2 , Figure 2 A block diagram of an electronic device 100 provided in an embodiment of the present application. The electronic device 100 may be, but is not limited to, a computer, a server, etc. The electronic device 100 includes a memory 110, a processor 120, and a communication unit 130. The memory 110, the processor 120, and the communication unit 130 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components may be electrically connected to each other via one or more communication buses or signal lines.

[0058] The memory 110 is used to store programs or data. The memory 110 may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc.

[0059] The processor 120 is used to read / write data or programs stored in the memory 110 and execute corresponding functions. For example, the memory 110 stores a port hierarchical control device 200, and the port hierarchical control device 200 includes at least one software function module that can be stored in the memory 110 in the form of software or firmware. The processor 120 executes various functional applications and data processing by running software programs and modules stored in the memory 110, such as the port hierarchical control device 200 in the embodiment of the present application, that is, implementing the port hierarchical control method in the embodiment of the present application.

[0060] The communication unit 130 is used to establish a communication connection between the electronic device 100 and other communication terminals through a network, and to send and receive data through the network.

[0061] It should be understood that Figure 2 The structure shown is only a schematic diagram of the structure of the electronic device 100. The electronic device 100 may also include Figure 2 More or fewer components as shown, or with Figure 2 Different configurations shown. Figure 2 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0062] Please refer to Figure 3 , Figure 3 One of the flow diagrams of the port hierarchical control method provided in the embodiment of the present application. The method can be applied to Ethernet environments with high requirements for real-time data transmission, such as data center networks, industrial networks, etc. The method can be applied to the above-mentioned electronic device 100. The specific process of the port hierarchical control method is described in detail below. In this embodiment, the method may include step S110, step S130 to step S150.

[0063] Step S110, respectively obtaining the states of the MII, PCS and SerDes of the target port to obtain the current port state combination of the target port.

[0064] In this embodiment, the target port is a specific Ethernet port that needs to be hierarchically controlled, which can be determined in combination with actual needs. First, the key status of each layer of the target port needs to be extracted. For ease of operation, Figure 4 As shown in the figure, the ANLT & PMD & PMA of the port are combined into a state phyready, plus the SYNC of the PCS and the MII link up, forming the key state combination of the port: (PHY_RDY, PCS_SYNC, MII_UP). That is, Figure 4 As shown in the figure, the ports include MII, PCS and SerDes (Serializer-Deserializer) from top to bottom. SerDes represents the part from the medium to the PCS. In other words, PHY_RDY indicates the status of SerDes; PCS_SYNC indicates the status of PCS; MII_UP indicates the status of MII.

[0065] The states of the MII, PCS and SerDes of the target port can be extracted respectively, so as to obtain the current port state combination of the target port, which includes the current states of the MII, PCS and SerDes.

[0066] Step S130, judging whether a state change occurs according to the saved historical port state combination and the current port state combination.

[0067] After obtaining a current port state combination, the current port state combination can be saved. When obtaining a new current port state combination, the previously saved current port state combination is the saved historical port state combination. Only one historical port state combination can be saved. When the current port state combination is obtained, the current port state combination can be compared with the historical port state combination to determine whether there is a change between the two state combinations. If there is a change, it means that a state change has occurred from the historical port state combination to the current port state combination; otherwise, it is determined that no change has occurred.

[0068] When it is determined that a state change occurs, step S140 may be performed. When it is determined that no state change occurs, step S110 may be performed, that is, obtaining a new current port state combination again.

[0069] Step S140: determining a target event corresponding to the state change.

[0070] When a state change occurs, the state change can be analyzed to determine the target event triggered by the state change. The target event is the up event of the top layer or the down event of the bottom layer in the MII, PCS and SerDes. That is, the target event may be an up event of MII, or an up event of PCS, or an up event of SerDes; it may also be a down event of MII, or a down event of PCS, or a down event of SerDes. The target event indicates that an up event or a down event has occurred in the target module, and the target module is one of the three of MII, PCS and SerDes.

[0071] For example, when MII, PCS and SerDes are all down, since SerDes is the lowest layer among the three and is dwon, the target event is the down event of SerDes; for another example, assuming that the state combination of MII, PCS and SerDes is: 0,1,1, since PCS is the uppermost layer of the two modules in which the up event occurs, the target event at this time is the up event of PCS.

[0072] Step S150: according to the target event, the receiving end of the upper layer module of the target module in the target event is reset or de-reset.

[0073] In the case of determining the target event triggered by the state change, the target event can be analyzed. If the target event is the target module up event, the receiving end RX of the upper layer module of the target module can be de-reset. If the target event is the target module down event, the receiving end RX of the upper layer module of the target module can be reset. For example, assuming that the target module is PCS, since the upper layer module of PCS is MII, the RX of MII can be de-reset or reset. For another example, assuming that the target module is MII, since the upper layer of MII is MAC, the RX of MAC can be de-reset or reset.

[0074] The embodiment of the present application is driven by states and events. After the lower-level module is in the best working state, the upper-level module is enabled, which can effectively reduce the bit error rate, prevent fragmented messages from entering the chip, and further reduce fragments and abnormal packets, thereby achieving the purpose of decoupling between layers and improving the stability of port operation.

[0075] In this embodiment, the ports may be configured first to determine the target ports and the modules corresponding to the target ports. Then, for each target port, based on the correspondence between the target port and the module, the MII, PCS, and SerDes corresponding to the target port may be determined to obtain the current port status combination.

[0076] There is a status called Global_PMD_signal_detect in the IEEE802.3 standard. When TX training is performed, this status is set to 1 if the training is successful, otherwise it is set to 0. If TX training is not performed, it is directly set to 1. Its function is to notify the upper layers layer by layer, indicating that the link from the medium to the part below the PCS (i.e., SerDes) has been established and the upper layer communication can begin.

[0077] In terms of function, PHY_RDY and Global_PMD_signal_detect in the embodiment of the present application are the same, indicating to the upper layer that the SerDes is ready. But in fact, the standard only defines a minimum requirement (even without TXtraining, no additional conditions are specified). Considering the operability of actual products, that is, to objectively reflect the information that the SerDes link is completed, the status of the SerDes should be redefined.

[0078] The inventor of the present application has found through research that when the port is configured in the auto-negotiation mode, if it is considered that the serdes link is established, multiple aspects should be considered from the perspective of engineering application. Therefore, in this embodiment, when the target port is configured in the auto-negotiation mode, Figure 5 The SerDes status of the target port can be obtained by Figure 5 , Figure 5 for Figure 3 One of the flowchart diagrams of the sub-steps included in step S110. In this embodiment, step S110 may include sub-steps S1111 to S1115.

[0079] Sub-step S1111, detecting whether the phase-locked loop of the SerDes is correctly locked.

[0080] Sub-step S1112, detecting whether the receiving end of the SerDes can recover a valid signal.

[0081] Sub-step S1113, detecting whether the equalizer at the receiving end of the SerDes is adjusted.

[0082] Sub-step S1114, detecting whether the sending end of the SerDes has completed training.

[0083] Sub-step S1115, determining whether the SerDes link establishment is completed according to the detected state;

[0084] The phase-locked loop PLL of the SerDes is correctly locked, indicating that the SerDes has been working normally. The receiving end of the SerDes can reply with a valid signal, indicating that the rate of the SerDes is the same as the rate of the online data (i.e., the data transmitted by the medium). The equalizer adjustment of the receiving end of the SerDes is completed, indicating that the SerDes is in the optimal working state. In the auto-negotiation mode, TX training is generally enabled. In this case, training needs to be completed. When 4 detection results are obtained through the detection of sub-steps S1111 to S1114, the state of the SerDes can be determined according to the 4 detection results (i.e., PHY_RDY is determined), that is, whether the SerDes link establishment is completed.

[0085] As a possible implementation method, if the SerDes link is considered to be complete, it must meet four conditions: (1) the SerDes PLL is correctly locked; (2) the RX end recovers the valid signal; (3) the RX end equalizer adjustment is completed; (4) if TX training is enabled, training must also be completed.

[0086] It can be seen that the PHY_RDY state in the embodiment of the present application is a subset of the standard Global_PMD_signal_detect. PHY_RDY = (SerDes PLL lock) && (RX signal valid) && (RX Equalization done) && (((TX training enable) && (TX training done)) || TX training disable). That is, when the above four conditions are met, the PHY_RDY state can be considered to be 1, otherwise it is 0.

[0087] When the target port is configured in the mandatory mode, the PHY_RDY check can be shielded, and the PHY_RDY state is directly determined to be 1, that is, it is determined that the SerDes link establishment is completed.

[0088] PCS_SYNC has the same meaning as PCS_status defined in the standard, see IEEE 802.3CL49.2.14.1 for details. Figure 6 The PCS status is obtained in the manner shown. Figure 6 , Figure 6 for Figure 3 2 is a flow chart of sub-steps included in step S110. In this embodiment, step S110 may include sub-steps S1121 to S1122.

[0089] Sub-step S1121, obtaining a block lock state and a high bit error rate state.

[0090] Sub-step S1122, obtaining the state of the PCS according to the block lock state and the high bit error rate state.

[0091] The block lock state can be true or false. The synchronization header is checked in units of 66 bits of coding length (i.e., one block). If the synchronization headers of 64 consecutive blocks are all valid, the block lock state is true. The high bit error rate state can be true or false. The number of bit errors is continuously monitored in units of every 125us. If it is less than 16, hi_ber (i.e., high bit error rate) is false, otherwise it is true. When the block lock state and the high bit error rate state are obtained through detection, the state of the PCS (i.e., PCS_status) can be determined based on the block lock state and the high bit error rate state, that is, whether the PCS is synchronized can be determined.

[0092] In this embodiment, PCS_SYNC=(block_lock is TRUE)&&(hi_ber is FALSE), that is, when the block lock state is true and the high bit error rate state is false, PCS_SYNC is true, otherwise it is false.

[0093] MII_UP is simply the combination of PCS_SYNC and link fault status. Link fault refers to the link_fault (link error) status defined by the standard, see IEEE 802.3CL46.3.4.3 for details. The link status indication of the MII interface has four values: equal to ok, indicating no error; equal to local fault, indicating a local error; equal to remote fault, indicating a remote error; equal to link interruption, indicating a temporary disconnection of the link.

[0094] In this embodiment, Figure 7 The state of the MII is obtained in the manner shown. Figure 7 , Figure 7 for Figure 3 3 is a flow chart of sub-steps included in step S110. In this embodiment, step S110 may include sub-steps S1131 to S1133.

[0095] Sub-step S1131, obtaining the status of the PCS.

[0096] Sub-step S1132, obtaining the link status of the MII.

[0097] Sub-step S1133, obtaining the state of the MII according to the state of the PCS and the link state of the MII.

[0098] In this embodiment, the state of the PCS may be the state obtained through sub-steps S1121 to S1122. The link state of the MII is link fault. The state acquisition method of the MII may be as follows: MII_UP = (PCS_SYNC == 1) && (link_fault == OK), that is, when the PCS is synchronized and the link has no error, MII_UP is determined to be true (i.e. 1), otherwise it is false (i.e. 0).

[0099] Putting the above three states PHY_RDY, PCS_SYNC, and MII_UP together forms a port state combination.

[0100] As a possible implementation manner, when the current state combination is obtained, the current state combination is directly compared with the stored historical port state combination to determine whether a state change occurs.

[0101] All port status combinations can be divided into two types: steady state and transient state. Steady state means that the state can be maintained for a long time without any changes on the local and remote devices. In contrast, transient state cannot be maintained even if the local and remote devices do not make any changes, and will eventually change to a steady state.

[0102] like Figure 8 As shown in the figure, a port state combination (MII_UP, PCS_SYNC, PHY_RDY) = (1,1,0) is a transient state, which occurs when the SerDes or PMA / PMD / medium signal jitters. Since the time is very short, the PCS has not yet generated enough bit errors, so the PCS maintains linkup and the MII also maintains linkup. However, this state cannot last, and there are two possible outcomes: one is that the jitter lasts long enough to cause a large number of bit errors in the PCS, then PCS_SYNC jumps to 0, and MII_UP also becomes 0; the other is that the jitter disappears, and all states return to all 1.

[0103] Because the transient state will inevitably fall back to a certain steady state, in order to reduce unnecessary processing, it can be Fig. 9 As shown, first analyze the current port status combination. Please refer to Fig. 9 , Fig. 9 The second flowchart of the port hierarchical control method provided in the embodiment of the present application is as follows. In this embodiment, after step S110, the method may further include step S120.

[0104] Step S120: whether the type of the current port state combination is a steady state.

[0105] Optionally, the characteristics of the current port state combination can be directly analyzed to determine whether the type of the current state combination is a steady state or a transient state. All steady state combinations can also be set in advance, and the current port state combination can be compared with each steady state combination. If the current port state combination is the same as one of the steady state combinations, the type of the current port state combination can be determined to be a steady state; otherwise, it can be determined to be a transient state.

[0106] like Fig.10 As shown, the steady-state port state combinations (MII_UP, PCS_SYNC, PHY_RDY) are: (0,0,0), (0,0,1), (0,1,1), (1,1,1). If the current port state combination is one of them, it can be determined that the type of the current port state combination is a steady state; otherwise, it is determined that the type of the current port state combination is a transient state.

[0107] When the type of the current port state combination is a steady state, the current port state combination is saved. When a new current state combination is obtained, the saved current port state combination is used as the historical port state combination for comparison, that is, the historical port state combination is updated, and step S130 is executed: according to the saved historical port state combination and the current port state combination, whether a state change occurs is determined. When the type of the current port state combination is a transient state, step S110 is executed again to obtain a new current state combination. That is, the collected transient state is directly discarded without any processing, and finally it is processed accordingly when it falls back to a certain steady state.

[0108] When it is determined that a state change occurs according to the saved historical port state combination and the current port state combination, Fig.11 The state change is analyzed in the manner shown to determine the target event triggered by the state change. Fig.11 , Fig.11 for Figure 3 Schematic diagram of the flow of sub-steps included in step S140. In this embodiment, step S140 may include sub-steps S141 to S143.

[0109] Sub-step S141, determining whether the state change from the historical port state combination to the current port state combination leads to link up or link down.

[0110] Sub-step S142, when the state change leads to link up, determining the target event as the up event of the top layer among the MII, PCS and SerDes.

[0111] Sub-step S143, when the state change leads to link down, determining the target event as the down event of the lowest layer among the MII, PCS and SerDes.

[0112] There are only two possible outcomes of the status change: the port is ready to connect to the other end and can start transmitting messages, which is called link up; conversely, the port connection is disconnected and cannot transmit messages, which is called link down.

[0113] When determining that a state change has occurred, if the state change is directed to link up, the up event of the top layer is reported; if the state change is directed to link down, the down event of the bottom layer is reported. Thus, 6 events can be extracted from the 3 states: PMA_UP, PCS_UP, MII_UP, MII_DOWN, PCS_DOWN, PMA_DOWN. Among them, the SerDes includes PMD and PMA, etc., the up event of the SerDes is the PMA_UP event, and the down event of the SerDes is the PMA_DOWN event.

[0114] For example, Fig.12 As shown in the figure, the historical port state combination (MII_UP, PCS_SYNC, PHY_RDY) is (0,0,1), the current port state combination (MII_UP, PCS_SYNC, PHY_RDY) is (0,1,1), and the state change from the historical port state combination to the current port state combination (i.e., 000→011) leads to link up, so it can be determined that the top-level up event needs to be reported; and the top-level up event among MII, PCS and SerDes is the up event of PCS, so it can be determined that the target event is the PCS_UP event.

[0115] For example, Fig.13 As shown in the figure, the historical port state combination (MII_UP, PCS_SYNC, PHY_RDY) is (1,1,1), the current port state combination (MII_UP, PCS_SYNC, PHY_RDY) is (0,0,1), and the state change from the historical port state combination to the current port state combination (i.e., 111→001) leads to link down, so it can be determined that the lowest layer down event needs to be reported; and the lowest layer down event among MII, PCS and SerDes is the down event of PCS, so it can be determined that the target event is the PCS_DOWN event.

[0116] When the XXX_UP event occurs, the RX reset of the upper layer module is unlocked; when the XXX_DOWN event occurs, the RX reset of the upper layer module is locked. In this way, various abnormal conditions can be effectively prevented, and the modules that do not need to be operated must be reset.

[0117] In this embodiment, the Fig.14 As shown, actions corresponding to various events are pre-configured, so that when an event is triggered, the corresponding action can be executed.

[0118] As a possible implementation method, it can be configured that no matter whether the target port is in forced mode or auto-negotiation mode, for a PMA_UP event, the corresponding action is PCS RX de-reset; for a PCS_UP event, the corresponding action is MII RX de-reset; for a MII_UP event, the corresponding action is MAC RX de-reset; for a MII_DOWN event, the corresponding action is MAC RX reset; for a PCS_DOWN event, the corresponding action is MII RX reset; and for a PMA_DOWN event, the corresponding action is PCS RX reset.

[0119] Thus, when the target port is configured in the mandatory mode or the auto-negotiation mode, after the target event is determined, the receiving end of the upper layer module of the target module is directly de-reset or reset according to the target event.

[0120] As another possible implementation, Fig.14 As shown in the configuration, no matter the port is in forced mode or auto-negotiation mode, for PMA_UP event, the corresponding action is PCS RX reset; for MII_UP event, the corresponding action is MAC RX reset; for MII_DOWN event, the corresponding action is MAC RX reset; for PCS_DOWN event, the corresponding action is MII RX reset; for PMA_DOWN event, the corresponding action is PCS RX reset.

[0121] in, Fig.14The action corresponding to the PCS_UP event in "Port forced mode: let MCU shield PHY_RDY and PCS_SYNC checks, start the link optimization process; enable auto-negotiation mode: MII RX reset" means that when the port is in forced mode, the PHY_RDY and PCS_SYNC checks are shielded, the PHY_RDY and PCS_SYNC states are directly set to 1, and the MII_UP state is detected. In this case, if the change corresponding to the detected state triggers the PCS_UP event, the link optimization process is started, that is, the link optimization process of SerDes is started, and the MII RX is reset after the optimization is completed; when the port is in auto-negotiation mode, the states of PHY_RDY, PCS_SYNC and MII_UP are detected. If the detected state triggers the PCS_UP event, the MII RX is reset.

[0122] In this way, when the target event is the up event of the PCS, if the target port is configured in forced mode, the link optimization process is started, and after completion, the receiving end of the upper layer module of the PCS is reset; when the target event is other events, the receiving end of the upper layer module of the target module is directly reset or reset.

[0123] Among them, starting the link optimization process at the PCS_UP event actually starts the optimization of SerDes according to the PCS state. This is because the standard has few regulations on SerDes and strongly relies on the private implementation of the manufacturer. In order to maximize compatibility, the above PCS is used as the reference state.

[0124] Whether the link optimization process is completed depends on the optimization completion status of SerDes. The prerequisite here is that even if SerDes is not optimized, it can provide a "decent" receiving bit error rate to the PCS enough for it to be up. This state depends on the default configuration of the SerDes equalizer having enough margin. This bit error rate is 10e-4. But this level is far from enough. In practical applications, it is generally required to reach the level of 10e-8, so from 10e-4 to 10e-8 is what needs to be optimized.

[0125] Generally speaking, optimization is a separate process, and what is being looked at here is its completion status. It does not mean that triggering an optimization will definitely result in a ber of 10e-8, nor does it mean that a linkup will be completed after triggering it once. This status only means that the optimization has been completed.

[0126] The above two configurations are the same except for the PCS_UP event. The difference between the actions corresponding to the PCS_UP event in the two configurations is that in the first configuration, no matter what mode the target port is in, the action corresponding to the PCS_UP event is MII RX de-reset; in the second configuration, in the forced mode, the action corresponding to the PCS_UP event is to start the link optimization process first, and then do MII RX de-reset after completion; in the auto-negotiation mode, the action corresponding to the PCS_UP event is MII RX de-reset.

[0127] Optionally, only one or two configurations may be configured in advance. In the case of configuring the above two types of information, it may be set based on which configuration the event is processed. The configuration may be selected by the user or specified by the user, and may be determined in combination with actual needs.

[0128] In the case where it is determined to use the first configuration, after the target event is determined, event processing is performed based on the first configuration: when the target event is the target module up event, the receiving end of the upper-layer module of the target module is reset; when the target event is the target module down event, the receiving end of the upper-layer module of the target module is reset.

[0129] If it is determined to use the second configuration, event processing can be performed based on the second configuration: (1) when the target event is an up event of the PCS, if the target port is configured in the forced mode, the link optimization process is started, and after completion, the receiving end of the upper-layer module of the PCS is reset; if the target port is configured in the auto-negotiation mode, the receiving end of the upper-layer module of the PCS is reset; (2) when the target event is an up event of other modules, the receiving end of the upper-layer module of the module is reset; when the target event is a down event of other modules, the receiving end of the upper-layer module of the module is reset.

[0130] Through this application, with states and events as the driving force, each module can be restored and tuned before sending and receiving user data, so as to be in the most suitable working state, and can effectively prevent fragmented messages from entering the chip, so as to achieve the purpose of decoupling between layers and improving the stability of port operation.

[0131] In order to execute the corresponding steps in the above embodiments and various possible methods, a method for implementing a port hierarchical control device 200 is provided below. Optionally, the port hierarchical control device 200 may adopt the above Figure 2 The device structure of the electronic device 100 is shown. Fig.15 , Fig.15A block diagram of a port hierarchical control device 200 provided in an embodiment of the present application. It should be noted that the basic principle and technical effects of the port hierarchical control device 200 provided in this embodiment are the same as those of the above-mentioned embodiments. For the sake of brief description, for parts not mentioned in this embodiment, reference can be made to the corresponding contents in the above-mentioned embodiments. In this embodiment, the ports include from top to bottom: MII, PCS and SerDes, and the port hierarchical control device 200 may include: a state collector 210, an event determiner 220 and an event processor 230.

[0132] The state collector 210 is used to obtain the states of the MII, PCS and SerDes of the target port respectively, so as to obtain the current port state combination of the target port.

[0133] The state collector 210 is further used to determine whether a state change occurs according to the saved historical port state combination and the current port state combination.

[0134] The event determiner 220 is used to determine the target event corresponding to the state change when the state change occurs, wherein the target event is the up event of the uppermost layer or the down event of the lowermost layer in the MII, PCS and SerDes.

[0135] The event processor 230 is used to reset or unreset the receiving end of the upper layer module of the target module in the target event according to the target event. When the target event is the up event of the target module, the receiving end is reset, and when the target event is the down event of the target module, the receiving end is reset.

[0136] Alternatively, the event processor 230 is used to start the link optimization process when the target event is an up event of the PCS, if the target port is configured in the forced mode; if the target port is configured in the auto-negotiation mode, then the receiving end of the upper layer module of the PCS is reset. And when the target event is an up event of other modules, the receiving end of the upper layer module of the module is reset; when the target event is a down event of other modules, the receiving end of the upper layer module of the module is reset.

[0137] Optionally, in this embodiment, before judging whether a state change occurs based on the saved historical port state combination and the current port state combination, the state collector 210 is further used to: judge whether the type of the current port state combination is a steady state or a transient state. When the type of the current port state combination is a steady state, the state collector 210 judges whether a state change occurs based on the saved historical port state combination and the current port state combination. When the type of the current port state combination is a transient state, the state collector 210 obtains the current port state combination of the target port again.

[0138] As a possible implementation, the state collector 210 is continuously operated in an embedded microcontroller (Micro Control Unit, MCU) to timely discover changes in the link states of each layer.

[0139] The MCU maintains an active port list, which records the key status of all currently active ports (i.e., target ports): (PHY_RDY, PCS_SYNC, MII_UP). The active ports are transmitted from the CPU (Central Processing Unit) to the MCU through the in-chip message mechanism.

[0140] The MCU main thread continuously polls the status of each module according to the mapping relationship between the port and the module. When a transient state is read, it is discarded; when a steady state is read, it is compared with the previous state. If there is a change, it is updated to the active port status list and a status change notification message is sent to the CPU.

[0141] The event determiner 220 can be deployed in the driver of the Ethernet chip and run on the main CPU of the device. Based on the rules for identifying state changes and triggering events described above, the state changes are determined as corresponding events, and then the event processor 230 is called to perform corresponding actions.

[0142] The event processor 230 performs corresponding configuration actions on the port according to the reported event.

[0143] Optionally, the above modules can be stored in the form of software or firmware. Figure 2 The memory 110 shown in the figure may be fixed in the operating system (OS) of the electronic device 100 and may be Figure 2 Meanwhile, the data and program codes required for executing the above modules may be stored in the memory 110.

[0144] The embodiment of the present application also provides a readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the port hierarchical control method is implemented.

[0145] In summary, the embodiments of the present application provide a port hierarchical control method, device, electronic device and readable storage medium. When there is a state change between the current port state combination composed of the current states of the MII, PCS and SerDes of the target port and the saved historical port state combination, the target event corresponding to the state change is determined; then, based on the target time, the receiving end of the upper layer module of the target module in the target event is reset or reset. Wherein, the target event is the up event of the top layer or the down event of the bottom layer in the MII, PCS and SerDes; wherein, when the target event is the up event of the target module, the reset is performed, and when the target event is the down event of the target module, the reset is performed. In this way, by enabling the upper module after the lower module is in the best working state, the bit error rate can be effectively reduced, and fragmented messages can be prevented from entering the chip, thereby reducing fragments and abnormal packets, and achieving the purpose of decoupling between layers and improving the stability of port operation.

[0146] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0147] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0148] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0149] The above description is only an optional embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A port hierarchical control method, It is characterized in that The port includes, from top to bottom, a medium independent interface MII, a physical coding sublayer PCS, and a deserializer SerDes. The method includes: Respectively obtain the states of the MII, PCS and SerDes of the target port to obtain the current port state combination of the target port; Determine whether a state change occurs according to the saved historical port state combination and the current port state combination; When a state change occurs, determining a target event corresponding to the state change, wherein the target event is an up event of the uppermost layer or a down event of the lowermost layer in the MII, PCS and SerDes; According to the target event, the receiving end of the upper layer module of the target module in the target event is de-reset or reset, wherein when the target event is the target module up event, the de-reset is performed, and when the target event is the target module down event, the reset is performed.

2. The method according to claim 1, It is characterized in that When a state change occurs, determining a target event corresponding to the state change includes: Determine whether the state change from the historical port state combination to the current port state combination leads to link up or link down; When the state change leads to link up, determining the target event as the up event of the uppermost layer among the MII, PCS and SerDes; When the state change leads to link down, the target event is determined to be a down event of the lowest layer among the MII, PCS and SerDes.

3. The method according to claim 1, It is characterized in that The SerDes includes a physical medium dependent sublayer PMD and a physical medium access sublayer PMA. The up event of the SerDes is a PMA_UP event, and the down event of the SerDes is a PMA_DOWN event.

4. The method according to claim 1, It is characterized in that Before determining whether a state change occurs based on the saved historical port state combination and the current port state combination, the method further includes: Determine whether the type of the current port state combination is a steady state or a transient state; When the type of the current port state combination is a steady state, executing the step of determining whether a state change occurs based on the saved historical port state combination and the current port state combination; When the type of the current port state combination is transient, the step of respectively obtaining the states of the MII, PCS and SerDes of the target port to obtain the current port state combination of the target port is performed.

5. The method according to any one of claims 1 to 4, It is characterized in that When the target port is configured in the auto-negotiation mode, obtaining the state of the SerDes of the target port includes: Detecting whether the phase-locked loop of the SerDes is correctly locked; Detecting whether the receiving end of the SerDes can recover a valid signal; Detecting whether the equalizer at the receiving end of the SerDes is adjusted; Detecting whether the transmitting end of the SerDes has completed training; Determine whether the SerDes link establishment is completed according to the detected state; When the target port is configured in the forced mode, obtaining the state of the SerDes includes: It is determined that the SerDes link establishment is completed.

6. The method according to any one of claims 1 to 4, It is characterized in that The obtaining of the state of the MII of the target port includes: Obtaining the status of the PCS; Obtaining the link status of the MII; Obtaining the state of the MII according to the state of the PCS and the link state of the MII; When the target port is configured in the auto-negotiation mode, obtaining the PCS status of the target port includes: Obtain block lock status and high bit error rate status; According to the block lock state and the high bit error rate state, the state of the PCS is obtained; When the target port is configured in the forced mode, obtaining the PCS status of the target port includes: It is determined that the PCS is synchronized.

7. The method according to any one of claims 1 to 4, It is characterized in that The step of de-resetting or resetting the receiving end of the upper layer module of the target module in the target event according to the target event includes: When the target port is configured in the mandatory mode or the auto-negotiation mode, directly de-reset or reset the receiving end of the upper layer module of the target module according to the target event; or, When the target event is the up event of the PCS, if the target port is configured in forced mode, the link optimization process is started, and after completion, the receiving end of the upper layer module of the PCS is reset; when the target event is other events, the receiving end of the upper layer module of the target module is directly reset or reset.

8. A port hierarchical control device, It is characterized in that The port includes from top to bottom: a medium independent interface MII, a physical coding sublayer PCS and a deserializer SerDes, and the device includes: A state collector, used to obtain the states of the MII, PCS and SerDes of the target port respectively, so as to obtain the current port state combination of the target port; The state collector is further used to determine whether a state change occurs based on the saved historical port state combination and the current port state combination; An event determiner, used for determining a target event corresponding to the state change when a state change occurs, wherein the target event is an up event of the uppermost layer or a down event of the lowermost layer in the MII, PCS and SerDes; An event processor is used to, according to the target event, de-reset or reset the receiving end of the upper layer module of the target module in the target event, wherein when the target event is the up event of the target module, de-reset is performed, and when the target event is the down event of the target module, reset is performed.

9. An electronic device, It is characterized in that The invention comprises a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor can execute the machine executable instructions to implement the port hierarchical control method according to any one of claims 1 to 7.

10. A readable storage medium having a computer program stored thereon, It is characterized in that When the computer program is executed by a processor, the port hierarchical control method according to any one of claims 1 to 7 is implemented.

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