Semiconductor structure and manufacturing method thereof, and memory

Abstract

The embodiments of the present application relate to the semiconductor field, and provide a semiconductor structure and a manufacturing method thereof, and a memory. The semiconductor structure may at least include: a first grating, a second grating, and a third grating stacked from bottom to top and arranged in different photolithography layers, the overlay mark areas for setting the gratings in different photolithography layers overlap, the first grating, the second grating, and the third grating are all periodic structures, the center distance between adjacent gratings in the periodic structure is the grating period, and the grating width and / or the grating period of the first grating and the second grating are different. The embodiments of the present application are conducive to improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present application relate to the semiconductor field, and in particular to a semiconductor structure and a manufacturing method thereof, and a memory. Background Art

[0002] The photolithography process is a process of transferring the mask pattern to the wafer through a series of steps such as alignment and exposure. In the process of semiconductor device manufacturing, multiple photolithography processes are usually required to achieve overlay. However, due to various factors in the photolithography process that cannot reach the ideal state, it is inevitable that the pattern left on the wafer after exposure and development cannot be completely aligned with the existing pattern on the wafer. Therefore, it is necessary to accurately measure the offset between the pattern left on the wafer after exposure and development and the existing pattern on the wafer, that is, the overlay error, so that the overlay error can be effectively compensated and corrected in the subsequent process, so that the final semiconductor device has the expected effect. Summary of the invention

[0003] The embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, and a memory, which are at least beneficial to improving the electrical performance of the semiconductor structure and the memory.

[0004] According to some embodiments of the present application, on the one hand, the embodiments of the present application provide a semiconductor structure, which may include at least: a first grating, a second grating and a third grating stacked from bottom to top and arranged in different photolithography layers, the overlay mark areas for setting the gratings in different photolithography layers overlap, the first grating, the second grating and the third grating are all periodic structures, the center distance between adjacent gratings in the periodic structure is the grating period, and the grating width and / or the grating period of the first grating and the second grating are different.

[0005] In addition, the first grating and the second grating are located in different adjacent photolithography layers.

[0006] In addition, the first grating, the second grating and the third grating are all composed of periodically arranged gaps, protrusions or holes.

[0007] In addition, the photolithography layer includes a core area and a peripheral area, the peripheral area is located between the core area and the cutting road, and the overlay mark area is located in the peripheral area.

[0008] In addition, the semiconductor structure also includes: a first pattern and a second pattern in the core area, the first pattern and the first grating are in the same photolithography layer, the second pattern and the second grating are in another photolithography layer, the first grating and the first pattern are grating structures with the same grating width and grating period, and the second grating and the second pattern are grating structures with different grating width and / or grating period.

[0009] In addition, the first pattern includes a word line.

[0010] In addition, the second pattern includes a capacitor contact hole.

[0011] In addition, the grating width and the grating period of the second grating are the same as the grating width and the grating period of the third grating.

[0012] In addition, the center position of the second grating is offset from the center position of the first grating in the vertical direction, and the second grating and the first grating do not overlap in the vertical direction.

[0013] In addition, the grating period of the second grating is greater than the grating period of the first grating, and the center position of the second grating serves as the center position of a portion of the gratings in the first grating.

[0014] In addition, the grating width of the second grating is greater than the grating width of the first grating.

[0015] In addition, the grating width of the second grating is less than or equal to twice the grating width of the first grating.

[0016] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a memory, comprising any semiconductor structure described above.

[0017] According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a method for manufacturing a semiconductor structure, the method for manufacturing a semiconductor structure at least includes: forming a first grating, a second grating and a third grating stacked from bottom to top and arranged in different photolithography layers, the overlay mark areas for setting the gratings in different photolithography layers overlap, the first grating, the second grating and the third grating are all periodic structures, the center distance between adjacent gratings in the periodic structure is the grating period, and the grating width or the grating period of the first grating is different from that of the second grating.

[0018] In addition, it also includes: forming a second pattern, the second grating and the second pattern are in the same photolithography layer, the second pattern and the second grating are grating structures with different grating periods, and the grating width of the second grating is greater than the grating width of the second pattern.

[0019] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0020] In the above technical solution, setting the grating width and / or grating period of the first grating and the second grating to be different is conducive to making the characteristics of the diffraction signal obtained by illuminating the first grating and the second grating different, thereby distinguishing the diffraction signal of the first grating and the diffraction signal of the second grating, avoiding taking the diffraction signal of the first grating and the diffraction signal of the second grating as a whole as the diffraction signal of the second grating, ensuring that the diffraction signal used to calculate the overlay error is composed of only the diffraction signal of the second grating and the diffraction signal of the third grating, thereby realizing accurate measurement of the overlay error. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0022] Figures 1 to 4 A schematic diagram of the structure of a semiconductor structure provided in an embodiment of the present application;

[0023] Figures 5 to 9 This is a structural schematic diagram of some steps in the method for manufacturing a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The detection of overlay error is generally divided into after development inspection (ADI) and after etching inspection (AEI). After development inspection refers to the measurement of critical dimension (CD) after development, which is generally used to detect the performance indicators of exposure machine and developer. After exposure and development are completed, the ADI machine conducts a qualitative inspection on the generated graphics to determine whether the graphics are normal. Since it cannot be measured by transmitted light, ADI is generally measured by electron beam or scanning electron microscope. After etching inspection refers to the CD measurement after etching. Before and after the removal of photoresist in the etching process, the product is fully inspected or sampled.

[0025] Overlay error can generally be measured by image recognition-based measurement technology (Image Based Overlay, IBO), scanning electron microscope (SEM) and new diffraction measurement technology (In Die Metrology, IDM). IDM collects zero-order diffraction light from different marking layers and determines the overlay error of different marking layers based on the asymmetry of the intensity distribution of the zero-order diffraction light.

[0026] The present application provides a semiconductor structure, in which a first grating and a second grating are provided with different grating widths and / or grating periods, so as to distinguish a diffraction signal corresponding to the first grating from a diffraction signal corresponding to the second grating. When measuring an overlay error of a third grating relative to the second grating, since the first grating located below the second grating also has a corresponding diffraction signal, by controlling the diffraction signal corresponding to the first grating and the diffraction signal corresponding to the second grating to have different characteristics, it is beneficial to ensure that the diffraction signal used for calculating the overlay error is composed of only the diffraction signal of the second grating and the diffraction signal of the third grating, thereby achieving accurate measurement of the overlay error.

[0027] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0028] Figures 1 to 4 A schematic diagram of the structure of a semiconductor structure provided in an embodiment of the present application.

[0029] refer to Figure 1 The semiconductor structure includes: a first grating 111, a second grating 211 and a third grating 311 stacked from bottom to top and arranged in different lithography layers, the overlay mark areas of the gratings arranged in different lithography layers overlap, the first grating 111, the second grating 211 and the third grating 311 are all periodic structures, the center distance between adjacent gratings in the periodic structure is the grating period, and the grating width and / or grating period of the first grating 111 and the second grating 211 are different.

[0030] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings.

[0031] The semiconductor structure includes a first photolithography layer 10, a second photolithography layer 20 and a third photolithography layer 30 stacked from bottom to top, the first photolithography layer 10 has a first overlay mark area 11, the second photolithography layer 20 has a second overlay mark area 21, the third photolithography layer 30 has a third overlay mark area 31, the first grating 111 is located in the first overlay mark area 11, the second grating 211 is located in the second overlay mark area 21, and the third grating 311 is located in the third overlay mark area 31. The first grating 111, the second grating 211 and the third grating 311 are all overlay marks, and in the stacking direction of the photolithography layers, the projections of the first overlay mark area 11 and the second overlay mark area 21 at least partially overlap.

[0032] It is understandable that due to the limited chip area, the overlay mark areas of different film layers often overlap in the film layer stacking direction. When using IDM to measure the overlay error of the upper film layer, the measurement result may be affected by the lower film layer. The exemplary scenario is as follows:

[0033] When illumination is applied above the third photolithography layer 30, part of the light passes through the third photolithography layer 30 and is reflected, and the reflected light is diffracted by the third grating 311 to form a third diffraction signal; part of the light passes through the third photolithography layer 30 and the second photolithography layer 20 in sequence and is reflected, and the reflected light is diffracted by the second grating 211 to form a second diffraction signal; part of the light passes through the third photolithography layer 30, the second photolithography layer 20 and the first photolithography layer 10 in sequence and is reflected, and the reflected light is diffracted by the first grating 111 to form a first diffraction signal. When the first grating 111 and the second grating 211 are periodic structures with the same grating width and grating period, the characteristics of the first diffraction signal and the second diffraction signal are the same. The technician cannot effectively distinguish the first diffraction signal from the second diffraction signal and can only regard the first diffraction signal and the second diffraction signal as a whole as the "second diffraction signal". That is, when measuring the overlay error between the third grating 311 and the second grating 211, what is actually measured is the overlay error between the equivalent structure of the first grating 111 and the second grating 112 and the third grating 311.

[0034] If the first grating 111 and the second grating 211 are completely aligned, the first diffraction signal is the same as the second diffraction signal, and the first diffraction signal will not interfere with the technician's identification of the second diffraction signal; if there is a deviation between the first grating 111 and the second grating 211, the actual positions of the first diffraction signal and the second diffraction signal are different, but since the first diffraction signal and the second diffraction signal have the same parameters (width and spacing) except for the position, the technician cannot distinguish between the first diffraction signal and the second diffraction signal and can only take the first diffraction signal and the second diffraction signal as a whole as the "second diffraction signal". At this time, the measurement result may be biased.

[0035] It is understandable that as the deviation between the first grating 111 and the second grating 211 gradually increases, the accuracy of the measurement result becomes lower and lower. Ideally, the first grating 111 and the second grating 211 are completely aligned, at which point the measured offset is the same or similar to the actual offset, for example, the difference does not exceed 0.5nm; as the difference between the first grating 111 and the second grating 211 increases to 2.5nm or even 5nm, the difference between the measured offset and the actual offset may increase to 1nm or even 2nm, at which point the measured offset is basically invalid.

[0036] It should be noted that the second diffraction signal will also be transmitted through the third photolithography layer 30, and the first diffraction signal will also be transmitted through the second photolithography layer 20 and the third photolithography layer 30, but since the first diffraction signal and the second diffraction signal are not parallel rays, and the grating width is generally much larger than the grating gap, most of the first diffraction signal and the second diffraction signal are transmitted through the upper film layer instead of being diffracted again, so the positions of the first diffraction signal and the second diffraction signal will not change or will change slightly, and the main change is the signal intensity (blocked by the film layer, the signal intensity becomes weaker). In addition, since the measured offset is a relative value (relative to the zero offset), the influence caused by the second photolithography layer 20 and the third photolithography layer 30 will be eliminated by the subtraction calculation of the relative value.

[0037] In an embodiment of the present application, the third photolithography layer 30 is a photolithography layer to be tested, the second photolithography layer 20 is a reference photolithography layer, the first photolithography layer 10 is an existing interference photolithography layer, the first photolithography layer 10 and the second photolithography layer 20 are adjacent or non-adjacent photolithography layers, and the second photolithography layer 20 and the third photolithography layer 30 are adjacent or non-adjacent photolithography layers.

[0038] In some embodiments, the first photolithography layer 10 and the second photolithography layer 20 are adjacent, that is, the first grating 111 and the second grating 211 are in different adjacent photolithography layers. When the first photolithography layer 10 and the second photolithography layer 20 are adjacent, the light intensity loss suffered by the first diffraction signal when transmitted to the top of the second photolithography layer 20 is small, and the impact on the second diffraction signal is large. At this time, it is necessary to adjust the signal characteristics of the second diffraction signal with a larger amplitude to effectively distinguish the first diffraction signal from the second diffraction signal.

[0039] In some embodiments, reference Figure 2 , the first grating 111 and the second grating 211 are in separate different lithography layers, at least a fourth lithography layer 40 is disposed between the first lithography layer 10 and the second lithography layer 20, the fourth lithography layer 40 has a fourth overlay mark region 41 and a fourth grating 411 disposed in the fourth overlay mark region 41, the fourth grating 411 is located between the first grating 111 and the second grating 211, the arrangement direction of the first grating 111 is parallel to the arrangement direction of the second grating 211, and the arrangement direction of the fourth grating 411 is perpendicular to the arrangement direction of the second grating 211. The fourth grating 411 is provided to reduce the light transmitted to the first lithography layer 10, and to suppress the first diffraction signal from propagating to the second lithography layer 20, so that the first diffraction signal finally transmitted from the third lithography layer 30 has a lower light intensity, thereby weakening or even eliminating the influence of the first diffraction signal on the second diffraction signal.

[0040] It is understandable that other intermediate film layers may be provided between the first photolithography layer 10 and the second photolithography layer 20. Due to the obstruction of the intermediate film layer, if the light intensity loss of the first diffraction signal during the propagation process is large, the influence of the first diffraction signal is small, and the difference between the first grating 111 and the second grating 211 may be small. In other words, the characteristic difference between the first grating 111 and the second grating 211 may be adjusted according to the loss of the first diffraction signal during the transmission process, and the characteristic difference includes the grating width difference and / or the grating period difference.

[0041] In different embodiments, the grating may have different manifestations. The grating may be composed of periodically arranged gaps, bumps or holes, or in other words, the grating contains periodically arranged gaps, bumps or holes. It is understandable that, affected by the manufacturing process, the middle part of the grating generally follows a more stringent periodic distribution, that is, the spacing between adjacent gratings is equal, the edge part of the grating has poor periodicity, and the distance between adjacent gratings may show a trend of gradually increasing or decreasing. Since this is a phenomenon formed by the limitation of the current process level, it cannot be used as evidence that it does not belong to a grating.

[0042] In addition, it can be understood that there may be multiple groups of gratings in the same overlay mark area, and the multiple groups of gratings have at least two arrangement directions, which are used to detect the offset of the measured photolithography layer compared with the reference photolithography layer in different directions, and the arrangement directions of different groups of gratings can be vertical or oblique. Among them, the expression forms of different groups of gratings can be the same or different. When the overlay mark includes a hole array, it can be considered that the overlay mark includes multiple groups of gratings with different arrangement directions, and there is a common hole between the two groups of gratings.

[0043] In some embodiments, the photolithography layer includes a core area and a peripheral area, the peripheral area is located between the core area and the cutting path, and the overlay mark area is located in the peripheral area. The peripheral area generally refers to the blank area between the core component and the cutting path. With the miniaturization of the semiconductor structure and the complexity of the core component, the area of ​​the blank area may gradually shrink, and the overlay marks of different film layers are more likely to overlap in the projection direction of the film layer stacking. It can be understood that the first overlay mark area 11, the second overlay mark area 21 and the third overlay mark area 31 are all overlay mark areas, and are all located in the peripheral area.

[0044] In some embodiments, the semiconductor structure further includes: a first pattern 112 and a second pattern 212 in the core region, the first pattern 112 and the first grating 111 are in the same lithography layer, the second pattern 212 and the second grating 211 are in another lithography layer, the first grating 111 and the first pattern 112 are grating structures with the same grating width and grating period, and the second grating 211 and the second pattern 212 are grating structures with different grating widths and / or grating periods. That is, the embodiment of the present application adjusts the grating width and / or grating period of the second grating 211 so that the diffraction signal of the second grating 211 is different from the diffraction signal of the first grating 111, thereby accurately obtaining the offset of the second lithography layer 20 and the third lithography layer 30 according to the diffraction signal of the second grating 211 and the diffraction signal of the third grating 311.

[0045] In order to accurately measure the overlay error of the second photolithography layer 20 and the third photolithography layer 30, the grating width and grating period of the second grating 211 can be set to be the same as the grating width and grating period of the third grating 311. In this context, if the grating width and / or grating period of the second grating 211 is adjusted, the grating width and / or grating period of the third grating 311 needs to be adjusted synchronously to ensure that the measurement of the overlay error has a high accuracy. Since the process steps of the peripheral area are the same as those of the core area, and the first grating 111 is at the bottom layer relative to the second grating 211 and the third grating 311, the second grating 211 and the third grating 311 are adjusted while keeping the characteristics of the first grating 111 unchanged, which is conducive to reducing the impact on the subsequent film layer process steps and reducing the adjustment cost.

[0046] In other embodiments, the second grating 211 and the second pattern 212 are grating structures with the same grating width and grating period, and the first grating 111 and the first pattern 112 are grating structures with different grating widths and / or grating periods, that is, the grating width and / or grating period of the first grating 111 are adjusted, and the grating width and grating period of the second grating 211 are kept unchanged. Since the number of film layers between the first photolithography layer 10 and the second photolithography layer 20 and between the second photolithography layer 20 and the third photolithography layer 30 may be different according to the application scenario, in the actual process, the characteristics of the first grating 111 can be adjusted according to actual needs, or the characteristics of the second grating 211 and the third grating 311 can be adjusted to reduce the impact on the overall film layer process and reduce costs.

[0047] In some embodiments, reference Figure 3, the center position aa of the second grating 211 is misaligned with the center position bb of the first grating 111 in the vertical direction, and the second grating 211 does not overlap with the first grating 111 in the vertical direction. In the case where the center position bb of the first grating 111 is misaligned with the center position aa of the second grating 211, by controlling the second grating 211 to not overlap with the first grating 111 in the vertical direction, it is helpful to avoid the overlap of diffraction signals caused by grating overlap, thereby accurately distinguishing the first diffraction signal from the second diffraction signal. Among them, the vertical direction refers to the stacking direction of the first photolithography layer 10 and the second photolithography layer 20, the center position of the grating refers to the central axis or central axis plane of each grating in the grating arrangement direction, and multiple gratings constitute the above-mentioned first grating 111, second grating 211 and third grating 311.

[0048] In some embodiments, the second grating 211 and the first grating 111 do not overlap in the vertical direction, which means that, in the arrangement direction of the first grating 111, there is a gap between the first grating 111 and the second grating 211, which is helpful to further distinguish the first diffraction signal and the second diffraction signal, and avoid the first diffraction signal and the second diffraction signal being indistinguishable due to being continuous; in other embodiments, the second grating 211 and the first grating 111 do not overlap in the vertical direction, which means that, in the arrangement direction of the first grating 111, the boundaries of the first grating 111 and the second grating 211 coincide with each other.

[0049] In some embodiments, the center position of the grating in the second pattern 212 is misaligned with the center position of the grating in the first pattern 112 in the vertical direction, and the second pattern 212 at least partially overlaps with the first pattern 112 in the vertical direction. It is understandable that if the grating features of the second grating 211 are different from the grating features of the second pattern 212, the second pattern 212 and the second grating 211 cannot be formed by the same mask. Therefore, in the actual production process, the peripheral area can be covered first to form the second pattern 212 in the core area first, and then the core area is covered, and the second grating 211 in the peripheral area is formed later. In other words, the second pattern 212 and the second grating 211 are formed respectively by different exposure, development and etching processes.

[0050] In some embodiments, reference Figure 4 , the grating period of the second grating 211 is greater than the grating period of the first grating 111, and the center position of the second grating 211 serves as the center position of a portion of the gratings in the first grating 111. In the case where the center position of the second grating 211 serves as the center position of the first grating 111, controlling the first grating 111 and the second grating 211 to have different grating periods is beneficial to distinguishing the first diffraction signal and the second diffraction signal formed based on the first grating 111 and the second grating 211.

[0051] Continue to refer Figure 4In some embodiments, the grating width of the second grating 211 is greater than the grating width of the first grating 111. On the basis of changing the grating period of the second grating 211, the grating width of the second grating 211 is further adjusted, which is beneficial to further distinguish the first diffraction signal from the second diffraction signal; in other embodiments, the grating width of the second grating 211 is less than the grating width of the first grating 111. Taking the second grating 211 as an example, the grating width of the second grating 211 is the width d of each grating in the grating arrangement direction.

[0052] In some embodiments, the grating width of the second grating 211 is less than or equal to twice the grating width of the first grating 111, or in other words, the grating width of the second grating 211 is less than or equal to twice the grating width of the second pattern 212. Setting the grating width of the second grating 211 and the grating width of the second pattern 212 to have the above relationship is conducive to forming the second pattern 212 and the second grating 211 in the same process step, reducing the influence of the adjustment of the second grating 211 on the film preparation process, thereby reducing the process cost of the semiconductor structure.

[0053] In some embodiments, the first pattern 112 includes a word line. For example, the word line may be a buried word line. In some embodiments, the second pattern 212 may be a bit line conductive layer or a capacitor contact hole.

[0054] In the embodiment of the present application, setting the grating width and / or grating period of the first grating and the second grating to be different is conducive to making the characteristics of the diffraction signals obtained by illuminating the first grating and the second grating different, thereby distinguishing the diffraction signal of the first grating from the diffraction signal of the second grating, avoiding taking the diffraction signal of the first grating and the diffraction signal of the second grating as a whole as the diffraction signal of the second grating, ensuring that the diffraction signal used to calculate the overlay error is composed of only the diffraction signal of the first grating and the diffraction signal of the second grating, thereby achieving accurate measurement of the overlay error.

[0055] Accordingly, the embodiment of the present application further provides a memory device, comprising any of the semiconductor structures described above. Since the semiconductor structure can accurately measure the offset between the photolithography layer where the second grating is located and the photolithography layer where the third grating is located, and then adjust and correct it through subsequent process steps, the memory device prepared based on the semiconductor structure has better electrical performance.

[0056] Accordingly, the present application also provides a method for manufacturing a semiconductor structure, referring to Figure 1The manufacturing method of the semiconductor structure includes: forming a first grating 111, a second grating 211 and a third grating 311 which are stacked from bottom to top and arranged in different lithography layers, the overlay mark areas for setting the gratings in different lithography layers overlap, the first grating 111, the second grating 211 and the third grating 311 are all periodic structures, the center distance between adjacent gratings in the periodic structure is the grating period, and the grating width or grating period of the first grating 111 is different from that of the second grating 211.

[0057] In some embodiments, reference Figure 4 The second pattern 212 and the second grating 211 are formed respectively by different exposure, development and etching processes. The second grating 211 and the second pattern 212 are in the same photolithography layer. The second pattern 212 and the second grating 211 are grating structures with different grating periods. The grating width of the second grating 211 is greater than the grating width of the second pattern 212.

[0058] The details are as follows:

[0059] refer to Figure 4 and Figure 5 , using different masks, respectively exposing and developing to form a first mask 212a and a second mask 211a, the first mask 212a is used to form the second pattern 212, and the second mask 211a is used to form the second grating 211; performing a deposition process, forming a pattern layer 212b and a grating layer 211b at the same time, when the opening width of the second mask 211a is less than or equal to twice the thickness of the pattern layer 212b, the grating layer 211b fills the opening of the second mask 211a. In an exemplary embodiment, the opening width of the second mask 211a is greater than the thickness of the pattern layer 212b and less than or equal to twice the thickness of the pattern layer 212b.

[0060] refer to Figure 6 , a maskless dry etching process is performed to remove the pattern layer 212b covering the top surface of the first mask 212a and the bottom of the opening of the first mask 212a to form a first sacrificial layer 212c, and to remove the grating layer 211b higher than the top surface of the second mask 211a to form a second sacrificial layer 211c.

[0061] refer to Figure 7 , perform an etching process to remove the first mask 212a and the second mask 211a, and retain the first sacrificial layer 212c and the second sacrificial layer 211c; perform a deposition process to form a third mask 212d that fills the gaps in the first sacrificial layer 212c and a fourth mask 211d that fills the gaps in the second sacrificial layer 211c.

[0062] Since the opening width of the second mask 211a is greater than the thickness of the pattern layer 212b and is less than or equal to twice the thickness of the pattern layer 212b, and the opening width of the first mask 212a is greater than twice the thickness of the pattern layer 212b, the opening width of the first mask 212a is greater than the opening width of the second mask 211a. In order to make the opening width of the second mask 211a smaller while the overall total width remains unchanged, it is necessary to set the width of a single mask strip in the second mask 211a to be greater than the width of a single mask strip in the first mask 212a. In other words, the opening width of the third mask 212d is smaller than the opening width of the fourth mask 211d, the grating width of the third mask 212d is smaller than the grating width of the fourth mask 211d, and the period of the third mask 212d is smaller than the period of the fourth mask 211d. The third mask 212d and the fourth mask 211d are used to etch the conductive layer 51 below to form a bit line conductive layer.

[0063] refer to Figure 8 , remove the first sacrificial layer 211c and the second sacrificial layer 212c, and use the third mask 212d and the fourth mask 211d to perform an etching process on the conductive layer 51 to form a first bit line conductive layer 512 located in the functional area and a second bit line conductive layer 511 located in the peripheral area. Since the grating features of the first bit line conductive layer 512 are the same as the grating features of the third mask 212d, and the grating features of the second bit line conductive layer 511 are the same as the grating features of the fourth mask 211d, the opening width of the first bit line conductive layer 512 is smaller than the opening width of the second bit line conductive layer 511.

[0064] refer to Fig. 9 A first sidewall 513 is formed on the sidewall of the first bit line conductive layer 512, and a second sidewall 514 is formed on the sidewall of the second bit line conductive layer 511; a first capacitor contact hole is formed to fill the gap between adjacent first bit line conductive layers 512 to serve as the second pattern 212, and a second capacitor contact hole is formed to fill the gap between adjacent second bit line conductive layers 511 to serve as the second grating 211.

[0065] The first sidewall 513 and the second sidewall 514 can be formed by the same deposition process, and the thickness of the first sidewall 513 is the same as the thickness of the second sidewall 514. When the opening width of the first bitline conductive layer 512 is smaller than the opening width of the second bitline conductive layer 511, and the thickness of the first sidewall 513 is the same as the thickness of the second sidewall 514, the grating width of the second pattern 212 is smaller than the grating width of the second grating 211.

[0066] In addition, the first capacitor contact hole and the second capacitor contact hole can also be formed by the same deposition process. The first capacitor contact hole in the functional area is used to connect the drain of the word line to play an electrical connection role, and the second capacitor contact hole in the peripheral area may not be connected to the drain of the word line and is only used as an overlay mark. The buried word line 60 in the functional area can be used as a first pattern, and the buried word line 60 in the peripheral area can be used as a first grating.

[0067] In other embodiments, after forming the first bit line conductive layer and the second bit line conductive layer, the first bit line conductive layer and the second bit line conductive layer are processed in situ to form the first sidewall and the second sidewall for isolation, such as the doped polysilicon of the bit line conductive layer, and the doped polysilicon is oxidized or nitrided to form silicon oxide or silicon nitride for electrical isolation; after forming the first sidewall and the second sidewall, a conductive material can be filled to form the first capacitor contact hole and the second capacitor contact hole. In this case, the width of the first capacitor contact hole is equal to the thickness of the pattern layer, and the width of the second capacitor contact hole is equal to the opening width of the second mask, that is, the width of the second capacitor contact hole is greater than the width of the first capacitor contact hole and less than or equal to twice the width of the first capacitor contact hole.

[0068] The width of the first capacitor contact hole may also be equal to the width of the buried word line. In this case, the width of the second capacitor contact hole is greater than the width of the buried word line and less than or equal to twice the width of the buried word line.

[0069] In the embodiment of the present application, setting the grating width and / or grating period of the first grating and the second grating to be different is conducive to making the characteristics of the diffraction signals obtained by illuminating the first grating and the second grating different, thereby distinguishing the diffraction signal of the first grating from the diffraction signal of the second grating, avoiding taking the diffraction signal of the first grating and the diffraction signal of the second grating as a whole as the diffraction signal of the second grating, ensuring that the diffraction signal used to calculate the overlay error is composed of only the diffraction signal of the first grating and the diffraction signal of the second grating, thereby achieving accurate measurement of the overlay error.

[0070] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the present application. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present application, so the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that: include: A first grating, a second grating and a third grating stacked from bottom to top and arranged in different photolithography layers, overlay mark regions for arranging the gratings in different photolithography layers overlap, the first grating, the second grating and the third grating are all periodic structures, the center distance between adjacent gratings in the periodic structure is the grating period, and the grating width and / or the grating period of the first grating and the second grating are different; The center position of the second grating is offset from the center position of the first grating in the vertical direction, the second grating and the first grating do not overlap in the vertical direction, and there is a gap between the first grating and the second grating, and the grating width of the second grating is greater than the grating width of the first grating and is less than or equal to twice the grating width of the first grating.

2. The semiconductor structure according to claim 1, characterized in that: The first grating and the second grating are located in different adjacent photolithography layers.

3. The semiconductor structure according to claim 1, characterized in that: The first grating, the second grating and the third grating are all composed of periodically arranged gaps, protrusions or holes.

4. The semiconductor structure according to claim 1, characterized in that The photolithography layer includes a core area and a peripheral area, wherein the peripheral area is located between the core area and the cutting path, and the overlay mark area is located in the peripheral area.

5. The semiconductor structure according to claim 4, characterized in that: Also includes: The first pattern and the second pattern are located in the core area, the first pattern and the first grating are located in the same photolithography layer, the second pattern and the second grating are located in another photolithography layer, the first grating and the first pattern are grating structures with the same grating width and grating period, and the second grating and the second pattern are grating structures with different grating width and / or grating period.

6. The semiconductor structure according to claim 5, characterized in that: The first pattern includes word lines.

7. The semiconductor structure according to claim 5, characterized in that: The second pattern includes a capacitor contact hole.

8. The semiconductor structure according to claim 1, characterized in that: The grating width and the grating period of the second grating are the same as the grating width and the grating period of the third grating.

9. A memory, characterized in that: A semiconductor structure comprising any one of claims 1 to 8.

10. A method for manufacturing a semiconductor structure, characterized in that: include: A first grating, a second grating and a third grating are formed which are stacked from bottom to top and are arranged in different photolithography layers, and the overlay mark areas for setting the gratings in different photolithography layers overlap, the first grating, the second grating and the third grating are all periodic structures, the center distance between adjacent gratings in the periodic structure is the grating period, the grating width or the grating period of the first grating is different from that of the second grating; the center position of the second grating is offset from the center position of the first grating in the vertical direction, the second grating does not overlap with the first grating in the vertical direction, and there is a gap between the first grating and the second grating, and the grating width of the second grating is greater than the grating width of the first grating and is less than or equal to twice the grating width of the first grating.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: Also includes: A second pattern is formed, wherein the second grating and the second pattern are in the same photolithography layer, the second pattern and the second grating are grating structures with different grating periods, and the grating width of the second grating is greater than the grating width of the second pattern.

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