Integrated circuit design method, relay module database construction method and device

Abstract

A method for designing an integrated circuit, and a method and device for constructing a relay module database. The integrated circuit design method includes: determining a relay module corresponding to the first interface protocol based on a first interface protocol; determining the physical distance between a first physical function module and a second physical function module; determining the number N of relay modules on the line connecting the first physical function module and the second physical function module and the corresponding physical insertion positions based on the physical distance; and inserting the N relay modules into the corresponding physical insertion positions on the line. The integrated circuit design method enables automatic insertion of relay modules, and clock gating is added to the relay modules, effectively reducing power consumption caused by inserting relay modules and achieving fine-grained clock gating. The insertion method is flexible and controllable, reducing the workload caused by inserting relay modules.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method for designing an integrated circuit, an apparatus for designing an integrated circuit, a method for constructing a relay module database, an apparatus for constructing a relay module database, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] Large-scale integrated circuits (LSIs) are typically divided into multiple physical functional modules based on their functionality and layout. A physical functional module is a general term for the physical implementation modules within an LSI. Physical functional modules are connected to each other via data signal lines for communication. For example, in front-end logic design, integrated circuits are typically designed based on intellectual property cores (IP cores). In back-end physical implementation, one physical functional module may correspond to one IP core, or, if the IP core is large, multiple physical functional modules may correspond to one IP core. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a design method for an integrated circuit, wherein the integrated circuit includes a first physical function module and a second physical function module, and the first physical function module and the second physical function module communicate using a first interface protocol. The design method includes: determining a relay module corresponding to the first interface protocol according to the first interface protocol, wherein the relay module is used to provide timing relay for an interface that communicates using the first interface protocol, and the relay module has a clock gating control set according to the first interface protocol; determining a physical distance between the first physical function module and the second physical function module; determining the number N of levels of the relay modules and corresponding insertion physical positions on a line between the first physical function module and the second physical function module according to the physical distance, wherein N is a positive integer; and inserting N relay modules into the corresponding insertion physical positions on the line.

[0004] For example, in a design method of an integrated circuit provided by at least one embodiment of the present disclosure, determining a relay module corresponding to the first interface protocol according to the first interface protocol includes: determining a relay module corresponding to the first interface protocol from a relay module database according to the first interface protocol, wherein the relay module database includes relay modules corresponding to different interface protocols, each relay module has a clock gating control set according to the corresponding interface protocol, and the different interface protocols include the first interface protocol.

[0005] For example, in a design method of an integrated circuit provided by at least one embodiment of the present disclosure, the number N of levels of the relay modules on the connection line between the first physical function module and the second physical function module and the corresponding physical insertion position are determined based on the physical distance, including: determining the routing delay between two adjacent levels of relay modules based on the clock domains where the first physical function module and the second physical function module are located; querying the distance delay database based on the routing delay and the clock domain to obtain the longest allowable routing length between the two adjacent levels of relay modules; determining the number N of levels of the relay modules on the connection line between the first physical function module and the second physical function module and the corresponding physical insertion position based on the physical distance and the longest allowable routing length.

[0006] For example, in a design method of an integrated circuit provided by at least one embodiment of the present disclosure, the distance delay database includes a mapping relationship between the routing length between two adjacent relay modules, the clock domain and the routing delay obtained through simulation, wherein the routing length between the two adjacent relay modules is determined based on the clock domain in which the two adjacent relay modules are located and the routing delay between the two adjacent relay modules.

[0007] For example, in a design method of an integrated circuit provided by at least one embodiment of the present disclosure, the routing delay of two adjacent levels of relay modules is determined based on the clock domain where the first physical function module and the second physical function module are located, including: querying the relay module database to obtain the input delay estimate and output delay estimate of the relay module corresponding to the first interface protocol; obtaining the clock period and clock skew based on the clock domain where the first physical function module and the second physical function module are located; and determining the routing delay of the two adjacent levels of relay modules in the clock domain based on the clock period, the clock skew, the input delay estimate and the output delay estimate.

[0008] For example, in a design method of an integrated circuit provided by at least one embodiment of the present disclosure, the number N of levels and the physical insertion position of the relay module on the connection line between the first physical function module and the second physical function module are determined according to the physical distance and the maximum allowable routing length, including: obtaining the number N of levels of the relay module according to the ratio of the physical distance and the maximum allowable routing length; obtaining the interval physical distance between the two adjacent levels of relay modules according to the ratio of the physical distance and the number N; and taking the positions starting from the center of the first physical function module and each interval of the interval physical distance as the physical insertion positions of the N relay modules.

[0009] For example, in a design method of an integrated circuit provided by at least one embodiment of the present disclosure, in response to the fact that the physical functional module at the physical position where the relay module is inserted does not belong to the clock domain where the first physical functional module and the second physical functional module are located, the clock signal of the relay module is added to the physical functional module at the physical position where the relay module is inserted to provide the clock signal to the relay module.

[0010] At least one embodiment of the present disclosure provides a method for constructing a relay module database for an integrated circuit, wherein the integrated circuit uses at least one interface protocol for communication between physical functional modules. The construction method includes: for any interface protocol among the at least one interface protocol, constructing a register transfer level description file corresponding to the any interface protocol according to the any interface protocol, wherein the register transfer level description file includes relay register logic and control logic related to clock gating control, and the relay register logic is used to provide timing relay for the connected interface; synthesizing the register transfer level description file to obtain a relay module netlist file corresponding to the any interface protocol, wherein the corresponding clock gating control is inserted during the synthesis process; and constructing the relay module database based on the relay module netlist file corresponding to the any interface protocol.

[0011] For example, the construction method provided by at least one embodiment of the present disclosure further includes: performing formal verification on the relay module netlist file to ensure consistency between the relay module netlist file and the register transfer level description file.

[0012] For example, in the construction method provided in at least one embodiment of the present disclosure, the control logic related to clock gating control includes: according to the valid signal level of any interface protocol, when the valid signal level indicates valid data transmission, turning on the clock signal; when the valid signal level indicates that valid data transmission is not taking place, turning off the clock signal and keeping the output value unchanged.

[0013] For example, in the construction method provided in at least one embodiment of the present disclosure, the relay module database is constructed based on the relay module netlist file corresponding to any one of the interface protocols, including: determining the input delay estimate and output delay estimate of the relay module corresponding to any one of the interface protocols according to the process of the integrated circuit, wherein the input delay estimate includes the delay estimate from the input port of the relay module to the first-level trigger, and the establishment time of the clock gating unit for performing the clock gating control, and the output delay estimate includes the delay estimate from the last-level trigger of the relay module to the output port; based on the relay module netlist file corresponding to any one of the interface protocols, the input delay estimate and the output delay estimate, the relay module database is constructed.

[0014] At least one embodiment of the present disclosure provides a design device for an integrated circuit, wherein the integrated circuit includes a first physical function module and a second physical function module, and the first physical function module and the second physical function module communicate using a first interface protocol. The design device includes: a first determination unit, configured to determine, according to the first interface protocol, a relay module corresponding to the first interface protocol, wherein the relay module is used to provide timing relay for an interface that communicates using the first interface protocol, and the relay module has clock gating control set according to the first interface protocol; a second determination unit, configured to determine the physical distance between the first physical function module and the second physical function module; a third determination unit, configured to determine, according to the physical distance, the number N of levels of the relay modules and the corresponding physical insertion positions on the connection line between the first physical function module and the second physical function module, wherein N is a positive integer; and an insertion unit, configured to insert N relay modules into the corresponding physical insertion positions on the connection line.

[0015] At least one embodiment of the present disclosure provides a device for constructing a relay module database for an integrated circuit, wherein the integrated circuit uses at least one interface protocol for communication between physical functional modules, and the construction device includes: a first construction unit, configured to construct a register transfer level description file corresponding to any interface protocol among the at least one interface protocol according to the any interface protocol, wherein the register transfer level description file includes relay register logic and control logic related to clock gating control, and the relay register logic is used to provide timing relay for the interface; a synthesis unit, configured to synthesize the register transfer level description file to obtain a relay module netlist file corresponding to the any interface protocol, wherein the corresponding clock gating control is inserted during the synthesis process; and a second construction unit, configured to construct the relay module database based on the relay module netlist file corresponding to the any interface protocol.

[0016] At least one embodiment of the present disclosure provides an electronic device, comprising: a memory, which non-transitorily stores computer-executable instructions; and a processor, configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the integrated circuit design method according to any embodiment of the present disclosure.

[0017] At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the integrated circuit design method according to any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0019] Figure 1 This is a schematic diagram of the chip divided by function;

[0020] Figure 2 A schematic diagram of a chip divided by physical functional modules;

[0021] Figure 3 A schematic flowchart of a method for designing an integrated circuit provided in at least one embodiment of the present disclosure;

[0022] Figure 4 A schematic diagram of a chip after inserting a relay module according to at least one embodiment of the present disclosure;

[0023] Figure 5 A schematic flow chart of a method for constructing a relay module database for an integrated circuit provided in at least one embodiment of the present disclosure;

[0024] Figure 6 A schematic block diagram of a design apparatus for an integrated circuit provided in at least one embodiment of the present disclosure;

[0025] Figure 7 A schematic block diagram of a device for constructing a relay module database provided in at least one embodiment of the present disclosure;

[0026] Figure 8 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure;

[0027] Figure 9 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0029] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0030] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and components.

[0031] During the design of large-scale integrated circuits (such as system-on-chips), due to their large scale, back-end design and implementation of the integrated circuit as a whole is often time-consuming or even impossible. Typically, the integrated circuit is first divided by function, and then the physical functional modules are divided from top to bottom based on their physical location. This results in the entire integrated circuit being divided into multiple physically implementable physical functional modules and a top-level layer. The reduced number of logic gates in each of these divided physical functional modules and the top-level layer makes physical implementation possible. Subsequently, each physical functional module and the top-level layer are physically implemented separately to obtain the final netlist for each component. These components are then combined from bottom to top to form the netlist for the entire integrated circuit. After various checks (including timing signoff, physical verification, and post-simulation) are completed on this netlist, the final tape-out is carried out.

[0032] Figure 1 This is a schematic diagram of chips divided by function. Figure 2 Schematic diagram of a chip divided according to physical functional modules.

[0033] like Figure 1 As shown, the chip is divided into 4 functional modules according to its functions, namely Figure 1 Module 1, module 2, module 3 and module 4 in the example, module 1, module 2, module 3 and module 4 can be 4 IP cores. Furthermore, module 1 can be further divided into 4 sub-functional modules according to function, namely module 1-A, module 1-B, module 1-C and module 1-D; similarly, module 4 can be further divided into 3 sub-functional modules, namely module 4-A, module 4-B and module 4-C. Of course, Figure 1The figure is a schematic diagram. The actual integrated circuit (or chip) may also include more functional modules, or each functional module may be divided into multiple levels. The present disclosure does not impose specific limitations on this.

[0034] like Figure 2 As shown, Figure 1 After the chip is divided according to the physical location, it can be divided into multiple physical functional modules, such as Figure 2 Physical function module 1, physical function module 2, ..., physical function module 9, etc. Among them, module 1-A and module 4-A divided by function are divided into physical function module 1 according to their physical location, module 1-B and module 4-B divided by function are divided into physical function module 7 according to their physical location, and module 1-C and module 4-C divided by function are divided into physical function module 9 according to their physical location.

[0035] Since VLSI is implemented by dividing physical functional modules, Figure 1 In the functional module according to the functional module, the connection 1 between module 1-A and module 1-C is Figure 2 The meeting is physically far apart (e.g. Figure 2 As shown by line 1 in FIG). As the line length is greatly increased, the delay caused by the line also increases accordingly, resulting in the timing between sequential devices (such as registers) and sequential devices (such as registers) not being met (for example, the setup time cannot be met).

[0036] Repeater registers can be used to address timing issues caused by long physical distances. Repeater registers are used to optimize timing. Inserting repeater registers between sequential devices can optimize the timing of the connections between them, ensuring that the timing meets the requirements.

[0037] However, current solutions for inserting relay registers include insertion based on connections between sequential devices. This approach cannot perform clock gating for complex protocols, resulting in higher power consumption of relay registers than registers on the same type of data path. Alternatively, determining the final relay register insertion solution requires multiple iterations, and calculating the number of relay registers that need to be inserted during top-level physical implementation. Each time the design is adjusted, the front-end design needs to be modified and a new round of design process needs to be executed, which results in poor flexibility. In addition, when a functional design needs to support different layouts at the same time, the workload is large and difficult to unify.

[0038] At least one embodiment of the present disclosure provides a method and apparatus for designing an integrated circuit, a method and apparatus for constructing a relay module database, an electronic device, and a non-transitory computer-readable storage medium.

[0039] The design method of the integrated circuit includes: determining a relay module corresponding to the first interface protocol according to a first interface protocol, wherein the relay module is used to provide timing relay for an interface that communicates using the first interface protocol, and the relay module has clock gating control set according to the first interface protocol; determining the physical distance between a first physical function module and a second physical function module; determining the number N of relay modules on a line connecting the first physical function module and the second physical function module and the corresponding physical insertion positions according to the physical distance, wherein N is a positive integer; and inserting the N relay modules into the corresponding physical insertion positions on the line.

[0040] In the design method of this integrated circuit, the relay module can be automatically inserted. Clock gating is added to the relay module, which can effectively reduce the power consumption caused by inserting the relay module and realize fine-grained clock gating. The insertion method is flexible and controllable, reducing the workload caused by inserting the relay module.

[0041] It should be noted that in the embodiments of the present disclosure, the timing device refers to devices such as triggers, registers, latches, etc. in digital circuit design. The timing device has storage and memory functions for input signals. When the valid edge or valid level of the clock signal is received, it can trigger the timing device to store the input signal and change the state of the output signal.

[0042] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0043] Figure 3 A schematic flowchart of a method for designing an integrated circuit provided in at least one embodiment of the present disclosure.

[0044] For example, the integrated circuit includes multiple physical function modules, and the multiple physical function modules include a first physical function module and a second physical function module. The definition of the physical function module can be referred to the above content and will not be repeated here.

[0045] For example, the first physical function module and the second physical function module may be two physical function modules among a plurality of physical function modules that execute the integrated circuit design method provided by at least one embodiment of the present disclosure.

[0046] For example, the first physical function module and the second physical function module can be any two physical function modules among multiple physical function modules. The multiple physical function modules can also include a third physical function module, a fourth physical function module, etc. The third physical function module, the fourth physical function module, etc. can all apply the integrated circuit design method provided by at least one embodiment of the present disclosure. The present disclosure does not impose any specific restrictions on this.

[0047] For example, the first physical function module and the second physical function module communicate using a first interface protocol.

[0048] For example, the first physical function module and the second physical function module can also communicate using other interface protocols, such as the second interface protocol, the third interface protocol, etc. The processing method for inserting the relay module using other interface protocols is the same as that of the first interface protocol, and will not be repeated here.

[0049] Similarly, for other physical function modules among the multiple physical function modules, the relay module can also be inserted in a manner similar to that of the first physical function module and the second physical function module, which will not be described in detail here.

[0050] For example, Figure 3 As shown, the integrated circuit design method provided by the embodiment of the present disclosure includes steps S10 to S40.

[0051] In step S10, a relay module corresponding to the first interface protocol is determined according to the first interface protocol.

[0052] For example, the relay module is used to provide timing relay for the interface that communicates using the first interface protocol. For example, the timing relay includes sampling the signal and transmitting it to ensure that the signal can be transmitted correctly under the corresponding clock cycle. The relay module also has clock gating control set according to the first interface protocol.

[0053] For example, the relay module is derived based on the relay register. The relay module has the function of performing timing relaying using the relay register (repeater). Furthermore, the relay module also has clock gating control (ClockGating) configured according to the first interface protocol. For details on how to create the relay module, please refer to the subsequent description of the method for constructing the relay module database. Any repetitions will not be repeated here.

[0054] Clock gating is a technique used in digital integrated circuit (IC) designs to disable the clock when certain parts (such as individual registers, modules, subsystems, or the entire chip) are not needed. Adding clock gating control effectively reduces the chip's dynamic power consumption by shutting down the clock signal when it is not needed. For detailed instructions and design methods for clock gating, please refer to the current technical implementation methods for clock gating and will not be elaborated here.

[0055] For example, step S10 may include: determining, according to the first interface protocol, a relay module corresponding to the first interface protocol from a relay module database.

[0056] For example, the relay module database includes relay modules corresponding to different interface protocols, each relay module has a clock gating control set according to the corresponding interface protocol, and the different interface protocols include the first interface protocol.

[0057] For example, the relay module database provides P types of relay modules corresponding to P types of interface protocols, where P is a positive integer. For example, the P types of interface protocols can be determined in advance based on possible interface protocols used in various integrated circuit designs.

[0058] For example, the relay module corresponding to each relay protocol has clock gating control set according to the corresponding interface protocol. Of course, the relay module also has the same clock optimization and clock repair functions as the relay register.

[0059] For example, P types of interface protocols include a first interface protocol. By querying the relay module database, the relay module corresponding to the first interface protocol can be directly obtained. The pre-built relay module database can provide unified and standardized relay modules corresponding to different interface protocols.

[0060] For example, in at least one embodiment of the present disclosure, targeted clock gating control is provided in the relay module, and the clock gating is optimized in combination with different interface protocols; in addition, the relay module also provides input delay estimation, output delay estimation, etc. under different processes according to the integrated circuit process, so that the allowable routing distance between relay modules can be estimated more accurately; and the relay module is synthesized and formally verified with the module as the granularity. The relay module can be applied to different integrated circuit designs, and can be automatically inserted into the netlist file of the integrated circuit (such as the netlist file corresponding to the entire chip formed by the final combination of various physical functional modules) during physical implementation, such as the floorplan stage, so that each physical functional module can still be independently designed, modified, and synthesized. After the netlist file of the entire integrated circuit is synthesized, the relay module is inserted, and there is no need to re-execute a round of design process from the front end to the back end to achieve tape-out, thereby reducing workload and increasing insertion flexibility.

[0061] For the specific construction process of the relay module database, please refer to the relevant content of the construction method of the relay module database later, which will not be repeated here.

[0062] Of course, it is also possible to directly create a corresponding relay module based on the first interface protocol, for example, by adding clock gating related to the first interface protocol to the relay register. This disclosure does not impose specific restrictions on this. For example, the specific construction method can refer to the relay module construction process in the subsequent relay module database construction method, and will not be repeated here.

[0063] In step S20 , the physical distance between the first physical function module and the second physical function module is determined.

[0064] For example, the physical distance can be calculated by a layout tool. For example, the physical distance can be the Manhattan distance between the first physical function module and the second physical function module. Of course, it can also be a physical distance defined by other rules. This disclosure does not impose specific restrictions on this.

[0065] For example, in order for the inserted relay module to fully meet the timing requirement, the physical distance may be the physical distance from the center point of the first physical function module to the center point of the second physical function module.

[0066] In step S30, the number N of relay modules on the line between the first physical function module and the second physical function module and the corresponding physical insertion positions are determined according to the physical distance, where N is a positive integer.

[0067] For example, step S30 may include: determining the routing delay between two adjacent levels of relay modules based on the clock domains where the first physical function module and the second physical function module are located; querying the distance delay database based on the routing delay and the clock domain to obtain the maximum allowable routing length between two adjacent levels of relay modules; determining the number N of relay modules on the connection line between the first physical function module and the second physical function module and the corresponding physical insertion position based on the physical distance and the maximum allowable routing length.

[0068] For example, determining the routing delay between two adjacent levels of relay modules based on the clock domain where the first physical function module and the second physical function module are located can include: querying the relay module database to obtain the input delay estimate and output delay estimate of the relay module corresponding to the first interface protocol; obtaining the clock period and clock skew based on the clock domain where the first physical function module and the second physical function module are located; and determining the routing delay of the two adjacent levels of relay modules in the clock domain based on the clock period, clock skew, input delay estimate and output delay estimate.

[0069] For example, the relay module database provides input delay estimates and output delay estimates related to the integrated circuit process. For example, the relay module can be simulated and analyzed in advance based on different integrated circuit process parameters to estimate the input delay and output delay estimates of the relay module corresponding to different protocols. For example, the input delay estimate includes the delay estimate from the input port of the relay module to the first-stage trigger and the setup time of the clock gating unit used for clock gating control. For example, the output delay estimate includes the delay estimate from the last-stage trigger of the relay module to the output port.

[0070] For example, the input delay estimation and output delay estimation are also stored in the relay module database, and a relay module database with complete information is constructed, so that a more accurate routing delay can be calculated and the most appropriate relay module level and insertion position can be obtained.

[0071] For example, the first physical function module and the second physical function module belong to the same clock domain, such as clock domain 1. The clock period T and clock skew T2 of clock domain 1 are obtained. Clock skew is caused by differences in wiring length and load, resulting in inconsistent arrival times of the same clock signal at two adjacent sequential devices. Clock skew indicates the time difference between the same clock signal arriving at two different sequential devices.

[0072] For example, when calculating routing delay, the estimated clock skew T2 is subtracted from the clock period T to obtain the delay T0 (T-T2) between two adjacent relay modules; the sum of the input delay estimate and the output delay estimate T1 is calculated; and the routing delay T=T0-T1 is calculated.

[0073] For example, in other examples, determining the routing delay of two adjacent relay modules may not require input delay estimation and output delay estimation, and a margin may be reserved based on experience when calculating the routing delay.

[0074] After the routing delay is obtained, the distance delay database is queried to obtain the longest allowed routing length L0 between two adjacent relay modules.

[0075] For example, the distance delay database includes a mapping relationship between the routing length and routing delay between two adjacent relay modules obtained through simulation. For example, the routing length between two adjacent relay modules is determined according to the routing delay of the two adjacent relay modules.

[0076] For example, the wiring length between two adjacent relay modules refers to the wiring length between the output of a relay module at one level and the input of the adjacent relay module at the next level, which is used to improve the buffer or inverter pair for level transition time.

[0077] For example, a distance delay database can be established through simulation. Under different digital circuit processes, the maximum routing distance between two adjacent relay modules will also vary. Through simulation, a mapping relationship between the routing length and routing delay between two adjacent relay modules is established. This allows the calculated routing delay to be used to query the distance delay database and determine the maximum allowable routing length L0 for that routing delay under the digital circuit process and clock frequency specified by the integrated circuit.

[0078] For example, determining the number N of relay modules on the line connecting the first physical function module and the second physical function module and the corresponding physical insertion positions based on the physical distance and the maximum allowable routing length may include: obtaining the number N of relay modules based on the ratio of the physical distance and the maximum allowable routing length; obtaining the interval physical distance between two adjacent levels of relay modules based on the ratio of the physical distance and the number N; and using the positions starting from the center of the first physical function module and at each interval of the interval physical distance as the physical insertion positions of the N relay modules.

[0079] The physical distance L between the first physical function module and the second physical function module is obtained in step S20, and the ratio (L / L0) of the physical distance L and the longest allowed routing length L0 is calculated. The ratio is rounded up to obtain the number of relay modules to be inserted, that is, here Represents the ceiling function.

[0080] Calculate the ratio of the physical distance to the number of levels N (L / N), and use it as the physical distance L1 between two adjacent relay modules. Starting from the center of a physical function module (for example, the first physical function module), every L1 position is the position where the relay module needs to be inserted, that is, the physical insertion position.

[0081] In step S40 , N relay modules are inserted into corresponding physical positions on the connection line.

[0082] For example, N relay modules are respectively inserted into corresponding N physical insertion positions on the connection line, and the corresponding input, output, and clock signals are connected. For example, when inserting the relay module, the original connection line is disconnected, and the relay module is placed in the corresponding physical insertion position. Starting from the first physical function module (for example, the first physical function module is the signal transmitting end), the output of the first physical function module is connected to the input of the first-level relay module, and the output of the first-level relay module is connected to the input of the second-level relay module, and so on, until the relay module is connected to the Nth-level relay module, and the Nth-level relay module is connected to the input of the second physical function module.

[0083] For example, the relay module inserted here is the relay module obtained by querying the relay module database in step S10. The relay module is in the form of a netlist, for example. The netlist is inserted into the corresponding physical insertion position in the netlist file of the integrated circuit, so that each physical functional module can still be independently designed, modified, and synthesized. After the netlist file of the entire integrated circuit is synthesized, the relay module is inserted. There is no need to re-execute a round of design process from the front end to the back end to achieve tape-out, which reduces workload and increases insertion flexibility.

[0084] For example, if multiple relay modules need to be inserted into a physical function module, the module name of the relay module needs to be modified before insertion to avoid duplication.

[0085] For example, Figure 4 A schematic diagram of a chip after inserting a relay module according to at least one embodiment of the present disclosure.

[0086] For example, module 1-A is the first physical function module, module 1-C is the second physical function module, and the connection 1 between module 1-A and module 1-C uses the first interface protocol for communication. The relay module corresponding to the first interface protocol is determined through step S10.

[0087] Thereafter, the physical distance L between the module 1 -A and the module 1 -C is determined in step S20 .

[0088] Afterwards, referring to step S30, the number of stages N between module 1-A and module 1-C and the corresponding physical insertion positions are calculated. The specific process is not repeated here. For example, after step S30, it is determined that the number of stages between module 1-A and module 1-C is 3, which means that 3 stages of relay modules need to be inserted. Thus, starting from the center of module 1-A, relay modules are inserted at positions of the calculated physical distance, such as Figure 4 As shown, a relay module of level 1 is inserted at intervals of the physical distance on the connection 1, namely, relay module 1, intermediate module 2 and relay module 3.

[0089] For example, in response to the physical function module where the relay module is physically inserted not belonging to the clock domain where the first physical function module and the second physical function module are located, the clock signal of the relay module is added to the physical function module where the relay module is physically inserted to provide the clock signal to the relay module.

[0090] For example, if the physical insertion position of the relay module is located in the first physical function module or the second physical function module, since the first physical function module and the second physical function module belong to the same clock domain, the clock of the corresponding register in the first physical function module or the second physical function module can be directly used as the clock signal of the relay module; if the physical insertion position of the relay module is not located in the first physical function module or the second physical function module, and the physical function module where the physical insertion position of the relay module is located does not have the clock signal required by the relay module, then the clock signal of the relay module is added to the physical function module where the physical insertion position of the relay module is located to provide the clock signal to the relay module.

[0091] For example, Figure 4For example, assuming that physical function module 1 and physical function module 9 both belong to clock domain 1 and are provided with clock signals by clock signal 1, relay module 1, relay module 2, and relay module 3 on the line between module 1-A and module 1-C all need to be connected to clock signal 1 to provide clock signals. Assuming that physical function module 3 belongs to clock domain 2 and is provided with clock signals by clock signal 2, that is, the clock domain of the physical function module where relay module 2 is located is different from the clock domain where modules 1-A and 1-C are located, then clock signal 1 needs to be added to physical function module 3 for use by relay module 2, and the clock signals used by all relay modules need to be balanced to ensure that the timing meets the requirements.

[0092] For example, when an integrated circuit includes multiple physical functional modules, the process of inserting relay modules into the lines between each physical functional module can be performed in parallel. For example, in some embodiments, there are U pairs of physical functional modules applying a first interface protocol, where U is a positive integer. After obtaining relay modules corresponding to the first interface protocol in step S10, steps S20-S40 are performed in parallel for each pair of physical functional modules to complete the insertion of relay modules between each pair of physical functional modules. This can improve the efficiency of the relay module insertion process.

[0093] Corresponding to the integrated circuit design method described above, at least one embodiment of the present disclosure further provides a method for constructing a relay module database.

[0094] For example, as described in step S10 of the aforementioned integrated circuit design method, the pre-built relay module database can provide unified and standardized relay modules corresponding to different interface protocols.

[0095] The following describes in detail a method for constructing a relay module database provided by at least one embodiment of the present disclosure with reference to the accompanying drawings.

[0096] Figure 5 A schematic flowchart of a method for constructing a relay module database for an integrated circuit provided in at least one embodiment of the present disclosure.

[0097] For example, the integrated circuit uses at least one interface protocol for communication between physical functional modules. For example, the at least one interface protocol includes a first interface protocol, and the at least one interface protocol may also include other interface protocols, such as a second interface protocol. Of course, the relay module database can support not only the interface protocols used in one integrated circuit design, but also interface protocols used in different integrated circuit designs. For example, the relay module database serves as a comprehensive library for various integrated circuit designs, providing corresponding relay modules for multiple interface protocols.

[0098] like Figure 5As shown, the method for constructing a relay module database provided by at least one embodiment of the present disclosure includes steps S50-S70.

[0099] In step S50 , for any interface protocol among the at least one interface protocol, a register transfer level description file corresponding to any interface protocol is constructed according to any interface protocol.

[0100] For example, the register transfer level description file includes a relay register logic and a control logic related to clock gating control, where the relay register logic is used to provide timing relay for the connected interface.

[0101] For example, according to the interface protocol, write the RTL code of the corresponding relay module. In the process of writing the RTL code, for data paths or multi-bit data, use a clock-gating-friendly coding style according to the interface protocol.

[0102] For example, the control logic related to clock gating control includes: according to the valid signal level of any interface protocol, when the valid signal level indicates valid data transmission, turning on the clock signal and performing valid data transmission; when the valid signal level indicates that no valid data transmission is taking place, turning off the clock signal and keeping the output value unchanged instead of changing it to 0, thereby reducing energy consumption.

[0103] In step S60 , the register transfer level description file is synthesized to obtain a relay module netlist file corresponding to any interface protocol, wherein corresponding clock gating control is inserted during the synthesis process.

[0104] For example, the RTL files of the relay modules corresponding to various interface protocols are synthesized separately. During the synthesis, the tool automatically inserts clock gating according to the coding to achieve the purpose of reducing power consumption.

[0105] For example, in some embodiments, the method further includes: performing formal verification on the relay module netlist file to ensure consistency between the relay module netlist file and the register transfer level description file.

[0106] In this way, fine-grained (module-level) clock gating can be achieved, and the power consumption of the relay module can be reduced to the level of an ordinary register on the data path.

[0107] In step S70 , a relay module database is constructed based on the relay module netlist file corresponding to any interface protocol.

[0108] For example, in some examples, a relay module database may be formed based on relay module netlist files corresponding to various interface protocols after synthesis and formal verification.

[0109] For example, in other examples, a more complete relay module database can be constructed based on the combination of input and output features, and the database is process-related.

[0110] For example, step S70 may include: determining the input delay estimate and output delay estimate of the relay module corresponding to any interface protocol based on the process of the integrated circuit, wherein the input delay estimate includes the delay estimate from the input port of the relay module to the first-level trigger, and the setup time of the clock gating unit for clock gating control, and the output delay estimate includes the delay estimate from the last-level trigger of the relay module to the output port; and constructing a relay module database based on the relay module netlist file, input delay estimate, and output delay estimate corresponding to any interface protocol.

[0111] For example, by querying the relay module database, the relay module netlist file corresponding to a certain interface protocol, as well as the input delay estimate and output delay estimate of the relay module can be found. The input delay estimate and output delay estimate can be used to calculate a more accurate relay module level and insertion position, and the relay module can be automatically inserted into the netlist file of the integrated circuit (for example, the netlist file corresponding to the entire chip formed by the final combination of various physical functional modules), thereby achieving a flexible insertion method and reducing the power consumption of the inserted relay module to the level of registers on the same type of data path.

[0112] Corresponding to the above-mentioned integrated circuit design method, at least one embodiment of the present disclosure further provides an integrated circuit design device. Figure 6 A schematic block diagram of a design apparatus for an integrated circuit provided in at least one embodiment of the present disclosure.

[0113] For example, the integrated circuit includes a first physical function module and a second physical function module, and the first physical function module and the second physical function module communicate using a first interface protocol. For a description of the first physical function module and the second physical function module and the first interface protocol, reference can be made to the aforementioned integrated circuit design method, and no further details are given here.

[0114] For example, Figure 6 As shown, the integrated circuit design device 100 includes: a first determining unit 101 , a second determining unit 102 , a third determining unit 103 and an inserting unit 104 .

[0115] The first determination unit 101 is configured to determine a relay module corresponding to the first interface protocol according to the first interface protocol, wherein the relay module is used to provide timing relay for the interface that communicates using the first interface protocol, and the relay module has clock gating control set according to the first interface protocol.

[0116] The second determining unit 102 is configured to determine a physical distance between the first physical function module and the second physical function module.

[0117] The third determining unit 103 is configured to determine the number N of relay modules on the line between the first physical function module and the second physical function module and corresponding physical insertion positions according to the physical distance, where N is a positive integer.

[0118] The inserting unit 104 is configured to insert the N relay modules into corresponding physical insertion positions on the connection line.

[0119] For example, when the first determination unit 101 executes to determine the relay module corresponding to the first interface protocol according to the first interface protocol, it includes performing the following operations: determining the relay module corresponding to the first interface protocol from the relay module database according to the first interface protocol, wherein the relay module database includes relay modules corresponding to different interface protocols respectively, each relay module has a clock gating control set according to the corresponding interface protocol, and the different interface protocols include the first interface protocol.

[0120] For example, when the third determination unit 103 determines the number N of relay modules on the line connecting the first physical function module and the second physical function module and the corresponding physical insertion position based on the physical distance, it includes performing the following operations: determining the routing delay between two adjacent relay modules based on the clock domains where the first physical function module and the second physical function module are located; querying the distance delay database based on the routing delay and the clock domain to obtain the maximum allowable routing length between two adjacent relay modules; determining the number N of relay modules on the line connecting the first physical function module and the second physical function module and the corresponding physical insertion position based on the physical distance and the maximum allowable routing length.

[0121] For example, the distance delay database includes the mapping relationship between the routing length between two adjacent relay modules, the clock domain and the routing delay obtained through simulation, wherein the routing length between two adjacent relay modules is determined according to the clock domain in which the two adjacent relay modules are located and the routing delay between the two adjacent relay modules.

[0122] For example, the third determination unit 103 determines the routing delay of two adjacent levels of relay modules based on the clock domain where the first physical function module and the second physical function module are located, including performing the following operations: querying the relay module database to obtain the input delay estimate and output delay estimate of the relay module corresponding to the first interface protocol; obtaining the clock period and clock skew based on the clock domain where the first physical function module and the second physical function module are located; and determining the routing delay of two adjacent levels of relay modules in the clock domain based on the clock period, clock skew, input delay estimate and output delay estimate.

[0123] For example, the third determination unit 103 determines the number N of relay modules on the line between the first physical function module and the second physical function module and the physical position of insertion based on the physical distance and the maximum allowable routing length, including the following operations: obtaining the number N of relay modules based on the ratio of the physical distance and the maximum allowable routing length; obtaining the interval physical distance between two adjacent levels of relay modules based on the ratio of the physical distance and the number N; and taking the position of each interval of the physical distance starting from the center of the first physical function module as the physical position of insertion of N relay modules.

[0124] For example, in response to the physical function module where the relay module is physically inserted not belonging to the clock domain where the first physical function module and the second physical function module are located, the clock signal of the relay module is added to the physical function module where the relay module is physically inserted to provide a clock signal to the relay module.

[0125] For example, the first determination unit 101, the second determination unit 102, the third determination unit 103, and the insertion unit 104 include codes and programs stored in a memory; a processor can execute the codes and programs to implement some or all of the functions of the first determination unit 101, the second determination unit 102, the third determination unit 103, and the insertion unit 104 described above. For example, the first determination unit 101, the second determination unit 102, the third determination unit 103, and the insertion unit 104 can be dedicated hardware devices used to implement some or all of the functions of the first determination unit 101, the second determination unit 102, the third determination unit 103, and the insertion unit 104 described above. For example, the first determination unit 101, the second determination unit 102, the third determination unit 103, and the insertion unit 104 can be a circuit board or a combination of multiple circuit boards used to implement the functions described above. In an embodiment of the present application, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-transitory memories connected to the processors; and (3) firmware stored in the memory that is executable by the processor.

[0126] It should be noted that the first determining unit 101 is used to implement Figure 3 In step S10 shown, the second determining unit 102 is used to implement Figure 3 In step S20 shown, the third determining unit 103 is used to implement Figure 3 In step S30 shown, the inserting unit 104 is used to implement Figure 3 The step S40 shown. Therefore, the detailed description of the first determining unit 101 can refer to the embodiment of the above-mentioned integrated circuit design method. Figure 3 The relevant description of step S10 shown in FIG. 1 and the specific description of the second determining unit 102 can refer to the embodiment of the design method of the integrated circuit described above. Figure 3 For the description of step S20 shown in FIG. 1 , the specific description of the third determining unit 103 can be referred to in the embodiment of the design method of the integrated circuit. Figure 3 The description of step S30 shown in FIG. 1 and the specific description of the insertion unit 104 can be referred to in the embodiment of the design method of the integrated circuit. Figure 3 In addition, the integrated circuit design device can achieve similar technical effects as the aforementioned integrated circuit design method, which will not be described in detail here.

[0127] Corresponding to the above-mentioned method for constructing a relay module database for an integrated circuit, at least one embodiment of the present disclosure further provides a device for constructing a relay module database. Figure 7 A schematic block diagram of a device for constructing a relay module database provided in at least one embodiment of the present disclosure.

[0128] For example, the integrated circuit uses at least one interface protocol to communicate between physical function modules. For the description of physical function modules and interface protocols, please refer to the related content of the method for constructing a relay module database for an integrated circuit, which will not be repeated here.

[0129] For example, Figure 7 As shown, the apparatus 200 for constructing a relay module database includes: a first constructing unit 201 , an integrating unit 202 , and a second constructing unit 203 .

[0130] The first construction unit 201 is configured to construct a register transfer level description file corresponding to any one of the at least one interface protocols according to the any one interface protocol, wherein the register transfer level description file includes a relay register logic and a control logic related to clock gating control, and the relay register logic is used to provide timing relay for the interface.

[0131] The synthesis unit 202 is configured to synthesize the register transfer level description file to obtain a relay module netlist file corresponding to any one of the interface protocols, wherein corresponding clock gating control is inserted during the synthesis process.

[0132] The second constructing unit 203 is configured to construct the relay module database based on the relay module netlist file corresponding to any one of the interface protocols.

[0133] The apparatus 200 for constructing a relay module database further includes a verification unit (not shown in the figure), which is configured to perform formal verification on the relay module netlist file to ensure consistency between the relay module netlist file and the register transfer level description file.

[0134] For example, the control logic related to clock gating control includes: according to the valid signal level of any interface protocol, when the valid signal level indicates valid data transmission, turning on the clock signal; when the valid signal level indicates no valid data transmission, turning off the clock signal and keeping the output value unchanged.

[0135] For example, the second construction unit 203 executes the construction of the relay module database based on the relay module netlist file corresponding to any of the interface protocols, including the following operations: determining the input delay estimation and output delay estimation of the relay module corresponding to any of the interface protocols according to the process of the integrated circuit, wherein the input delay estimation includes the delay estimation from the input port of the relay module to the first-level trigger, and the establishment time of the clock gating unit for performing the clock gating control, and the output delay estimation includes the delay estimation from the last-level trigger of the relay module to the output port; constructing the relay module database based on the relay module netlist file corresponding to any of the interface protocols, the input delay estimation and the output delay estimation.

[0136] It should be noted that the first construction unit 201 is used to implement Figure 5 In step S50 shown, the integration unit 202 is used to implement Figure 5 In step S60 shown, the second construction unit 203 is used to implement Figure 5 The detailed description of the first construction unit 201 can refer to the embodiment of the construction method of the relay module database. Figure 5 The description of step S50 shown in FIG. 2 and the detailed description of the integration unit 202 can refer to the embodiment of the method for constructing the relay module database. Figure 5 The description of step S60 shown in FIG. 2 and the detailed description of the second construction unit 203 can refer to the embodiment of the construction method of the relay module database. Figure 5 In addition, the apparatus for constructing a relay module database can achieve similar technical effects as the aforementioned method for constructing a relay module database, and will not be described in detail here.

[0137] At least one embodiment of the present disclosure further provides an electronic device, Figure 8 A schematic block diagram of an electronic device provided in accordance with at least one embodiment of the present disclosure.

[0138] For example, Figure 8As shown, the electronic device includes a processor 301, a communication interface 302, a memory 303, and a communication bus 304. The processor 301, the communication interface 302, and the memory 303 communicate with each other via the communication bus 304. The processor 301, the communication interface 302, the memory 303, and other components can also communicate with each other via a network connection. This disclosure does not limit the type and function of the network.

[0139] For example, the memory 303 is configured to non-transiently store computer-executable instructions. When the processor 301 is configured to execute the computer-executable instructions, the computer-executable instructions, when executed by the processor 301, implement the integrated circuit design method according to any of the aforementioned embodiments, or implement the relay module database construction method according to any of the aforementioned embodiments. The specific implementation and related explanations of each step of the integrated circuit design method can be found in the aforementioned embodiments of the integrated circuit design method. The specific implementation and related explanations of each step of the relay module database construction method can be found in the aforementioned embodiments of the relay module database construction method, and are not further described here.

[0140] For example, the implementation manner of the integrated circuit design method implemented by the processor 301 executing the program stored in the memory 303 is the same as the implementation manner mentioned in the embodiment of the integrated circuit design method, and will not be repeated here.

[0141] For example, the processor 301 executes the program stored in the memory 303 to implement the method for constructing the relay module database, which is the same as the implementation method mentioned in the embodiment of the method for constructing the relay module database, and will not be repeated here.

[0142] For example, the communication bus 304 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industrial Standard Architecture (EISA) bus. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used in the figure, but this does not mean that there is only one bus or only one type of bus.

[0143] For example, the communication interface 302 is used to implement communication between the electronic device and other devices.

[0144] For example, the processor 301 and the memory 303 may be provided on a server side (or a cloud side).

[0145] For example, the processor 301 can control other components in the electronic device to perform desired functions. The processor 301 can be a central processing unit (CPU), a network processor (NP), etc., and can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The central processing unit (CPU) can be an X86 or ARM architecture, etc.

[0146] For example, the memory 303 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer-executable instructions may be stored on the computer-readable storage medium, and the processor 301 may execute the computer-executable instructions to implement various functions of the electronic device. Various applications and various data may also be stored in the storage medium.

[0147] For example, for a detailed description of the process of the electronic device executing the design of an integrated circuit, reference can be made to the relevant description in the embodiment of the integrated circuit design method, and any repetitions will not be repeated. For a detailed description of the process of the electronic device executing the construction of the relay module database, reference can be made to the relevant description in the embodiment of the method for constructing the relay module database, and any repetitions will not be repeated.

[0148] Figure 9 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Figure 9 As shown, one or more computer executable instructions 401 may be non-transitory stored on a storage medium 400. For example, when the computer executable instructions 401 are executed by a processor, one or more steps in the integrated circuit design method described above may be performed.

[0149] For example, the storage medium 400 may be applied to the above-mentioned electronic device and / or integrated circuit design device. For example, the storage medium 400 may include a memory in the electronic device.

[0150] For example, the description of the storage medium 400 may refer to the description of the memory in the embodiment of the electronic device, and the repeated parts will be omitted.

[0151] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented through hardware, software, firmware, or a combination of some or all of the three.

[0152] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0153] Flowcharts are used in this disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the preceding or following steps do not necessarily need to be performed in exact order. Instead, the various steps may be performed in reverse order or simultaneously. Furthermore, other operations may be added to these processes.

[0154] Those skilled in the art will appreciate that all or part of the steps in the above method can be performed by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk, or an optical disk. Alternatively, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of software functional modules. The present disclosure is not limited to any particular combination of hardware and software.

[0155] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or highly formal sense unless expressly defined as such herein.

Claims

1. A method for designing an integrated circuit, the integrated circuit comprising a first physical function module and a second physical function module, the first physical function module and the second physical function module communicating using a first interface protocol, The design method includes: Determining, according to the first interface protocol, a relay module corresponding to the first interface protocol, wherein the relay module is used to provide timing relay for an interface that communicates using the first interface protocol, and the relay module has clock gating set according to the first interface protocol; determining a physical distance between the first physical function module and the second physical function module; Determine, based on the physical distance, the number N of relay modules on the line connecting the first physical function module and the second physical function module and the corresponding physical insertion position, where N is a positive integer; Inserting N of the relay modules into corresponding physical positions on the connection line; Wherein, determining a relay module corresponding to the first interface protocol according to the first interface protocol includes: According to the first interface protocol, a relay module corresponding to the first interface protocol is determined from a relay module database, wherein the relay module database includes relay modules corresponding to different interface protocols respectively, each relay module has a clock gating control set according to the corresponding interface protocol, and the different interface protocols include the first interface protocol.

2. The design method according to claim 1, wherein: Determining, based on the physical distance, the number N of stages of the relay modules and corresponding physical insertion positions on the line connecting the first physical function module and the second physical function module, includes: determining a routing delay between two adjacent relay modules according to the clock domains where the first physical function module and the second physical function module are located; According to the routing delay and the clock domain, querying a distance delay database to obtain the longest allowed routing length between the two adjacent relay modules; The number N of stages of the relay modules and corresponding physical insertion positions on the line between the first physical function module and the second physical function module are determined according to the physical distance and the maximum allowed routing length.

3. The design method according to claim 2, wherein: The distance delay database includes a mapping relationship between the routing length and routing delay between two adjacent relay modules obtained through simulation, wherein the routing length between the two adjacent relay modules is determined according to the routing delay between the two adjacent relay modules.

4. The design method according to claim 2, wherein: Determining, according to the clock domains where the first physical function module and the second physical function module are located, routing delays of two adjacent relay modules, including: querying a relay module database to obtain an input delay estimate and an output delay estimate of the relay module corresponding to the first interface protocol; Obtaining a clock period and a clock skew according to the clock domains where the first physical function module and the second physical function module are located; The routing delays of the two adjacent relay modules in the clock domain are determined according to the clock period, the clock skew, the input delay estimate, and the output delay estimate.

5. The design method according to claim 2, wherein: Determining, based on the physical distance and the maximum allowable routing length, the number N of stages and the physical position of insertion of the relay module on the line connecting the first physical function module and the second physical function module, includes: Obtaining the number N of relay modules according to a ratio of the physical distance to the longest allowable routing length; Obtaining a physical distance between two adjacent relay modules according to a ratio of the physical distance to the number of stages N; Starting from the center of the first physical function module, positions at intervals of the physical distance are respectively used as physical insertion positions of the N relay modules.

6. The design method according to claim 2, wherein: In response to the fact that the physical function module where the relay module is physically inserted does not belong to the clock domain where the first physical function module and the second physical function module are located, the clock signal of the relay module is added to the physical function module where the physical insertion position is located to provide the clock signal to the relay module.

7. A method for constructing a relay module database for an integrated circuit, wherein the integrated circuit uses at least one interface protocol for communication between physical functional modules. The construction method comprises: For any interface protocol among the at least one interface protocol, constructing a register transfer level description file corresponding to the any interface protocol according to the any interface protocol, wherein the register transfer level description file includes relay register logic and control logic related to clock gating control, the relay register logic being used to provide timing relay for the connected interface; synthesizing the register transfer level description file to obtain a relay module netlist file corresponding to any one of the interface protocols, wherein corresponding clock gating control is inserted during the synthesis process; The relay module database is constructed based on the relay module netlist file corresponding to any of the interface protocols; wherein the relay module database includes relay modules corresponding to different interface protocols, each relay module having a clock gating control set according to the corresponding interface protocol.

8. The construction method according to claim 7, further comprising: Formal verification is performed on the relay module netlist file to ensure consistency between the relay module netlist file and the register transfer level description file.

9. The construction method according to claim 7, wherein: The control logic related to clock gating control includes: According to the valid signal level of any of the interface protocols, when the valid signal level indicates valid data transmission, the clock signal is turned on; when the valid signal level indicates no valid data transmission, the clock signal is turned off and the output value is kept unchanged.

10. The construction method according to claim 7, wherein: Constructing the relay module database based on the relay module netlist file corresponding to any one of the interface protocols includes: Determining, based on the process of the integrated circuit, an input delay estimate and an output delay estimate of the relay module corresponding to any one of the interface protocols, wherein the input delay estimate includes a delay estimate from an input port of the relay module to a first-stage trigger and a setup time of a clock gating unit used for performing the clock gating control, and the output delay estimate includes a delay estimate from a last-stage trigger of the relay module to an output port; The relay module database is constructed based on the relay module netlist file, input delay estimation and output delay estimation corresponding to any one of the interface protocols.

11. A design device for an integrated circuit, the integrated circuit comprising a first physical function module and a second physical function module, the first physical function module and the second physical function module communicating using a first interface protocol, The design device comprises: a first determining unit configured to determine, according to the first interface protocol, a relay module corresponding to the first interface protocol, wherein the relay module is used to provide timing relay for an interface that communicates using the first interface protocol, and the relay module has a clock gating control set according to the first interface protocol; a second determining unit, configured to determine a physical distance between the first physical function module and the second physical function module; a third determining unit configured to determine, based on the physical distance, a number N of stages of the relay modules on a line connecting the first physical function module and the second physical function module and corresponding physical insertion positions, where N is a positive integer; an inserting unit configured to insert the N relay modules into corresponding physical insertion positions on the connection line; Wherein, determining a relay module corresponding to the first interface protocol according to the first interface protocol includes: According to the first interface protocol, a relay module corresponding to the first interface protocol is determined from a relay module database, wherein the relay module database includes relay modules corresponding to different interface protocols respectively, each relay module has a clock gating control set according to the corresponding interface protocol, and the different interface protocols include the first interface protocol.

12. A device for constructing a relay module database for an integrated circuit, wherein the integrated circuit uses at least one interface protocol for communication between physical functional modules. The construction device comprises: a first constructing unit configured to construct, for any interface protocol among the at least one interface protocol, a register transfer level description file corresponding to the any interface protocol according to the any interface protocol, wherein the register transfer level description file includes a relay register logic and a control logic related to clock gating control, the relay register logic being used to provide timing relay for the interface; a synthesis unit configured to synthesize the register transfer level description file to obtain a relay module netlist file corresponding to any one of the interface protocols, wherein corresponding clock gating control is inserted during the synthesis process; The second construction unit is configured to construct the relay module database based on the relay module netlist file corresponding to any of the interface protocols; wherein the relay module database includes relay modules corresponding to different interface protocols, and each relay module has clock gating control set according to the corresponding interface protocol.

13. An electronic device comprising: a memory that non-transitorily stores computer-executable instructions; a processor configured to execute the computer-executable instructions, Wherein, when the computer executable instructions are executed by the processor, the method for designing an integrated circuit according to any one of claims 1 to 6 or the method for constructing a relay module database according to any one of claims 7 to 10 is implemented.

14. A non-transitory computer-readable storage medium, wherein: The non-transitory computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, implement the integrated circuit design method according to any one of claims 1 to 6 or the relay module database construction method according to any one of claims 7 to 10.

Images