Array substrate, method for preparing same, and display panel

Abstract

The present application provides an array substrate, a preparation method thereof, and a display panel. The array substrate includes: a substrate substrate including a display area and a non-display area located on at least one side of the display area; thin-film transistors disposed on the substrate substrate, and the thin-film transistors are located in the display area; a passivation layer disposed on the thin-film transistors and the substrate substrate; wherein, the passivation layer includes a first passivation layer located in the display area and a second passivation layer located in the non-display area, the first passivation layer and the second passivation layer are disposed in the same layer, and the light transmittance of the first passivation layer is higher than that of the second passivation layer. The array substrate structure provided by the present application can improve the transmittance of the array substrate without affecting the reliability of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and particularly to an array substrate, a preparation method thereof, and a display panel. Background Art

[0002] The transmittance of a display screen is an important indicator for measuring the optical performance of the display screen. The array substrate is an important part of the display screen. Since pixel switches and driving circuits need to be fabricated on the array substrate, the transmittance of the array substrate will affect the overall transmittance of the display screen, thereby affecting the overall optical utilization effect and backlight selection cost of the liquid crystal display screen. In order to improve the transmittance of the array substrate, many related studies on the film layer structure have been carried out in the industry in recent years. For example, the film layer materials are improved. However, although the change of some film layer materials improves the transmittance of the array substrate, it causes problems in reliability. Summary of the Invention

[0003] In view of this, this application provides an array substrate, a preparation method thereof, and a display panel, which can improve the transmittance of the array substrate and do not affect the reliability of the array substrate.

[0004] In a first aspect, this application provides an array substrate, including:

[0005] A substrate, including a display area and a non-display area located on at least one side of the display area;

[0006] A thin film transistor, disposed on the substrate, and the thin film transistor is located in the display area;

[0007] A passivation layer, disposed on the thin film transistor and the substrate;

[0008] Wherein, the passivation layer includes a first passivation layer located in the display area and a second passivation layer located in the non-display area. The first passivation layer and the second passivation layer are disposed in the same layer, and the light transmittance of the first passivation layer is higher than that of the second passivation layer.

[0009] In an optional embodiment of this application, the material of the first passivation layer is silicon oxide.

[0010] In an optional embodiment of this application, the material of the second passivation layer is silicon nitride.

[0011] In an optional embodiment of this application, the thin film transistor includes: an active layer, a gate insulating layer, a gate, a source electrode, and a drain electrode; wherein, the active layer is disposed on the substrate, the gate insulating layer is disposed on the active layer, the gate is disposed on the gate insulating layer, the source electrode and the drain electrode are disposed on the gate, and the passivation layer is disposed on the source electrode and the drain electrode.

[0012] In an optional embodiment of the present application, the thin-film transistor includes: a gate, a gate insulating layer, an active layer, a source electrode, and a drain electrode; wherein, the gate is disposed on the substrate, the gate insulating layer is disposed on the gate, the active layer is disposed on the gate insulating layer, the source electrode and the drain electrode are disposed on the active layer, and the passivation layer is disposed on the source electrode and the drain electrode.

[0013] In an optional embodiment of the present application, the array substrate further includes a first electrode layer and a second electrode layer, the first electrode layer is disposed on a side of the passivation layer close to the source electrode and the drain electrode, and the second electrode layer is disposed on a side of the passivation layer away from the source electrode and the drain electrode.

[0014] In a second aspect, the present application provides a method for manufacturing an array substrate, including:

[0015] Providing a substrate, the substrate includes a display area and a non-display area located on at least one side of the display area;

[0016] Forming a thin-film transistor on the substrate, the thin-film transistor is formed in the display area;

[0017] Forming a first passivation layer on the thin-film transistor and the substrate, the first passivation layer is formed in the display area;

[0018] Forming a second passivation layer on the substrate, the second passivation layer is formed in the non-display area, and the second passivation layer is disposed on the same layer as the first passivation layer;

[0019] Wherein, the light transmittance of the first passivation layer is higher than that of the second passivation layer.

[0020] In an optional embodiment of the present application, the material of the first passivation layer is silicon oxide.

[0021] In an optional embodiment of the present application, the material of the second passivation layer is silicon nitride.

[0022] In a third aspect, the present application provides a display panel, including the array substrate as described above.

[0023] The present application provides an array substrate, a preparation method thereof, and a display panel. In the present application, the passivation layer of the array substrate is divided into two regions, namely, a first passivation layer located in the display area and a second passivation layer located in the non-display area. The light transmittance of the first passivation layer is higher than that of the second passivation layer. By using a material with a higher transmittance in the display area of the array substrate, the present application improves the transmittance of the array substrate and ensures the normal ability of the second passivation layer in the non-display area to block external moisture and impurity ions. This array substrate structure can improve the transmittance of the array substrate without affecting the reliability of the array substrate, thereby improving the performance of the display panel. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0025] Figure 1 It is a schematic structural diagram of an array substrate provided by an embodiment of the present application.

[0026] Figure 2 It is a schematic structural diagram of a display panel provided by an embodiment of the present application. Detailed Embodiments

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present application.

[0028] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "upper" and "lower" is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "multiple" means two or more, unless otherwise specifically defined.

[0029] This application may repeatedly reference numerals and / or reference letters in different embodiments. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or arrangements discussed.

[0030] In the prior art, in order to improve the transmittance of the array substrate, the passivation layer (PV layer) of the array substrate is entirely replaced with a material having a higher transmittance. However, since the film layer of the passivation layer in the display area affects the transmittance of the array substrate, and the film layer of the passivation layer in the non-display area outside the display area affects the reliability (i.e., the ability of the array substrate to resist external moisture and impurity ions). In some cases, after the passivation layer is entirely replaced with a material having a higher transmittance, although the transmittance of the array substrate is significantly improved, in the non-display area, external moisture and impurity ions can easily enter the display area through the passivation layer, thereby reducing the reliability of the array substrate.

[0031] To solve the above problems, this application provides an array substrate that can improve the transmittance of the array substrate while ensuring that the reliability of the array substrate is not affected.

[0032] The array substrate 100 provided by this application includes:

[0033] A substrate 110, including a display area AA and a non-display area RA located on at least one side of the display area AA;

[0034] A thin film transistor 120, disposed on the substrate 110, and the thin film transistor 120 is located within the display area AA;

[0035] A passivation layer 180, disposed on the thin film transistor 120 and the substrate 110;

[0036] Wherein, the passivation layer 180 includes a first passivation layer 181 located in the display area AA and a second passivation layer 182 located in the non-display area RA. The first passivation layer 181 and the second passivation layer 182 are disposed in the same layer, and the light transmittance of the first passivation layer 181 is higher than the light transmittance of the second passivation layer 182.

[0037] In this application, the passivation layer 180 of the array substrate 100 is divided into two regions, namely the first passivation layer 181 located in the display area AA and the second passivation layer 182 located in the non-display area RA. The light transmittance of the material of the first passivation layer 181 is higher than that of the material of the second passivation layer 182. By using a material with a higher transmittance in the display area AA, the transmittance of the display area AA of the array substrate 100 is increased, and the ability of the second passivation layer 182 in the non-display area RA to normally block external moisture and impurity ions is ensured. The structure of the array substrate 100 can effectively improve the transmittance of the array substrate 100 without affecting the reliability of the array substrate 100.

[0038] In this application, the array substrate 100 can be an array substrate of types such as a-Si TFT (amorphous silicon), LTPS TFT (low-temperature polycrystalline silicon), HTPS TFT (high-temperature polycrystalline silicon), LTPO TFT (low-temperature polycrystalline oxide), IGZO TFT (indium gallium zinc oxide - metal oxide), etc.

[0039] In this application, the thin film transistor 120 includes: a gate 123, a gate insulating layer 122, an active layer 121, a source electrode 124, and a drain electrode 125; the gate 123 is disposed on the substrate 110, the gate insulating layer 122 is disposed on one side of the gate 123, the active layer 121 is disposed on the side of the gate 123 away from the gate insulating layer 122, and the source electrode 124 and the drain electrode 125 are disposed on the active layer 121. The thin film transistor 120 can be a bottom-gate structure or a top-gate structure.

[0040] In some embodiments, the array substrate 100 further includes a light shielding layer 130 (LS layer) disposed on the side of the substrate 110 close to the thin film transistor 120, a buffer layer 140 (buffer layer) disposed on the side of the light shielding layer 130 away from the substrate 110, an interlayer insulating layer 150 (ILD layer) disposed on the side of the source electrode 124 and the drain electrode 125 close to the substrate 110, a planarization layer 160 (PLN layer) disposed on the side of the source electrode 124 and the drain electrode 125 away from the substrate 110, a first electrode layer 170 (BITO) disposed on the side of the passivation layer 180 close to the source electrode 124 and the drain electrode 125, a second electrode layer 190 (TITO) disposed on the side of the passivation layer 180 away from the source electrode 124 and the drain electrode 125, and other film layers.

[0041] The array substrate 100 provided in this application will be described in detail below in combination with specific embodiments and the accompanying drawings.

[0042] As Figure 1As shown, it is a schematic structural diagram of an array substrate 100 provided by an embodiment of the present application. In this embodiment, the array substrate 100 is of the LTPS TFT type.

[0043] The array substrate 100 includes: a substrate substrate 110, a light-shielding layer 130, a buffer layer 140, a thin-film transistor 120, an interlayer insulating layer 150, a planarizing layer 160, a first electrode layer 170, a passivation layer 180, and a second electrode layer 190.

[0044] The substrate substrate 110 includes a display area AA and a non-display area RA surrounding the display area AA.

[0045] The light-shielding layer 130 is disposed on one side of the substrate substrate 110 and is opposite to the thin-film transistor 120.

[0046] The buffer layer 140 is disposed on a side of the light-shielding layer 130 away from the substrate substrate 110.

[0047] Furthermore, the buffer layer 140 includes a first buffer layer 141 and a second buffer layer 142. The first buffer layer 141 is disposed on a side of the light-shielding layer 130 away from the substrate substrate 110, and the second buffer layer 142 is disposed on a side of the first buffer layer 141 away from the light-shielding layer 130. Among them, the material of the first buffer layer 141 may be silicon nitride, and the material of the second buffer layer 142 may be silicon oxide.

[0048] The thin-film transistor 120 is disposed on a side of the buffer layer 140 away from the light-shielding layer 130, and the thin-film transistor 120 is located within the display area AA. Specifically, as Figure 1 shown, the thin-film transistor 120 includes: an active layer 121, a gate insulating layer 122, a gate 123, a source 124, and a drain 125; the active layer 121 is disposed on a side of the buffer layer 140 away from the light-shielding layer 130, the gate insulating layer 122 is disposed on a side of the active layer 121 away from the buffer layer 140, the gate 123 is disposed on a side of the gate insulating layer 122 away from the active layer 121, and the source 124 and the drain 125 are disposed on a side of the gate 123 away from the gate insulating layer 122.

[0049] The above is the thin film transistor 120 of the top gate structure. In some embodiments, the thin film transistor 120 may also be of the bottom gate structure. The thin film transistor of the bottom gate structure includes: a gate 123, a gate insulating layer 122, an active layer 121, a source electrode 124, and a drain electrode 125. Among them, the gate 123 is disposed on a side of the buffer layer 140 away from the light shielding layer 130, the gate insulating layer 122 is disposed on a side of the gate 123 away from the buffer layer 140, the active layer 121 is disposed on a side of the gate insulating layer 122 away from the gate 123, and the source electrode 124 and the drain electrode 125 are disposed on a side of the active layer 121 away from the gate insulating layer 122.

[0050] The interlayer insulating layer 150 is disposed on a side of the source electrode 124 and the drain electrode 125 close to the gate 123 and covers the gate 123.

[0051] Further, the interlayer insulating layer 150 includes a first interlayer insulating layer 151 and a second interlayer insulating layer 152. The first interlayer insulating layer 151 is disposed on a side of the gate 123 away from the gate insulating layer 122 and covers the gate 123. The second interlayer insulating layer 152 is disposed on a side of the first interlayer insulating layer 151 away from the gate 123. Among them, the material of the first interlayer insulating layer 151 is silicon nitride, and the material of the second interlayer insulating layer 152 is silicon oxide.

[0052] The planarization layer 160 is disposed on a side of the source electrode 124 and the drain electrode 125 away from the interlayer insulating layer 150 and covers the source electrode 124 and the drain electrode 125.

[0053] The first electrode layer 170 is disposed on a side of the planarization layer 160 away from the source electrode 124 and the drain electrode 125. Further, the first electrode layer 170 may be a common electrode layer.

[0054] The passivation layer 180 is disposed on a side of the first electrode layer 170 away from the planarization layer 160. The passivation layer 180 includes a first passivation layer 181 in the display area AA and a second passivation layer 182 in the non-display area RA. The first passivation layer 181 and the second passivation layer 182 are disposed in the same layer, and the light transmittance of the first passivation layer 181 is higher than that of the second passivation layer 182.

[0055] Specifically, the material of the first passivation layer 181 can be silicon oxide, and the material of the second passivation layer 182 can be silicon nitride. Silicon oxide and silicon nitride are common materials for inorganic insulating protective layers in the array substrate 100. Usually, a whole layer of silicon oxide or silicon nitride is formed to cover the thin film transistor 120 and the substrate 110. However, the properties of the silicon oxide film and the silicon nitride film are different. Compared with the silicon oxide film, the silicon nitride film has stronger compactness but lower light transmittance. When the passivation layer 180 is a whole layer of silicon nitride film, although the ability of the passivation layer 180 to block water vapor and impurity ions can be ensured, the silicon nitride will affect the transmittance of the array substrate 100; when the passivation layer 180 is a whole layer of silicon oxide film, the transmittance of the display panel can be significantly improved, but due to the poor ability of the silicon oxide film to block water vapor and impurity ions, external water vapor and impurity ions will enter the display area AA through the silicon oxide film layer in the non-display area RA located outside the display area AA, thereby reducing the reliability of the array substrate 100.

[0056] Therefore, in this application, the passivation layer 180 is divided into two parts, that is, the first passivation layer 181 made of silicon oxide material in the display area AA and the second passivation layer 182 made of silicon nitride material in the non-display area RA. The first passivation layer 181 and the second passivation layer 182 are arranged in the same layer. In this way, both the transmittance of the display area AA of the array substrate 100 can be improved, and the ability of the passivation film in the non-display area RA of the array substrate 100 to block external water vapor and impurity ions can be ensured, thereby improving the transmittance of the array substrate 100 while ensuring the reliability of the array substrate 100.

[0057] The second electrode layer 190 is disposed on a side of the passivation layer 180 away from the first electrode layer 170. Further, the second electrode layer 190 can be a pixel electrode layer.

[0058] This application also provides a method for manufacturing an array substrate 100, including:

[0059] Providing a substrate 110, the substrate 110 includes a display area AA and a non-display area RA located on at least one side of the display area AA;

[0060] Forming a thin film transistor 120 on the substrate 110, the thin film transistor 120 is formed in the display area AA;

[0061] Forming a first passivation layer 181 on the thin film transistor 120 and the substrate 110, the first passivation layer 181 is formed in the display area AA;

[0062] A second passivation layer 182 is formed on the substrate 110, and the second passivation layer 182 is formed within the non-display area RA and is provided in the same layer as the first passivation layer 181;

[0063] Among them, the light transmittance of the first passivation layer 181 is higher than that of the second passivation layer 182.

[0064] Hereinafter, a method for manufacturing the array substrate 100 provided in the present application will be described in detail with reference to specific embodiments.

[0065] The method for manufacturing the array substrate 100 includes the following steps:

[0066] S1: Provide a substrate 110, which includes a display area AA and a non-display area RA surrounding the display area AA. Specifically, the substrate 110 can be a rigid substrate or a flexible substrate. The material of the rigid substrate can be glass, and the material of the flexible substrate can be a polymer, such as polyimide, etc.

[0067] S2: Deposit a light-shielding layer 130 on the substrate 110, and perform patterning on the light-shielding layer 130 through a patterning process (exposure, development, etching) to obtain a light-shielding layer 130 pattern.

[0068] S3: Deposit a buffer layer 140 on the substrate 110, and the buffer layer 140 covers the light-shielding layer 130. The material of the buffer layer 140 can be silicon oxide or silicon nitride.

[0069] In some embodiments, the buffer layer 140 may include multiple film layers. For example, the buffer layer 140 may include a first buffer layer 141 and a second buffer layer 142 located on the first buffer layer 141. The manufacturing method includes: first depositing the first buffer layer 141 on the substrate, and the first buffer layer 141 covers the light-shielding layer 130, and then depositing the second buffer layer 142 on the first buffer layer 141. The material of the first buffer layer 141 can be silicon nitride, and the material of the second buffer layer 142 can be silicon oxide.

[0070] S4: Deposit an active layer 121 on the buffer layer 140. The material of the active layer 121 is amorphous silicon a-Si. Through an excimer laser annealing (ELA) process, a-Si is transformed into polycrystalline silicon to form a polycrystalline silicon active layer 121, and then patterning is performed on the active layer 121 through a patterning process (exposure, development, etching) to obtain a Poly-Si pattern of the active layer 121.

[0071] S5: Deposit a gate insulating layer 122 on the active layer 121, and the gate insulating layer 122 covers the active layer 121.

[0072] S6: Deposit a gate 123 on the gate insulating layer 122, and pattern the gate 123 through a patterning process (exposure, development, etching) to obtain a gate 123 pattern. Then, use the gate 123 as a mask to form a heavily doped region and a lightly doped region of the active layer 121.

[0073] S7: Deposit an interlayer insulating layer 150 on the gate 123, and the interlayer insulating layer 150 covers the light-shielding layer 130. Pattern the interlayer insulating layer 150 through a patterning process (exposure, development, etching) to form a pattern of a first via hole in the interlayer insulating layer 150. The material of the interlayer insulating layer 150 can be silicon oxide or silicon nitride.

[0074] In some embodiments, the interlayer insulating layer 150 may include multiple film layers. For example, the interlayer insulating layer 150 may include a first interlayer insulating layer 151 and a second interlayer insulating layer 152 located on the first interlayer insulating layer 151. The preparation method includes: first, deposit the first interlayer insulating layer 151 on the gate 123, and the first interlayer insulating layer 151 covers the gate 123. Then, deposit the second interlayer insulating layer 152 on the first interlayer insulating layer 151. The material of the first interlayer insulating layer 151 can be silicon nitride, and the material of the second interlayer insulating layer 152 can be silicon oxide.

[0075] S8: Deposit a source-drain metal layer on the interlayer insulating layer 150, and pattern the source-drain metal layer through a patterning process (exposure, development, etching) to form patterns of the source electrode 124 and the drain electrode 125. Among them, the source electrode 124 and the drain electrode 125 are electrically connected to the active layer 121 through the first via hole.

[0076] S9: Deposit a planarization layer 160 on the source electrode 124 and the drain electrode 125, and the planarization layer 160 covers the source electrode 124 and the drain electrode 125. Pattern the planarization layer 160 through a patterning process (exposure, development, etching) to form a pattern of a second via hole in the planarization layer 160, and the second via hole exposes the drain electrode 125.

[0077] S10: Deposit a first electrode layer 170 on the flat layer 160. The material of the first electrode layer 170 can be indium tin oxide (ITO), and perform patterning on the first electrode layer 170 through a patterning process (exposure, development, etching) to obtain the pattern of the first electrode layer 170. Among them, a hole is formed in the first electrode layer 170 that penetrates the first electrode layer 170 and communicates with the second via. The first electrode layer 170 can be a common electrode.

[0078] S11: Deposit a first passivation layer 181 on the first electrode layer 170, and perform patterning on the first passivation layer 181 through a patterning process (exposure, development, etching), and remove the part of the first passivation layer located in the non-display area RA to obtain the pattern of the first passivation layer 181 located in the display area AA. And a hole is formed in the first passivation layer 181 that penetrates the first passivation layer 181 and communicates with the second via. The material of the first passivation layer 181 can be silicon oxide.

[0079] S12: Deposit a second passivation layer 182 on the first passivation layer 181, and perform patterning on the second passivation layer 182 through a patterning process (exposure, development, etching), and remove the part of the second passivation layer in the display area AA to obtain the pattern of the second passivation layer 182 located in the non-display area RA. Among them, the second passivation layer 182 is provided on the same layer as the first passivation layer 181. The material of the second passivation layer 182 can be silicon nitride.

[0080] S13: Deposit a second electrode layer 190 on the first passivation layer 181 and the second passivation layer 182. The material of the second electrode layer 190 can be indium tin oxide (ITO), and perform patterning on the second electrode layer 190 through a patterning process (exposure, development, etching) to obtain the pattern of the second electrode layer 190. Among them, the second electrode layer 190 is electrically connected to the drain 125 through the second via. The second electrode layer 190 can be a pixel electrode.

[0081] This application also provides a display panel, including the array substrate 100 as described above.

[0082] As Figure 2 shown, it is a schematic structural diagram of a display panel provided by an embodiment of this application.

[0083] The display panel provided in this embodiment is a liquid crystal display panel, but the type of display panel protected by this application is not limited thereto.

[0084] Specifically, as Figure 2As shown, the display panel includes an array substrate 100, a color filter substrate 200 disposed opposite to the array substrate 100, a sealant 300 located between the array substrate 100 and the color filter substrate 200, a liquid crystal layer 400 located in a sealed space surrounded by the array substrate 100, the color filter substrate 200 and the sealant 300, and support pillars 500 located between the array substrate 100 and the color filter substrate 200.

[0085] Among them, the array substrate 100 includes:

[0086] A substrate substrate 110, including a display area AA and a non-display area RA located on at least one side of the display area AA;

[0087] Thin film transistors 120 are disposed on the substrate substrate, and the thin film transistors 120 are located within the display area AA;

[0088] A passivation layer 180 is disposed on the thin film transistors 120 and the substrate substrate 110;

[0089] Among them, the passivation layer 180 includes a first passivation layer 181 located in the display area AA and a second passivation layer 182 located in the non-display area RA. The first passivation layer 181 and the second passivation layer 182 are provided in the same layer, and the light transmittance of the first passivation layer 181 is higher than that of the second passivation layer 182.

[0090] In some embodiments, the material of the first passivation layer 181 is silicon oxide, and the material of the second passivation layer 182 is silicon nitride.

[0091] In some embodiments, the thin film transistor 120 includes: a gate 123, a gate insulating layer 122, an active layer 121, a source 124 and a drain 125; the gate 123 is disposed on the substrate substrate 110, the gate insulating layer 122 is disposed on one side of the gate 123, the active layer 121 is disposed on the side of the gate 123 away from the gate insulating layer 122, and the source 124 and the drain 125 are disposed on the active layer 121. The thin film transistor 120 can be a bottom-gate structure or a top-gate structure.

[0092] In some embodiments, the array substrate 100 further includes a light shielding layer 130 (LS layer) disposed on one side of the substrate substrate 110 close to the thin film transistor 120, a buffer layer 140 (buffer layer) disposed on one side of the light shielding layer 130 away from the substrate substrate 110, an interlayer insulating layer 150 (ILD layer) disposed on one side of the source electrode 124 and the drain electrode 125 close to the substrate substrate 110, a planarization layer 160 (PLN layer) disposed on one side of the source electrode 124 and the drain electrode 125 away from the substrate substrate 110, a first electrode layer 170 (BITO) disposed on one side of the passivation layer 180 close to the source electrode 124 and the drain electrode 125, a second electrode layer 190 (TITO) disposed on one side of the passivation layer 180 away from the source electrode 124 and the drain electrode 125, and other film layers.

[0093] The present application provides an array substrate, a preparation method thereof, and a display panel. The present application divides the passivation layer of the array substrate into two regions, namely a first passivation layer located in the display area AA and a second passivation layer located in the non-display area RA. The light transmittance of the first passivation layer is higher than that of the second passivation layer. By using a material with a higher transmittance in the display area AA of the array substrate, the transmittance of the array substrate is increased, and the ability of the second passivation layer in the non-display area RA to normally block external moisture and impurity ions is ensured. This array substrate structure can improve the transmittance of the array substrate without affecting the reliability of the array substrate, and further improve the performance of the display panel.

[0094] In summary, although the present application has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Those of ordinary skill in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is subject to the scope defined by the claims.

Claims

1. An array substrate, characterized in that: include: A base substrate, comprising a display area and a non-display area located at at least one side of the display area; A thin film transistor is disposed on the base substrate, and the thin film transistor is located in the display area; a passivation layer, disposed on the thin film transistor and the base substrate; In which, the passivation layer includes a first passivation layer located in the display area and a second passivation layer located in the non-display area, the first passivation layer and the second passivation layer are arranged on the same layer, the material of the first passivation layer is different from the material of the second passivation layer, the first passivation layer and the second passivation layer are in contact with each other at the junction of the display area and the non-display area, and the light transmittance of the first passivation layer is higher than the light transmittance of the second passivation layer, and the density of the second passivation layer is greater than the density of the first passivation layer.

2. The array substrate according to claim 1, wherein: The material of the first passivation layer is silicon oxide.

3. The array substrate according to claim 2, wherein: The material of the second passivation layer is silicon nitride.

4. The array substrate according to claim 1, wherein: The thin film transistor includes: an active layer, a gate insulating layer, a gate, a source and a drain; wherein the active layer is arranged on the base substrate, the gate insulating layer is arranged on the active layer, the gate is arranged on the gate insulating layer, the source and the drain are arranged on the gate, and the passivation layer is arranged on the source and the drain.

5. The array substrate according to claim 1, wherein: The thin film transistor includes: a gate, a gate insulating layer, an active layer, a source and a drain; wherein the gate is arranged on the base substrate, the gate insulating layer is arranged on the gate, the active layer is arranged on the gate insulating layer, the source and the drain are arranged on the active layer, and the passivation layer is arranged on the source and the drain.

6. The array substrate according to any one of claims 4 to 5, wherein: The array substrate further includes a first electrode layer and a second electrode layer. The first electrode layer is arranged on a side of the passivation layer close to the source and the drain, and the second electrode layer is arranged on a side of the passivation layer away from the source and the drain.

7. A method for preparing an array substrate, characterized in that: include: Providing a base substrate, the base substrate comprising a display area and a non-display area located at at least one side of the display area; forming a thin film transistor on the base substrate, wherein the thin film transistor is formed in the display area; forming a first passivation layer on the thin film transistor and the base substrate, wherein the first passivation layer is formed in the display area; forming a second passivation layer on the base substrate, wherein the second passivation layer is formed in the non-display area and is disposed on the same layer as the first passivation layer, the first passivation layer and the second passivation layer are made of different materials, and the second passivation layer and the first passivation layer are in contact with each other at a boundary between the display area and the non-display area; The light transmittance of the first passivation layer is higher than that of the second passivation layer, and the density of the second passivation layer is greater than that of the first passivation layer.

8. The method for preparing an array substrate according to claim 7, wherein: The material of the first passivation layer is silicon oxide.

9. The method for preparing an array substrate according to claim 8, wherein: The material of the second passivation layer is silicon nitride.

10. A display panel, characterized in that: The invention comprises an array substrate as claimed in any one of claims 1 to 6.

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