A PFC circuit, switching power supply and computing device

Abstract

Embodiments of the present application disclose a PFC circuit, a switching power supply and a computing device. The PFC circuit comprises a first voltage boosting branch, a second voltage boosting branch and a controller. The first voltage boosting branch comprises a first switch tube. The second voltage boosting branch comprises a second switch tube. The control end of the first switch tube and the control end of the second switch tube are electrically connected to two control ends of the controller respectively. The controller is configured to: acquire a first period of a first pulse width modulation signal of the first switch tube and a second period of a second pulse width modulation signal of the second switch tube; the first pulse width modulation signal is used for controlling the working state of the first switch tube, and the second pulse width modulation signal is used for controlling the working state of the second switch tube; determine a first difference value between the first period and the second period; and based on the first difference value, adjust the maintaining time length of the conduction control level in the second pulse width modulation signal. By using the embodiments of the present application, the ripple current in the output of the switching power supply can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a PFC circuit, a switching power supply and a computing device. BACKGROUND

[0002] With the progress of power electronics technology, the power consumption of Internet Technology (IT) devices is getting larger and larger, and the power demand of the power supply for the IT devices is also getting larger and larger. The traditional single-phase boost power factor correction (PFC) circuit is not suitable for the rectifier circuit in the front end of the high-power power supply. In high-power applications, a multi-parallel boost PFC circuit is often used. Due to the small output ripple current and small branch power level of the interleaved multi-parallel boost PFC circuit, it is widely used in medium and high-power power supplies. However, due to the difference between the devices in the circuit, the periods of the boost circuits in each phase are not completely the same, and they cannot work in the interleaved state, which leads to a large ripple current output by the PFC circuit. SUMMARY

[0003] The PFC circuit, the switching power supply and the computing device provided by the embodiments of the present application can reduce the ripple current in the output of the switching power supply.

[0004] In a first aspect, the embodiments of the present application provide a PFC circuit, which comprises a first boost branch, a second boost branch and a controller. The first boost branch comprises a first switch tube, and the second boost branch comprises a second switch tube. The control end of the first switch tube and the control end of the second switch tube are electrically connected to two control ends of the controller. The controller is configured to: obtain a first period of a first pulse width modulation signal of the first switch tube and a second period of a second pulse width modulation signal of the second switch tube; the first pulse width modulation signal is used to control the working state of the first switch tube, and the second pulse width modulation signal is used to control the working state of the second switch tube; determine a first difference value between the first period and the second period; and adjust the maintenance time length of the on control level in the second pulse width modulation signal based on the first difference value.

[0005] In a possible design, when the switch tube in the PFC circuit is an NMOS tube, the on control level is a high level; and when the switch tube in the PFC circuit is a PMOS tube, the on control level is a low level.

[0006] The period of the pulse width modulation signal of each phase boost branch is obtained, and the high level of the pulse width modulation signal of each phase boost branch is compensated in advance based on the period of the pulse width modulation signal of one phase boost branch, so that the period of the pulse width modulation signal of each phase boost branch is the same as the period of the pulse width modulation signal of one phase boost branch. The high level and low level of the pulse width modulation signal of each phase boost branch are staggered, so that the N-phase boost branch works in a staggered state, and the output ripple current is reduced.

[0007] In one possible design, the controller is configured to adjust, based on the first difference, a duration of the high level in the second pulse width modulation signal, including:

[0008] The controller is configured to:

[0009] The first difference is multiplied by a first compensation factor to obtain a first compensation value, where the first compensation factor is determined based on the AC input voltage and the output voltage of the PFC.

[0010] The duration of the high level in the second pulse width modulation signal is added or subtracted by the first compensation value.

[0011] By compensating the duration of the high level in the second pulse width modulation signal, the high level for the second boost branch is output according to the compensated duration of the high level, the charging duration of the inductor L2 in the second boost branch is changed, the discharging duration of the inductor L2 in the second boost branch is changed, and the second period of the second pulse width modulation signal of the second boost branch is adjusted. The second period of the second pulse width modulation signal of the second boost branch is close to or equal to the first period of the first pulse width modulation signal of the first boost branch.

[0012] In another possible design, the controller is configured to obtain a first period of a first pulse width modulation signal of a first switch tube and a second period of a second pulse width modulation signal of a second switch tube, including:

[0013] The controller is configured to:

[0014] The first level signal is output to the control end of the first switch tube.

[0015] The second level signal is output to the control end of the second switch tube.

[0016] The first period of the first pulse width modulation signal of the first switch tube is obtained based on the first level signal, and the second period of the second pulse width modulation signal of the second switch tube is obtained based on the second level signal.

[0017] The first level signal and the second level signal are high level signals with the same duration.

[0018] In another possible design, the controller is configured to obtain a first period of the first pulse width modulation signal based on the first level signal and a second period of the second pulse width modulation signal based on the second level signal; and the controller comprises:

[0019] The controller is configured to:

[0020] The controller is configured to obtain a current of the first inductor based on the first level signal, determine the first period of the first pulse width modulation signal according to a zero-crossing time of the current of the first inductor, and obtain a current of the second inductor based on the second level signal, and determine the second period of the second pulse width modulation signal according to a zero-crossing time of the current of the second inductor. The first period of the first pulse width modulation signal and the second period of the second pulse width modulation signal are obtained respectively based on the zero-crossing time, thereby improving the accuracy of obtaining the periods.

[0021] In another possible design, the first boost branch further includes a first inductor and a first diode; a first end of the first inductor is electrically connected to a positive pole of the AC power supply; a first end of the first switch tube, a second end of the first inductor, and an anode of the first diode are electrically connected; a cathode of the first diode is electrically connected to a first end of the load; a second end of the first switch tube, a negative pole of the AC power supply, and a second end of the load are electrically connected; a control end of the first switch tube is electrically connected to a first control signal output end of the controller;

[0022] The second boost branch further includes a second inductor and a second diode; a first end of the first inductor is electrically connected to a positive pole of the AC power supply; a first end of the second switch tube, a second end of the second inductor, and an anode of the second diode are electrically connected; a cathode of the second diode is electrically connected to a first end of the load; a second end of the second switch tube, a negative pole of the AC power supply, and a second end of the load are electrically connected; a control end of the second switch tube is electrically connected to a second control signal output end of the controller.

[0023] In another possible design, the first boost branch further includes a first inductor and a third switch tube; a first end of the first inductor is electrically connected to a positive pole of the AC power supply; a first end of the first switch tube, a second end of the first inductor, and a second end of the third switch tube are electrically connected; a first end of the third switch tube is electrically connected to a first end of the load; a second end of the first switch tube, a negative pole of the AC power supply, and a second end of the load are electrically connected; a third end of the first switch tube is electrically connected to a first control signal output end of the controller; a third end of the third switch tube is electrically connected to a third control signal output end of the controller.

[0024] The second boost branch further includes a second inductor and a fourth switch tube; a first end of the second inductor is electrically connected to the positive pole of the alternating power supply; a first end of the fourth switch tube, a second end of the second inductor and a second end of the fourth switch tube are electrically connected; a second end of the second switch tube, the negative pole of the alternating power supply and a second end of the load are electrically connected; a control end of the second switch tube is electrically connected to a second control signal output end of the controller; and a control end of the fourth switch tube is electrically connected to a fourth control signal output end of the controller.

[0025] The controller is further configured to obtain a fourth period of a fourth pulse width modulation signal for controlling the fourth switch tube, wherein the fourth pulse width modulation signal is used to control the working state of the fourth switch tube.

[0026] The controller is further configured to adjust the duration of the high level in the fourth pulse width modulation signal based on the first difference.

[0027] Regardless of whether the alternating power supply input is in the positive half cycle or the negative half cycle, a compensation value is determined, and the duration of the high level in the second PWM signal is compensated according to the same compensation value. Thus, the number of compensation operations is reduced, and the compensation efficiency is improved.

[0028] In another possible design, the controller is configured to:

[0029] When the alternating power supply input is in the positive half cycle, the duration of the high level in the second pulse width modulation signal is adjusted based on the first difference; and / or, when the alternating power supply input is in the negative half cycle, the duration of the high level in the fourth pulse width modulation signal is adjusted based on the first difference.

[0030] By respectively adjusting the duration of the high level in the second pulse width modulation signal of the second switch tube when the alternating power supply input is in the positive half cycle and adjusting the duration of the high level in the fourth pulse width modulation signal of the fourth switch tube when the alternating power supply input is in the negative half cycle, the accuracy of compensation is improved.

[0031] In another possible design, the controller is further configured to:

[0032] The controller is further configured to determine whether the first difference exceeds a preset threshold.

[0033] When the first difference exceeds the preset threshold, the duration of the high level in the second pulse width modulation signal is adjusted based on the first difference.

[0034] By compensating the duration of the high level in the second pulse width modulation signal when the first difference exceeds the preset threshold, the number of compensation operations is reduced, and the working efficiency of the PFC circuit is improved.

[0035] In another possible design, the PFC circuit includes a plurality of second boost branches.

[0036] In a second aspect, an embodiment of the present application provides a switching power supply, which includes a PFC circuit in any possible implementation of the first aspect.

[0037] In a third aspect, an embodiment of the present application provides a computing device, which includes the switching power supply in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0039] Figure 1 This is a schematic diagram of a PFC circuit;

[0040] Figure 2 This is a schematic diagram of another PFC circuit;

[0041] Figure 3 This is a waveform diagram of a PFC circuit;

[0042] Figure 4 This is another waveform diagram of a PFC circuit;

[0043] Figure 5 This is a flow chart of a phase compensation method provided in an embodiment of the present application;

[0044] Figure 6 is a schematic diagram of phase compensation provided by an embodiment of the present application;

[0045] Figure 7 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0047] like Figure 1 As shown, Figure 1 This is a schematic diagram of a PFC circuit. The PFC circuit may include a bridge rectifier circuit 101, a boost circuit 102, a controller 103, and a driver 104.

[0048] The bridge rectifier circuit 101 is used to receive an input voltage V1 and provide an output voltage V2. The bridge rectifier circuit 101 can convert alternating current (AC) with positive and negative variations into unidirectional pulsating DC.

[0049] The boost circuit 102 includes N-phase boost branches and a capacitor C, and the N-phase boost branches are connected in parallel and then connected to the capacitor C. In the boost circuit 102, taking the 2-phase boost branches as an example, the boost branch 1 and the boost branch 2 are described as follows, Figure 1 Only the 2-phase boost branches (the boost branch 1 and the boost branch 2) are described. Each phase boost branch includes an inductor, a switch tube and a diode. The one end of the inductor is electrically connected to the output end of the bridge rectifier circuit 101, the other end of the inductor is electrically connected to the anode of the diode and the first electrode of the switch tube respectively, the cathode of the diode is electrically connected to one end of the capacitor C, the second electrode of the switch tube is electrically connected to the driver 104, and the third electrode of the switch tube and the other end of the capacitor C are grounded. The boost circuit 102 is configured to receive the output voltage V2 of the bridge rectifier circuit 101, and provide an output voltage V0 to a subsequent circuit (for example, a load) based on a driving signal of the driver 104.

[0050] The controller 103 is electrically connected to the one end of the inductor in each phase boost branch, and is configured to sample the current of the inductor in each phase boost branch and output a pulse width modulation (PWM) signal according to the current of the inductor in each phase boost branch. The controller can be a micro controller unit (MCU).

[0051] The driver 104 is electrically connected to the controller 103, and is configured to drive the switch tube in each phase boost branch of the boost circuit 102 to be turned on or turned off according to the PWM signal output by the controller 103.

[0052] The control principle of the boost circuit 102 is as follows: first, the controller 103 outputs a high-level PWM1 signal to the driver 104, the driver 104 amplifies the high-level PWM1 signal and outputs the amplified signal to the switch tube Q1 in the boost branch 1, so as to control the switch tube Q1 to be turned on, and at this time, the inductor L1 is charged. Then, after a time t1, the controller 103 outputs a low-level PWM1 signal, the driver 104 amplifies the low-level PWM1 signal and outputs the amplified signal to the switch tube Q1 in the boost branch 1, so as to control the switch tube Q1 in the boost branch 1 to be turned off, and at this time, the inductor L1 is discharged. After a time t2, when the inductor L1 is completely discharged, the controller 103 can sample the current of the inductor L1 to be 0, and the controller 103 outputs a high-level PWM1 signal again. At this time, the previous cycle ends and the next cycle begins. The control principle of the boost branch 2 is similar to the above, and is not described herein.

[0053] It should be understood that, in the PFC circuit shown in FIG. 1, Figure 1 It should be understood that, in the PFC circuit shown in FIG. 1,

[0054] As Figure 2 shown, Figure 2 is another schematic diagram of a PFC circuit. The PFC circuit can include a bridgeless rectifier circuit 201, a boost circuit 202, a controller 203 and a driver 204. Among them:

[0055] The bridgeless rectifier circuit 201 includes a switch tube Q1 and a switch tube Q2. When the AC power input is in the positive half cycle, the switch tube Q1 is off and the switch tube Q2 is on. When the AC power input is in the negative half cycle, the switch tube Q1 is on and the switch tube Q2 is off. The bridgeless rectifier circuit 201 is used to receive an input voltage V1 and provide an output voltage V2.

[0056] The boost circuit 202 includes N-phase boost branches and a capacitor C, and the N-phase boost branches are connected in parallel to the capacitor C. In the boost circuit 202, taking a 2-phase boost branch as an example, Figure 2 Only 2-phase boost branches (boost branch 1 and boost branch 2) are given. Each phase boost branch includes an inductor, a first switch tube and a second switch tube. Among them, one end of the inductor is electrically connected to the output end of the bridgeless rectifier circuit 201, the other end of the inductor is electrically connected to the first pole of the first switch tube and the second pole of the second switch tube respectively, the second pole of the first switch tube is electrically connected to one end of the capacitor C, the first pole of the second switch tube and the other end of the capacitor C are grounded. The third pole of the first switch tube and the third pole of the second switch tube are electrically connected to the driver 204 respectively. The boost circuit 102 is used to receive the output voltage V2 of the bridgeless rectifier circuit 201, and based on the driving signal of the driver 204, to provide an output voltage V0 to the rear stage circuit (such as a load).

[0057] The controller 203 is electrically connected to one end of the inductor in each phase boost branch, and is used to sample the current of the inductor in each phase boost branch, and output a PWM signal according to the current of the inductor in each phase boost branch.

[0058] The driver 204 is electrically connected to the controller 203, and is used to drive the conduction or turn-off of the switch tube in each phase boost branch in the boost circuit 202 according to the PWM signal output by the controller 203.

[0059] The control principle of the voltage boosting circuit 202 is as follows: when the AC power input is in the positive half cycle, when the switch tube Q1 is off and the switch tube Q2 is on, the controller 203 outputs a low-level PWM1 signal and a high-level PWM2 signal to the driver 204, respectively, the driver 204 amplifies the low-level PWM1 signal and the high-level PWM2 signal, and then outputs them to the control electrode of the switch tube Q3 and the control electrode of the switch tube Q4 in the voltage boosting branch 1, respectively, to control the switch tube Q3 to be off and the switch tube Q4 to be on, at this time the inductor L1 is charged. Then after a time t1, the controller 203 outputs a high-level PWM1 signal and a low-level PWM2 signal, the driver 204 amplifies the high-level PWM1 signal and the low-level PWM2 signal, and then outputs them to the control electrode of the switch tube Q3 and the control electrode of the switch tube Q4, respectively, to control the switch tube Q3 to be on and the switch tube Q4 to be off in the voltage boosting branch 1, at this time the inductor L1 is discharged. After a time t2, when the inductor L1 is discharged, the controller 203 can sample the current of the inductor L1 to be 0.

[0060] When the AC power input is in the negative half cycle, when the switch tube Q1 is on and the switch tube Q2 is off, the controller 203 outputs a high-level PWM2 signal and a low-level PWM1 signal to the driver 204, respectively, the driver 204 amplifies the high-level PWM2 signal and the low-level PWM1 signal, and then outputs them to the control electrode of the switch tube Q3 and the control electrode of the switch tube Q4 in the voltage boosting branch 1, respectively, to control the switch tube Q3 to be on and the switch tube Q4 to be off, at this time the inductor L1 is charged. Then after a time t3, the controller 203 outputs a low-level PWM2 signal and a high-level PWM1 signal, the driver 204 amplifies the low-level PWM2 signal and the high-level PWM1 signal, and then outputs them to the control electrode of the switch tube Q3 and the control electrode of the switch tube Q4, respectively, to control the switch tube Q3 to be off and the switch tube Q4 to be on in the voltage boosting branch 1, at this time the inductor L1 is discharged. After a time t4, when the inductor L1 is discharged, the controller 203 can sample the current of the inductor L1 to be 0.

[0061] The control principle of the voltage boosting branch 2 is similar, which will not be described here.

[0062] In the working process of the PFC circuit shown in Figure 1 and Figure 2 , the N-phase voltage boosting branch works in the interleaved state. For example, as shown in Figure 3 , the waveform diagram of a PFC circuit is shown in Figure 3 . For Figure 1The PFC circuit shown, the controller 103 outputs a high level PWM1 signal, so that the driver 104 drives the switch Q1 in the boost branch 1 on, inductor L1 charging. In the process of inductor L1 charging, the controller 103 outputs a low level PWM2 signal, so that the driver 104 drives the switch Q2 in the boost branch 2 off, inductor L2 discharge. Alternatively, the controller 103 outputs a low level PWM1 signal, so that the driver 104 drives the switch Q1 in the boost branch 1 off, inductor L1 discharge. In the process of inductor L1 discharge, the controller 103 outputs a high level PWM2 signal, so that the driver 104 drives the switch Q2 in the boost branch 2 on, inductor L2 charging.

[0063] Throughout the process, the high and low levels of PWM1 signal and PWM2 signal are staggered, and the phase difference between PWM1 signal and PWM2 signal can be 180. If the boost circuit 102 includes N-phase boost branches, the phase difference between adjacent two-phase boost branches can be 360 / N. Wherein, N is an integer greater than or equal to 2. And, the charging and discharging of inductor L1 and inductor L2 are also staggered, that is, in the process of inductor L1 charging in the boost branch 1, inductor L2 discharges in the boost branch 2, in the process of inductor L1 charging in the boost branch 1, inductor L2 discharges in the boost branch 2. The boost branch 1 and the boost branch 2 work in the interleaved state.

[0064] For Figure 2 The PFC circuit shown, if the AC power input is in the positive half cycle, the conduction or turn-off of switch Q4 is controlled by PWM1 signal, and the conduction or turn-off of switch Q6 is controlled by PWM2 signal. The high and low levels of PWM1 signal and PWM2 signal are staggered, and the phase difference between PWM1 signal and PWM2 signal is 180. If the AC power input is in the negative half cycle, the conduction or turn-off of switch Q3 is controlled by PWM1 signal, and the conduction or turn-off of switch Q5 is controlled by PWM2 signal, the high and low levels of PWM1 signal and PWM2 signal are staggered, and the phase difference between PWM1 signal and PWM2 signal is 180. The AC power input is in the positive half cycle or the negative half cycle, the waveform diagram of PWM1 signal and PWM2 signal is as shown in Figure 3 Similarly, it is not described here.

[0065] Wherein, the period T1 of PWM1 signal of boost branch 1 is from the start time of inductor L1 charging to the end time of inductor L1 discharging. The period T2 of PWM2 signal of boost branch 2 is from the start time of inductor L2 charging to the end time of inductor L2 discharging. That is, the zero-crossing time of the current of the inductor in each phase boost branch can be obtained, and the period of the PWM signal of each phase boost branch is determined according to the zero-crossing time of the current of the inductor.

[0066] However, due to differences in components within each phase's boost branch—for example, differences in inductor inductance, drive delays, or sampling delays in the inductor's current—the periods of the PWM signals for the N-phase boost branches vary. This prevents the high and low levels of the PWM signals from interleaving, preventing the N-phase boost branches from operating in an interleaved state. Existing control schemes perform phase compensation without interleaving the boost branches. This results in the boost branches consistently operating between non-interleaving and interleaving, without pre-compensation, and prevents the PFC circuit from operating stably in an interleaved state.

[0067] For example, Figure 4 As shown, the period of the PWM1 signal in boost branch 1 is T1, and the period of the PWM2 signal in boost branch 2 is T2. Within a period, the high level of the PWM1 signal and the high level of the PWM2 signal should be maintained for the same duration, which means that the charging duration of the inductor L1 in boost branch 1 and the inductor L2 in boost branch 2 are the same. However, due to differences in the components in boost branch 1 and boost branch 2, the discharge duration of the inductor L1 in boost branch 1 and the inductor L2 in boost branch 2 are different. This results in different maintenance durations of the low level of the PWM1 signal and the low level of the PWM2 signal, resulting in the period T1 of the PWM1 signal in boost branch 1 and the period T2 of the PWM2 signal in boost branch 2 being different. As a result, after a period of time, the high and low levels of the PWM1 and PWM2 signals become non-interlaced, preventing boost branch 1 and boost branch 2 from operating in an interlaced state, resulting in increased ripple current output by the PFC circuit.

[0068] In order to solve the above technical problems, the embodiments of the present application provide the following solutions.

[0069] like Figure 5 As shown, Figure 5 1 is a flow chart of a phase compensation method provided in an embodiment of the present application. The method is applied to a PFC circuit, which includes N-phase boost branches connected in parallel. Figure 1 The phase compensation method is described using the PFC in the embodiment as an example. The method can be executed by a controller in the PFC circuit. The steps in the embodiment of the present application mainly include:

[0070] S501, output a first level signal for the switch tube Q1 in the first boost branch and a second level signal for the switch tube Q2 in the second boost branch, wherein the first level signal and the second level signal are control signals with the same maintenance duration and the same level.

[0071] For example, the first level signal and the second level signal can be high level signals with the same maintaining time length, when the switch Q1 and the switch Q2 in the PFC circuit are NMOS transistors. It can be understood that, when the switch Q1 and the switch Q2 in the PFC circuit are PMOS transistors, the first level signal and the second level signal can be low level signals with the same maintaining time length.

[0072] The phase compensation process can include two stages. The first stage is a measurement stage. Before the PFC circuit works normally, the controller outputs the first level signal and the second level signal with the same maintaining time length, obtains the first period of the first boost branch and the second period of the second boost branch, and determines the compensation value according to the first period of the first boost branch and the second period of the second boost branch. The second stage is a compensation stage. After the PFC circuit works normally, the controller outputs the second PWM signal for the second boost branch, and compensates the maintaining time length of the level signal for turning on the control switch in the second PWM signal based on the compensation value. For example, for the NMOS switch, the high level signal in the second PWM signal is compensated.

[0073] In the first stage, the controller can output the first level signal for the first boost branch and the second level signal for the second boost branch at the same time. The first level signal for the first boost branch and the second level signal for the second boost branch can also be output at different times.

[0074] The first boost branch is any one of the N-phase boost branches, and the second boost branch can be any one of the other boost branches except the first boost branch in the N-phase boost branches.

[0075] S502, obtaining the first period of the first PWM signal of the switch Q1 and the second period of the second PWM signal of the switch Q2.

[0076] Specifically, the first boost branch includes a first switch, and the second boost branch includes a second switch. The control end of the first switch and the control end of the second switch are respectively electrically connected to two control ends of the controller. The controller 103 can output the first level signal to the control end of the first switch, and output the second level signal to the control end of the second switch. The controller 103 can obtain the first period of the first pulse width modulation signal of the first switch based on the first level signal, and obtain the second period of the second pulse width modulation signal of the second switch based on the second level signal.

[0077] In the working process of the PFC circuit, the controller 103 outputs a high level for the first boost branch. Initially, the current of the inductor L1 in the first boost branch is 0, and the inductor L1 starts to charge. After a maintaining time t1, the output for the first boost branch is switched to a low level, and the inductor L1 in the first boost branch discharges. After a maintaining time t2, the inductor L1 in the first boost branch completes discharging, and the current of the inductor L1 in the first boost branch is 0. The complete process of charging and discharging of the inductor L1 in the first boost branch can be regarded as a period of the first PWM signal. The control principle of the second boost branch is similar, and will not be described herein.

[0078] In one period of compensation, the first PWM signal includes not only the first level signal, but also a third level signal (for example, a low level) after the first level signal. The second PWM signal includes not only the second level signal, but also a fourth level signal (for example, a low level) after the second level signal. The maintaining time of the first level signal and the second level signal can be set by the controller. The maintaining time of the third level signal is determined according to the discharging time of the inductor L1 in the first boost branch, and the maintaining time of the fourth level signal is determined according to the discharging time of the inductor L2 in the second boost branch. Due to the difference of the devices in the first boost branch and the second boost branch, the discharging time of the inductor L1 in the first boost branch and the discharging time of the inductor L2 in the second boost branch can be different, so that the maintaining time of the third level signal and the maintaining time of the fourth level signal are also different.

[0079] Further, the current of the inductor L1 in the first boost branch can be sampled to obtain the zero-crossing time of the current of the inductor L1 in the first boost branch, and the first period of the first PWM signal is determined according to the zero-crossing time of the current of the inductor L1. The zero-crossing time of the current of the inductor L1 in the first boost branch includes the starting time of charging of the inductor L1 in the first boost branch and the ending time of discharging of the inductor L1 in the first boost branch. Further, the first period of the first PWM signal can be determined according to the starting time of charging of the inductor L1 in the first boost branch and the ending time of discharging of the inductor L1 in the first boost branch. That is, the first period of the first PWM signal is from the starting time of charging of the inductor L1 in the first boost branch to the ending time of discharging of the inductor L1 in the first boost branch.

[0080] The current of the inductor L2 in the second voltage boosting branch can be sampled to obtain a zero-crossing time of the current of the inductor L2 in the second voltage boosting branch, and the second period of the second PWM signal is determined according to the zero-crossing time of the current of the inductor L2. The zero-crossing time of the current of the inductor L2 in the second voltage boosting branch includes a start time of charging of the inductor L2 in the second voltage boosting branch and an end time of discharging of the inductor L2 in the second voltage boosting branch. Further, the second period of the second PWM signal can be determined according to the start time of charging of the inductor L2 in the second voltage boosting branch and the end time of discharging of the inductor L2 in the second voltage boosting branch. That is, the second period of the second PWM signal is from the end time of charging of the inductor L2 in the second voltage boosting branch to the end time of discharging of the inductor L2 in the second voltage boosting branch.

[0081] S503, determining a first difference between the first period and the second period.

[0082] S504, determining whether the first difference between the first period and the second period exceeds a preset threshold. If the first difference between the first period and the second period does not exceed the preset threshold, the process ends at this step, and if the first difference between the first period and the second period exceeds the preset threshold, S505 is performed.

[0083] S505, compensating for a maintaining time length of the on control level in the second PWM signal according to the first difference.

[0084] It can be understood that for an N-type MOS tube, in the PWM signal, the on control level is high, and the high level signal is compensated according to the first difference.

[0085] Specifically, the difference value can be multiplied by a compensation coefficient to calculate a first compensation value, and then the maintaining time length of the high level is added or subtracted by the first compensation value to obtain the maintaining time length of the high level after compensation. For example, the first period is T1, the second period is T2, and the difference between the first period and the second period is Err=T2-T1. The compensation value M=μ*Err, wherein μ is a compensation coefficient, and the compensation coefficient can be determined according to an input voltage Vin of the voltage boosting circuit and an output voltage Vout provided by the voltage boosting circuit.

[0086] The compensation for the maintaining time length of the high level includes reducing the maintaining time length of the high level or increasing the maintaining time length of the high level. In the case where the second period is greater than the first period, the maintaining time length of the high level is subtracted by the first compensation value to obtain the maintaining time length of the high level after compensation, and in the case where the second period is less than the first period, the maintaining time length of the high level is added by the first compensation value to obtain the maintaining time length of the high level after compensation.

[0087] Optionally, after the PFC circuit is normally working, the controller can compensate the maintaining time length of the high level in the second PWM signal according to the first compensation value. After compensating the maintaining time length of the high level in the first period of the second PWM signal, the maintaining time length of the high level in each subsequent period of the second PWM signal can be compensated. Thus, the second period of the subsequent second PWM signal is always close to or equal to the first period of the second PWM signal of the first boost branch.

[0088] It can be understood that for the P-type MOS tube, in the PWM signal, the turn-on control level is low, and the low level signal is compensated according to the first difference.

[0089] Please refer to Figure 4 , Figure 4 The PWM1 signal and the PWM2 signal of three periods are shown, the period of the PWM1 signal is T1, and the period of the PWM2 signal is T2. In the first two periods, the high level and the low level of the PWM1 signal and the PWM2 signal are staggered. However, because the period T1 of the PWM1 signal is not the same as the period of the PWM2 signal, in the third period, the high level and the low level of the PWM1 signal and the PWM2 signal are not staggered. As shown in Figure 6 , Figure 6 is a schematic diagram of phase compensation provided by an embodiment of the present application. Based on the period T1 of the PWM1 signal and the period T2 of the PWM2 signal, the maintaining time length of the high level of the PWM2 signal is compensated according to the compensation value M, the maintaining time length of the high level of the PWM2 signal in each period is reduced, and the period of the PWM2 signal in each period is adjusted to T3, so that the period T3 of the PWM2 signal is within a certain range of the difference of the period T1 of the PWM1 signal.

[0090] When the PFC circuit is formally working, the controller compensates the maintaining time length of the high level in the second PWM signal, outputs the control signal for the second boost branch according to the maintaining time length of the high level after compensation, changes the charging time length of the inductor L2 in the second boost branch, changes the discharging time length of the inductor L2 in the second boost branch, and then adjusts the second period of the second PWM signal of the second boost branch. The second period of the second PWM signal of the second boost branch is close to or equal to the first period of the second PWM signal of the first boost branch.

[0091] For the PFC circuit shown in Figure 1 , the second period of the second PWM signal of the second boost branch is adjusted according to the above method based on the period of the PWM signal of the first boost branch, that is, the turn-on time length of the switch tube Q1 in Figure 1 is taken as the reference to adjust the turn-on time length of the switch tube Q2.

[0092] For Figure 2 As shown in the PFC circuit, in the positive half cycle of the AC power input, the period of the PWM signal of the first boost branch switch tube is taken as the reference, and the period of the PWM signal of the corresponding position switch tube of the second boost branch is adjusted according to the above method, that is, the length of the conduction of the switch tube Q6 (the second switch tube) is adjusted based on the length of the conduction of the switch tube Q4 (the first switch tube). Figure 2 In the negative half cycle of the AC power input, the period of the PWM signal of the first boost branch switch tube is taken as the reference, and the period of the PWM signal of the corresponding position switch tube of the second boost branch is adjusted according to the above method, that is, the length of the conduction of the switch tube Q5 (the fourth switch tube) is adjusted based on the length of the conduction of the switch tube Q3 (the third switch tube). Figure 2

[0093] It can be understood that the control signal PWM1 of the switch tube Q4 in the positive half cycle of the AC power input and the control signal PWM3 of the switch tube Q3 in the negative half cycle of the AC power input can be the same signal; the control signal PWM2 of the switch tube Q6 in the positive half cycle of the AC power input and the control signal PWM4 of the switch tube Q5 in the negative half cycle of the AC power input can be the same signal.

[0094] Based on this, in an implementable manner, in the positive half cycle of the AC power input, a first compensation value can be determined, and the high level signal of PWM2 for controlling the switch tube Q6 (the second switch tube) is compensated by using the compensation value. In the negative half cycle of the AC voltage input, the same compensation value is used to compensate the length of time for maintaining the high level in the fourth PWM signal for controlling the switch tube Q5 (the fourth switch tube). By using this compensation method, for the corresponding two groups of switch tubes in the two-phase boost branch, the compensation value needs to be calculated only once, thereby reducing the number of compensation calculations and improving the compensation efficiency.

[0095] ​In one feasible manner, in the positive half cycle of the AC power input, the first cycle of the first pulse width modulation signal PWM1 of the switch tube Q4 (the first switch tube) and the second cycle of the second pulse width modulation signal PWM2 of the switch tube Q6 (the second switch tube) are obtained; wherein, the first pulse width modulation signal PWM1 is used to control the working state of the switch tube Q4 (the first switch tube), and the second pulse width modulation signal PWM2 is used to control the working state of the switch tube Q6 (the second switch tube); a first difference between the first cycle and the second cycle is determined; and based on the first difference, the maintenance time of the high level in the second pulse width modulation signal PWM2 is adjusted. During the negative half-cycle of the AC power input, a third cycle of the third pulse width modulation signal PWM3 for the switch Q3 (the third switch) and a fourth cycle of the fourth pulse width modulation signal PWM4 for the switch Q5 (the fourth switch) can be obtained. The third pulse width modulation signal PWM3 is used to control the operating state of the switch Q3 (the third switch), and the fourth pulse width modulation signal PWM4 is used to control the operating state of the switch Q5 (the fourth switch). A second difference between the third cycle and the fourth cycle is determined; based on the second difference, the duration of the high level in the fourth pulse width modulation signal PWM4 is adjusted. By adjusting the compensation values ​​of the two groups of switches during the positive and negative half-cycles of the AC input, specifically adjusting the duration of the high level in the second pulse width modulation signal of the second switch during the positive half-cycle of the AC power input and adjusting the duration of the high level in the fourth pulse width modulation signal of the fourth switch during the negative half-cycle of the AC power input, the accuracy of the compensation is improved.

[0096] In an embodiment of the present application, by applying initial control signals of the same level with the same maintenance time to the switching tubes in the N-phase boost branches, the period of the PWM signal of the switching tube in each phase boost branch is obtained, and the period of the PWM signal of one phase boost branch is used as a reference, the conduction control level in the PWM signal of the other phase boost branches is compensated in advance, that is, the phase of the PWM signal is compensated, so that the period of the PWM signal of the other phase boost branches is the same as the period of the PWM signal of the boost branch serving as the reference. In this way, the high level and low level of the PWM signal of each phase boost branch are staggered, so that the N-phase boost branch operates in a staggered state, thereby reducing the ripple current in the PFC output.

[0097] like Figure 7 As shown, Figure 7 The present invention provides a schematic diagram of a computing device. The computing device may be an electronic device such as a server, a switch, or a computer. The computing device includes a switching power supply. The switching power supply may include Figure 1 or Figure 2The controller in any of the PFC circuits shown can be configured to perform the above-described Figure 5 The phase compensation method shown.

[0098] The computing device can further include a processor, a memory and a transceiver. Wherein the processor, the memory, the transceiver and the switching power supply can communicate with each other through internal connection paths to transfer control and / or data signals, the memory is used to store a computer program, the processor is used to call and run the computer program from the memory to control the transceiver to transceive signals. The processor is configured to execute the program code stored in the memory to implement the above-described functions. In specific implementation, the memory can be integrated in the processor or independent of the processor. The above-described transceiver can also be referred to as a transceiving unit or a transceiving module. The transceiver can include a receiver (or receiver, receiver circuit) and a transmitter (or transmitter, transmitter circuit). Wherein the receiver is used to receive signals, and the transmitter is used to transmit signals. The transceiver is configured to communicate with other devices.

[0099] It should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the above-mentioned embodiments of the present application have been described in detail, those skilled in the art should understand that: it can still modify the technical solutions recorded in the above-mentioned embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A power factor correction (PFC) circuit, characterized in that, the PFC circuit comprises a first boost branch, a second boost branch and a controller; the first boost branch comprises a first switch tube; the second boost branch comprises a second switch tube; a control end of the first switch tube and a control end of the second switch tube are electrically connected to two control ends of the controller respectively; the controller is configured to: obtain a first period of a first pulse width modulation (PWM) signal of the first switch tube and a second period of a second PWM signal of the second switch tube; the first PWM signal is used to control a working state of the first switch tube, and the second PWM signal is used to control a working state of the second switch tube; determine a first difference between the first period and the second period; based on the first difference, adjust a maintaining duration of a turn-on control level in the second PWM signal, wherein the turn-on control level is a level signal used to control the second switch tube to turn on.

2. The PFC circuit of claim 1, wherein, The controller is configured to adjust the maintaining duration of the first level in the second PWM signal based on the first difference, including: the controller is configured to: multiply the first difference by a first compensation coefficient to obtain a first compensation value; wherein the first compensation coefficient is determined based on an alternating current (AC) input voltage and an output voltage of the PFC; add or subtract the first compensation value to the maintaining duration of the turn-on control level in the second PWM signal.

3. The PFC circuit of claim 1 or 2, wherein The controller is configured to obtain a first period of a first pulse width modulation (PWM) signal of the first switch tube and a second period of a second PWM signal of the second switch tube, including: the controller is configured to: output a first level signal to a control end of the first switch tube; output a second level signal to a control end of the second switch tube; obtain a first period of a first pulse width modulation (PWM) signal of the first switch tube based on the first level signal, and obtain a second period of a second PWM signal of the second switch tube based on the second level signal; wherein the first level signal and the second level signal are turn-on level signals with the same maintaining duration.

4. The PFC circuit of claim 3, wherein, The controller is configured to obtain a first period of a first pulse width modulation (PWM) signal based on the first level signal, and obtain a second period of a second PWM signal based on the second level signal; including: the controller is configured to: obtain a current of the first inductor based on the first level signal, and determine the first period of the first PWM signal according to a zero-crossing time of the current of the first inductor; and obtain a current of the second inductor based on the second level signal, and determine the second period of the second PWM signal according to a zero-crossing time of the current of the second inductor.

5. The PFC circuit of any one of claims 1-2, wherein, The first boost branch further comprises a first inductor and a first diode; a first end of the first inductor is electrically connected to a positive pole of a direct current power supply; a first end of the first switch tube, a second end of the first inductor and an anode of the first diode are electrically connected; a cathode of the first diode is electrically connected to a first end of a load; a second end of the first switch tube, a negative pole of the direct current power supply and a second end of the load are electrically connected; a control end of the first switch tube is electrically connected to a first control signal output end of the controller; The second boost branch further comprises a second inductor and a second diode; a first end of the second inductor is electrically connected to the positive pole of the direct current power supply; a first end of the second switch tube, a second end of the second inductor and an anode of the second diode are electrically connected; a cathode of the second diode is electrically connected to the first end of the load; a second end of the second switch tube, the negative pole of the direct current power supply and the second end of the load are electrically connected; a control end of the second switch tube is electrically connected to a second control signal output end of the controller.

6. The PFC circuit of any one of claims 1-2, wherein, The first boost branch further comprises a first inductor and a third switch tube; a first end of the first inductor is electrically connected to a positive pole of an alternating current power supply; a first end of the first switch tube, a second end of the first inductor and a second end of the third switch tube are electrically connected; a first end of the third switch tube is electrically connected to the first end of the load; a second end of the first switch tube, a negative pole of the alternating current power supply and a second end of the load are electrically connected; a third end of the first switch tube is electrically connected to the first control signal output end of the controller; a third end of the third switch tube is electrically connected to a third control signal output end of the controller; The second boost branch further comprises a second inductor and a fourth switch tube; a first end of the second inductor is electrically connected to the positive pole of the alternating current power supply; a first end of the second switch tube, a second end of the second inductor and a second end of the fourth switch tube are electrically connected; a first end of the fourth switch tube is electrically connected to the first end of the load; a second end of the second switch tube, the negative pole of the alternating current power supply and the second end of the load are electrically connected; a control end of the second switch tube is electrically connected to the second control signal output end of the controller; a control end of the fourth switch tube is electrically connected to a fourth control signal output end of the controller; The controller is further configured to: acquire a fourth period of a fourth pulse width modulation signal of the fourth switch tube, wherein the fourth pulse width modulation signal is used to control an operating state of the fourth switch tube; Based on the first difference, adjust a maintaining duration of a conduction control level in the fourth pulse width modulation signal.

7. The PFC circuit of claim 6, wherein, The controller is configured to: when the alternating current power supply input is in a positive half cycle, based on the first difference, adjust a maintaining duration of a high level in the second pulse width modulation signal; and / or when the alternating current power supply input is in a negative half cycle, based on the first difference, adjust a maintaining duration of a conduction control level in the fourth pulse width modulation signal. The controller is further configured to:

8. The PFC circuit of any of claims 1-2, wherein, determine whether the first difference exceeds a preset threshold value; ​ If the first difference exceeds the preset threshold, a maintaining time length of a high level in the second pulse width modulation signal is adjusted based on the first difference.

9. The PFC circuit of any of claims 1-2, wherein, The PFC circuit includes a plurality of second boost branches.

10. The PFC circuit of any one of claims 1-2, wherein, The on control level is a high level.

11. A switching power supply, characterized by comprising: The switching power supply includes the PFC circuit according to any one of claims 1-10.

12. A computing device, comprising: The computing device includes the switching power supply according to claim 11.

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