A Phase-Locked Loop Spurious Optimization Method

Abstract

The present invention proposes a phase-locked loop spurious optimization method, comprising the following steps: S1, assuming the input frequency of the DDS chip is fi, and determining the current input frequency f according to the required output frequency range. i The integer division ratio range and the division frequency corresponding to each integer division ratio; S2, calculate the difference between adjacent division frequencies, compare the difference with the threshold a, and record the input frequency f that DDS can use i Output frequency range; S3, when the input frequency is f1, according to the threshold a' required by the user, the frequency range with larger spurious is (F 1i ‑a')~(F 1i +a'), so this frequency range uses other input frequencies for output, ultimately obtaining all input frequencies and corresponding frequency division ratios that can cover the required output frequency range. S4 and the DDS chip obtain the optimized output frequency segment based on the input frequency obtained by S3, and the output frequency segment serves as the reference input frequency of the phase-locked loop. This invention can greatly reduce the problem of integer frequency division spurious and is simple and effective.

Description

Technical Field

[0001] The present invention relates to the technical field of frequency synthesis, and in particular to a phase-locked loop spurious optimization method. Background Art

[0002] Spurious emissions are a core specification for measuring instruments, especially signal generators. Current spurious emissions in both domestic and international signal generators are steadily increasing, from -70dBc in previous generations to below -80dBc today. Generally, low- and mid-range signal generators, due to their lower phase noise requirements, can meet these requirements using a single phase-locked loop (PLL). However, while a single PLL structure effectively suppresses far-end spurious emissions due to its inherent characteristics, it theoretically has no effect on near-end spurious emissions. Therefore, the spurious emission level of the PLL reference signal represents the overall spurious emission level. In high-end signal generators, multiple PLLs are often used because a single PLL structure cannot meet the required phase noise specifications. However, due to the multiple reference frequencies of multiple PLLs, the intermodulation signals they generate also vary in frequency. Once the intermodulation signal approaches the PLL reference signal, the PLL's inherent characteristics cannot suppress near-end spurious emissions. Consequently, the intermodulation signals generated by multiple loops inevitably become spurious emissions in the signal generator and are difficult to suppress.

[0003] Currently, spurious suppression technologies have been extensively researched both domestically and internationally, and can be broadly categorized. One approach utilizes multiple phase-locked loops (PLLs) to avoid frequencies where spurious signals are present; the other approach involves directly optimizing the PLL reference spurious signal. The multi-PLL approach, however, remains under intense research due to its complex principles and the high complexity of its hardware circuits and software algorithms. Direct optimization of the PLL reference spurious signal is relatively simple, typically employing fractional frequency division chips or DDS chips to optimize spurious signals, but this approach places high demands on the chips. Currently, these two types of chips are still in the design phase in China and have yet to be verified and standardized. While international manufacturers like ADI and TI have mature designs for these chips and have already produced models, their broadband spurious signals, such as the AD9914ABCPZ, are generally around -80dBc, which is increasingly insufficient for signal generators with increasingly stringent spurious signal requirements. Therefore, this paper utilizes existing DDS chips to design a method for reducing spurious signals in the DDS output signal, thereby optimizing the near-end spurious signals of the PLL. Summary of the Invention

[0004] To solve the above problems, the present invention provides a phase-locked loop spurious optimization method, which has a reasonable design, solves the shortcomings of the existing technology, and has good effects.

[0005] In order to achieve the purpose of the invention, the following technical solutions are adopted:

[0006] A phase-locked loop spurious optimization method comprises the following steps:

[0007] S1. Assume the input frequency of the DDS chip is f i , 1 <i≤k,f i and f i+1 The difference between them is a fixed value; according to the required output frequency range, determine the current input frequency f i The integer division ratio range is (N1,N n ), thus obtaining (N1,N n ) corresponds to the frequency division frequency F of each integer point between ij , 1 <j<n;

[0008] S2. Calculate the difference between adjacent frequency divisions, set a threshold a according to user requirements, compare the difference with a, and record the input frequency f that DDS can use. i Output frequency range;

[0009] S3, when the input frequency is f1, according to the threshold a' required by the user, the frequency range with larger spurious is (F 1i -a')~(F 1i +a'), these frequency ranges are output using other input frequencies, and ultimately all input frequencies and corresponding division ratios that can cover the required output frequency range are obtained;

[0010] S4 and the DDS chip obtain the input frequency through S3, avoid the integer frequency division boundary spurs, and obtain the optimized output frequency segment, which is used as the reference input frequency of the phase-locked loop.

[0011] Furthermore, in said S2, the following are calculated respectively at different input frequencies f i Next, the adjacent crossover frequency F ij and F i(j+1) The difference between the two values ​​is set according to the user's requirements. If the difference is less than a, the output frequency range F ij ~F i(j+1) The current starting frequency f cannot be used i As the input frequency of DDS; if the difference is greater than a, the output frequency range F ij ~F i(j+1) Able to use the current starting frequency f i As the input frequency of DDS, it is recorded as array {f i ,j,j+1,F ij ,F i(j+1 )}, k input frequencies get a total of (m1+…+m k ) arrays.

[0012] Furthermore, in said S3, when the input frequency is fk When the frequency range with larger spurious is (F ki -a')~(F ki +a'), if (F 1i -a')~(F 1i +a') and (F ki -a')~(F ki +a') has an intersection area, then judge (F ki +a')-(F 1i +a') is greater than the threshold a', if it is greater than a', then the input frequency f is used k Used to output (F 1i -a')~(F 1i +a'), and finally all input frequencies that can cover the required output frequency range and the corresponding frequency division ratios are obtained.

[0013] Furthermore, in said S1, the input frequency f of said DDS chip k Less than or equal to the maximum design value of the DDS chip.

[0014] The present invention has the following beneficial effects:

[0015] The present invention proposes a phase-locked loop spurious optimization method, which determines multiple input frequencies through an offline pre-calculation method, thereby greatly reducing integer frequency division spurious problems. The method is simple and effective, and has low circuit complexity and software algorithm complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Flowchart of the phase-locked loop spurious optimization method of the present invention; DETAILED DESCRIPTION

[0017] The specific implementation of the present invention will be further described below with reference to specific embodiments:

[0018] A phase-locked loop spurious optimization method, such as Figure 1 As shown, the following steps are included:

[0019] S1. Assume the input frequency of the DDS chip is f i , 1 <i≤k,f i and f i+1 The difference between them is a fixed value. According to the required output frequency range, the current input frequency f is determined. i The integer division ratio range is (N1,N n ), thus obtaining (N1,N n ) corresponds to the frequency division frequency F of each integer point between ij , 1 <j<n;

[0020] In this embodiment, the DDS chip is AD9914ABCPZ. Taking the initial input frequency f1 = 3000 MHz as an example, according to the output frequency range of 100 to 150 MHz, the integer division ratio range is (20, 30), so the division frequencies corresponding to each integer point between (20, 30) are [100 Hz, 103.4 Hz, ..., 142.8 MHz, 150 MHz].

[0021] S2, respectively calculate at different input frequencies f i Next, the adjacent crossover frequency F ij and F i(j+1) The difference between the two values ​​is set according to the user's requirements. If the difference is less than a, the output frequency range F ij ~F i(j+1) The current starting frequency f cannot be used i As the input frequency of DDS; if the difference is greater than a, the output frequency range F ij ~F i(j+1) The current starting frequency f can be used i As the input frequency of DDS, it is recorded as array {f i ,j,j+1,F ij ,F i(j+1)}, k input frequencies are obtained in total (m1+…+m k ) arrays;

[0022] The threshold a can be selected based on actual needs. For example, if the DDS integer boundary output spurious value is -65dBc within 1MHz, and the required spurious value is better than -65dBc, then the threshold can be set to 1. If the required spurious value is -70dBc, and the DDS boundary spurious value is greater than 3MHz to achieve the desired effect, then the threshold can be set to 3, and so on.

[0023] Taking the adjacent divided frequencies 142.8MHz and 150MHz as an example, the difference is 7.2. Set a threshold a = 2. Since 7.2>2, the output frequency range of 142.8~150MHz can use 3000hz as the input frequency of the DDS chip, which is recorded as the array {3000,20,21,142.8,150}. And so on to get m1 arrays;

[0024] S3, when the input frequency is f1, according to the threshold a' required by the user, the frequency range with larger spurious is (F 1i -a')~(F 1i +a'), so these frequency ranges use other input frequencies for output; when the input frequency is f s When the frequency range with larger spurious is (F si -a')~(Fsi +a'), if (F 1i -a')~(F 1i +a') and (F si -a')~(F si +a') has an intersection area, then judge (F si +a')-(F 1i +a') is greater than the threshold a', if it is greater than a', then the input frequency f is used s Used to output (F 1i -a')~(F 1i +a'), and finally obtain all input frequencies and corresponding frequency division ratios that can cover the required output frequency range;

[0025] Taking the case of a frequency division ratio of 20, the input frequency is 3000MHz, a'=2, and the frequency range with larger spurious signals is (150-2) to (150+2)MHz, i.e., 148 to 152MHz. Therefore, when outputting 142.8 to 150MHz, 3000MHz is only responsible for outputting 142.8 to 148MHz, and 148 to 150MHz is output using other input frequencies.

[0026] When the input frequency is 3060MHz, its integer division ratio is (20, 30). When the division ratio is 20, the frequency range with larger spurious signals is (153-2)~(153+2)MHz, that is, 151~155MHz. There is an intersection area between 148~152MHz and 151~155MHz, and the size of (155-152)=3 is greater than 2. Therefore, the input frequency of 3060MHz is used to output 148~151MHz, that is, 148~150MHz.

[0027] S4 and the DDS chip obtain the input frequency through S3, avoid the integer frequency division boundary spurs, and obtain the optimized output frequency segment. The output frequency segment is used as the reference input frequency of the phase-locked loop, thereby optimizing the phase-locked loop near-end spurs.

[0028] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the scope of protection of the present invention.

Claims

1. A phase-locked loop spurious optimization method, characterized in that: The following steps are involved: S1. Assume the input frequency of the DDS chip is f i , 1 <i≤k,f i and f i+1 The difference between them is a fixed value; according to the required output frequency range, determine the current input frequency f i The integer division ratio range is (N1, Nn), so (N1, N n ) corresponds to the frequency division frequency F of each integer point between ij , 1 <j<n; S2. Calculate the difference between adjacent frequency divisions, set a threshold a according to user requirements, compare the difference with a, and record the input frequency f that DDS can use. i Output frequency range; S3, when the input frequency is f1, according to the threshold a' required by the user, the frequency range with larger spurious is (F 1i -a)~(F 1i +a), these frequency ranges are output using other input frequencies, ultimately obtaining all input frequencies and corresponding frequency division ratios that can cover the required output frequency range; S4 and the DDS chip obtain the input frequency through S3, avoid the integer frequency division boundary spurs, and obtain the optimized output frequency segment, which is used as the reference input frequency of the phase-locked loop.

2. A phase-locked loop spurious optimization method according to claim 1, characterized in that: In S2, the input frequencies f are calculated respectively. i Next, the adjacent crossover frequency F ij and F i(j+1) The difference between the two values ​​is set according to the user's requirements. If the difference is less than a, the output frequency range F ij ~F i(j+1) The current starting frequency f cannot be used i As the input frequency of DDS; if the difference is greater than a, the output frequency range F ij ~F i(j+1) Able to use the current starting frequency f i As the input frequency of DDS, it is recorded as array {f i ,j,j+1,F ij ,F i(j+1 )}, k input frequencies get a total of (m1+…+m k ) arrays.

3. The phase-locked loop spurious optimization method according to claim 1, characterized in that: In S3, when the input frequency is f k When the frequency range with larger spurious is (F ki -a')~(F ki +a'), if (F 1i -a')~(F 1i +a') and (F ki -a')~(F ki +a') has an intersection area, then judge (F ki +a')-(F 1i +a') is greater than the threshold a', if it is greater than a', then the input frequency f is used k Used to output (F 1i -a')~(F 1i +a'), and finally all input frequencies that can cover the required output frequency range and the corresponding frequency division ratios are obtained.

4. The method for optimizing phase-locked loop spurious emission according to claim 1, wherein: In the S1, the input frequency f of the DDS chip k Less than or equal to the maximum design value of the DDS chip.

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