Display panels and spliced ​​display screens

Abstract

The present application discloses a display panel and a spliced ​​display screen. The display panel includes a first circuit, a fan-out line and a second circuit. By electrically connecting the first electrode of each transistor in the first subcircuit and a data line respectively, and electrically connecting the second electrode of each transistor in the same second subcircuit and the other end of a fan-out line respectively, a transistor in the first subcircuit and a transistor in the second subcircuit are synchronously turned on or off, so that the first subcircuit and the second subcircuit can share the same fan-out line, thereby reducing the number of fan-out lines used.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a spliced ​​display screen. Background Art

[0002] The display panel includes a display area and a frame area. With the development of display technology, the space occupied by the frame area is getting smaller and smaller. However, there are still a large number of fan-out lines in the frame area, making it difficult to compress the space occupied by the frame area. Summary of the invention

[0003] The present application provides a display panel and a spliced ​​display screen to alleviate the technical problem of an excessive number of fan-out lines in a frame area.

[0004] In a first aspect, the present application provides a display panel, which includes a first circuit, a fan-out line and a second circuit, the first circuit includes one or more first sub-circuits, the first sub-circuit includes N transistors, the first pole of each transistor in the first sub-circuit is respectively electrically connected to a data line, N is an integer greater than or equal to 2; one end of a fan-out line is electrically connected to the second pole of each transistor in the same first sub-circuit; the second circuit includes one or more second sub-circuits, the second sub-circuit includes N transistors, the first pole of each transistor in the second sub-circuit is respectively electrically connected to an output pin, and the second pole of each transistor in the same second sub-circuit is electrically connected to the other end of a fan-out line; wherein a transistor in the first sub-circuit and a transistor in the second sub-circuit are synchronously turned on or off.

[0005] In some embodiments, a channel type of a transistor in the first subcircuit is the same as a channel type of a transistor in the second subcircuit, and a gate of a transistor in the first subcircuit is electrically connected to a gate of a transistor in the second subcircuit.

[0006] In some of the embodiments, each transistor in the first sub-circuit and each transistor in the second sub-circuit are N-channel thin film transistors.

[0007] In some embodiments, the first sub-circuit includes a first transistor and a second transistor, the first electrode of the first transistor is electrically connected to the first data line, the second electrode of the first transistor is electrically connected to one end of a fan-out line, the first electrode of the second transistor is electrically connected to the second data line, and the second electrode of the second transistor is electrically connected to the second electrode of the first transistor; the second sub-circuit includes transistor A and transistor B, the first electrode of transistor A is electrically connected to the first output pin, the second electrode of transistor A is electrically connected to the other end of the fan-out line, the gate of transistor A is electrically connected to the gate of the first transistor, the first electrode of transistor B is electrically connected to the second output pin, the second electrode of transistor B is electrically connected to the second electrode of transistor A, and the gate of transistor B is electrically connected to the gate of the second transistor.

[0008] In some embodiments, the first sub-circuit also includes a third transistor, a first electrode of the third transistor is electrically connected to the third data line, and a second electrode of the third transistor is electrically connected to the second electrode of the second transistor; the second sub-circuit includes a C transistor, a first electrode of the C transistor is electrically connected to the third output pin, a second electrode of the C transistor is electrically connected to the second electrode of the B transistor, and a gate of the C transistor is electrically connected to the gate of the third transistor.

[0009] In some embodiments, the first sub-circuit also includes a fourth transistor, a first electrode of the fourth transistor is electrically connected to the fourth data line, and a second electrode of the fourth transistor is electrically connected to the second electrode of the third transistor; the second sub-circuit includes a D transistor, a first electrode of the D transistor is electrically connected to the fourth output pin, a second electrode of the D transistor is electrically connected to the second electrode of the C transistor, and a gate of the D transistor is electrically connected to the gate of the fourth transistor.

[0010] In some embodiments, the first sub-circuit also includes a fifth transistor, a first electrode of the fifth transistor is electrically connected to the fifth data line, and a second electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor; the second sub-circuit includes an E transistor, a first electrode of the E transistor is electrically connected to the fifth output pin, a second electrode of the E transistor is electrically connected to the second electrode of the D transistor, and a gate of the E transistor is electrically connected to the gate of the fifth transistor.

[0011] In some embodiments, the first sub-circuit also includes a sixth transistor, a first electrode of the sixth transistor is electrically connected to the sixth data line, and a second electrode of the sixth transistor is electrically connected to the second electrode of the fifth transistor; the second sub-circuit includes a heptathlon transistor, a first electrode of the heptathlon transistor is electrically connected to the sixth output pin, a second electrode of the heptathlon transistor is electrically connected to the second electrode of the pentathlon transistor, and a gate of the heptathlon transistor is electrically connected to the gate of the sixth transistor.

[0012] In some implementations, the N transistors in the first sub-circuit are turned on in sequence and in a time-sharing manner, and / or the N transistors in the second sub-circuit are turned on in sequence and in a time-sharing manner.

[0013] In a second aspect, the present application provides a spliced ​​display screen, which includes a plurality of display panels according to at least one of the above-mentioned embodiments, wherein the first circuit is located in a display area of ​​the display panel, and the fan-out line and the second circuit are both located in a border area of ​​the display panel.

[0014] The display panel and the spliced ​​display screen provided by the present application electrically connect the first electrode of each transistor in the first subcircuit with a data line respectively, and electrically connect the second electrode of each transistor in the same second subcircuit with a data line respectively.

[0015] The other end of a fan-out line synchronously turns on or off a transistor in the first subcircuit and a transistor in the second subcircuit, so that the first subcircuit and the second subcircuit share the same fan-out line, thereby reducing the number of fan-out lines used.

[0016] Furthermore, since the number of fan-out lines used is reduced, the space occupied by the frame area is reduced, and the seams between display panels are also reduced, which is beneficial to improving the display effect of the spliced ​​display screen. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0018] 5 Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0019] Figure 2 A comparative schematic diagram of fan-out lines provided in an embodiment of the present application.

[0020] Figure 3 Another structural schematic diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The technical solution in the embodiment of the present application will be described below in conjunction with the accompanying drawings in the embodiment of the present application.

[0022] Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0023] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features, thereby limiting the terms "first", "second" and "third" to the extent that the terms "first" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0024] The "second" feature may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise clearly and specifically defined.

[0025] In view of the technical problem mentioned above that the number of fan-out lines 300 in the border area is too large, this embodiment

[0026] A display panel is provided, see Figures 1 to 3 ,like Figure 1As shown, the display panel includes a first circuit 100, a fan-out line 300 and a second circuit 200, the first circuit 100 includes one or more first sub-circuits 110, the first sub-circuit 110 includes N transistors, the first electrode of each transistor in the first sub-circuit 110 is electrically connected to a data line, N is an integer greater than or equal to 2; one end of a fan-out line 300 is electrically connected to the second electrode of each transistor in the same first sub-circuit 110; the second circuit 200 includes one or more second sub-circuits 210, the second sub-circuit 210 includes N transistors, the first electrode of each transistor in the second sub-circuit 210 is electrically connected to an output pin, and the second electrode of each transistor in the same second sub-circuit 210 is electrically connected to the other end of a fan-out line 300; wherein a transistor in the first sub-circuit 110 and a transistor in the second sub-circuit 210 are synchronously turned on or off.

[0027] It can be understood that the display panel and spliced ​​display screen provided in this embodiment can electrically connect the first electrode of each transistor in the first sub-circuit 110 with a data line, and electrically connect the second electrode of each transistor in the same second sub-circuit 210 with the other end of a fan-out line 300, and synchronously turn on or off a transistor in the first sub-circuit 110 and a transistor in the second sub-circuit 210, so that the first sub-circuit 110 and the second sub-circuit 210 can share the same fan-out line 300, thereby reducing the number of fan-out lines 300 used.

[0028] Furthermore, since the number of fan-out lines 300 used is reduced, the space occupied by the frame area is reduced, and the seams between display panels are also reduced, which is beneficial to improving the display effect of the spliced ​​display screen.

[0029] It should be noted that the output pin may be an output pin of a source driver chip or a data driver circuit. Each data line is used to transmit a corresponding data signal.

[0030] In one embodiment, a channel type of a transistor in the first sub-circuit 110 is the same as a channel type of a transistor in the second sub-circuit 210 , and a gate of a transistor in the first sub-circuit 110 is electrically connected to a gate of a transistor in the second sub-circuit 210 .

[0031] It should be noted that when a transistor in the first sub-circuit 110 and a transistor in the second sub-circuit 210 need to be turned on or off synchronously, both use transistors of the same channel type, and the gate of a transistor in the first sub-circuit 110 and the gate of a transistor in the second sub-circuit 210 can share the same control line, which can save the number of wirings in the border area and further reduce the space occupied by the border area.

[0032] In one embodiment, each transistor in the first sub-circuit 110 and each transistor in the second sub-circuit 210 are N-channel thin film transistors.

[0033] It should be noted that the first sub-circuit 110 and the second sub-circuit 210 both use the same type of transistors, which is conducive to simplifying the manufacturing process of all transistors. Of course, this embodiment is not intended to limit the channel type of each transistor to N-channel type, and can also be P-channel type.

[0034] In one embodiment, if Figure 1 As shown, the first sub-circuit 110 includes a first transistor U1 and a second transistor U2, wherein a first electrode of the first transistor U1 is electrically connected to a first data line D1, a second electrode of the first transistor U1 is electrically connected to one end of a fan-out line 300, a first electrode of the second transistor U2 is electrically connected to a second data line D2, and a second electrode of the second transistor U2 is electrically connected to a second electrode of the first transistor U1; the second sub-circuit 210 includes a first transistor T1 and a second transistor T2, wherein a first electrode of the first transistor T1 is electrically connected to a first output pin S1, a second electrode of the first transistor T1 is electrically connected to the other end of the fan-out line 300, a gate of the first transistor T1 is electrically connected to a gate of the first transistor U1, a first electrode of the second transistor T2 is electrically connected to a second output pin S2, a second electrode of the second transistor T2 is electrically connected to a second electrode of the first transistor T1, and a gate of the second transistor T2 is electrically connected to a gate of the second transistor U2.

[0035] It should be noted that the gate of transistor A T1 and the gate of the first transistor U1 share the first control line M1, and the gate of transistor B T2 and the gate of the second transistor U2 share the second control line M2. This can save the number of wiring in the border area and further reduce the occupied space of the border area.

[0036] In one embodiment, the first sub-circuit 110 also includes a third transistor U3, a first electrode of the third transistor U3 is electrically connected to the third data line D3, and a second electrode of the third transistor U3 is electrically connected to the second electrode of the second transistor U2; the second sub-circuit 210 includes a C transistor T3, a first electrode of the C transistor T3 is electrically connected to the third output pin S3, a second electrode of the C transistor T3 is electrically connected to the second electrode of the B transistor T2, and a gate of the C transistor T3 is electrically connected to the gate of the third transistor U3.

[0037] It should be noted that the gate of the third transistor T3 and the gate of the third transistor U3 share the third control line M3, which can save the number of wirings in the border area and further reduce the occupied space of the border area.

[0038] In one embodiment, the first sub-circuit 110 also includes a fourth transistor U4, a first electrode of the fourth transistor U4 is electrically connected to the fourth data line D4, and a second electrode of the fourth transistor U4 is electrically connected to the second electrode of the third transistor U3; the second sub-circuit 210 includes a D transistor T4, a first electrode of the D transistor T4 is electrically connected to the fourth output pin S4, a second electrode of the D transistor T4 is electrically connected to the second electrode of the C transistor T3, and a gate of the D transistor T4 is electrically connected to the gate of the fourth transistor U4.

[0039] It should be noted that the gate of the fourth transistor T4 and the gate of the fourth transistor U4 share the fourth control line M4, which can save the number of wirings in the border area and further reduce the occupied space of the border area.

[0040] In one embodiment, the first sub-circuit 110 also includes a fifth transistor U5, a first electrode of the fifth transistor U5 is electrically connected to the fifth data line D5, and a second electrode of the fifth transistor U5 is electrically connected to the second electrode of the fourth transistor U4; the second sub-circuit 210 includes a fifth transistor T5, a first electrode of the fifth transistor T5 is electrically connected to the fifth output pin S5, a second electrode of the fifth transistor T5 is electrically connected to the second electrode of the fourth transistor T4, and a gate of the fifth transistor T5 is electrically connected to the gate of the fifth transistor U5.

[0041] It should be noted that the gate of the fifth transistor T5 and the gate of the fifth transistor U5 share the fifth control line M5, which can save the number of wirings in the border area and further reduce the occupied space of the border area.

[0042] In one embodiment, the first sub-circuit 110 also includes a sixth transistor U6, a first electrode of the sixth transistor U6 is electrically connected to the sixth data line D6, and a second electrode of the sixth transistor U6 is electrically connected to the second electrode of the fifth transistor U5; the second sub-circuit 210 includes a heptathlon transistor T6, a first electrode of the heptathlon transistor T6 is electrically connected to the sixth output pin S6, a second electrode of the heptathlon transistor T6 is electrically connected to the second electrode of the fifth transistor T5, and a gate of the heptathlon transistor T6 is electrically connected to the gate of the sixth transistor U6.

[0043] It should be noted that the gate of the sixth transistor T6 and the gate of the sixth transistor U6 share the sixth control line M6, which can save the number of wirings in the border area and further reduce the occupied space of the border area.

[0044] It should be noted that as the number of transistors in the first sub-circuit 110 and the second sub-circuit 210 increases, more fan-out lines 300 can be saved. For example, taking a display panel with 600 output pins as an example, Figure 2 The unused Figure 1In the case of the circuit shown, 600 fan-out lines 300 are required, resulting in the space occupied by the fan-out lines 300 (as shown in the dotted box) being both wide and high; Figure 1 , Figure 2 As shown in the middle right figure, when the first sub-circuit 110 and the second sub-circuit 210 each include six transistors, only 100 fan-out lines 300 are needed. The height space required by 100 fan-out lines 300 is significantly smaller than the height space required by 600 fan-out lines 300. Even if the space required by the first circuit 100 and the second circuit 200 is added, the space is still smaller than before the improvement. Under the same conditions, the pitch between the fan-out lines 300 is Figure 2 The fan-out line 300 shown in the middle right figure occupies approximately Figure 2 The fan-out line 300 shown in the middle left figure occupies about 1 / 6 of the space, which achieves the purpose of narrow frame.

[0045] In one embodiment, the N transistors in the first sub-circuit 110 are turned on in sequence and in a time-sharing manner, and / or the N transistors in the second sub-circuit 210 are turned on in sequence and in a time-sharing manner.

[0046] For example, the first transistor U1 and the transistor A T1 are turned on synchronously, and then the second transistor U2 and the transistor B T2 are turned on synchronously, and so on.

[0047] In one embodiment, this embodiment provides a spliced ​​display screen, which includes a plurality of display panels according to at least one of the above embodiments. Figures 1 to 3 As shown, the first circuit 100 is located in the display area AA of the display panel, and the fan-out line 300 and the second circuit 200 are both located in the border area of ​​the display panel.

[0048] It can be understood that, since the spliced ​​display screen provided in this embodiment includes multiple display panels of at least one of the above-mentioned embodiments, it is also possible to synchronously turn on or off a transistor in the first subcircuit 110 and a transistor in the second subcircuit 210 by electrically connecting the first electrode of each transistor in the first subcircuit 110 to a data line, and electrically connecting the second electrode of each transistor in the same second subcircuit 210 to the other end of a fan-out line 300, so that the first subcircuit 110 and the second subcircuit 210 can share the same fan-out line 300, thereby reducing the number of fan-out lines 300 used.

[0049] Furthermore, since the number of fan-out lines 300 used is reduced, the space occupied by the frame area is reduced, and the seams between display panels are also reduced, which is beneficial to improving the display effect of the spliced ​​display screen.

[0050] It needs to be explained that if Figure 2 , Figure 3 As shown, in Figure 2The display area AA shown in FIG. 1 has multiple Figure 3 In the clear area P2 shown, each clear area P2 is provided with a pixel area P1, and the pixel area P1 has a clear area P3, and the clear area P3 is provided with a light emitting device P7 and a driving circuit P6. Among them, since there are only data lines (shown in the dotted box indicated by P5) and scan lines (shown in the dotted box indicated by P4) in the clear area P2 and the clear area P3, and no other wiring is placed, this makes the display panel easy to cut.

[0051] The first circuit 100 can be placed in the area occupied by the driving circuit P6, which further reduces the occupied space of the border area.

[0052] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0053] The display panel and spliced ​​display screen provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises: A first circuit, wherein the first circuit includes one or more first sub-circuits, the first sub-circuit includes N transistors, a first electrode of each transistor in the first sub-circuit is electrically connected to a data line, and N is an integer greater than or equal to 2; A fan-out line, one end of which is electrically connected to the second electrode of each transistor in the same first sub-circuit; a second circuit, wherein the second circuit includes one or more second sub-circuits, the second sub-circuit includes N transistors, a first electrode of each transistor in the second sub-circuit is electrically connected to an output pin, and a second electrode of each transistor in the same second sub-circuit is electrically connected to the other end of one of the fan-out lines; Wherein, a transistor in the first sub-circuit and a transistor in the second sub-circuit are turned on or off synchronously.

2. The display panel according to claim 1, characterized in that: A channel type of a transistor in the first sub-circuit is the same as a channel type of a transistor in the second sub-circuit, and a gate of a transistor in the first sub-circuit is electrically connected to a gate of a transistor in the second sub-circuit.

3. The display panel according to claim 2, characterized in that: Each transistor in the first sub-circuit and each transistor in the second sub-circuit are N-channel thin film transistors.

4. The display panel according to claim 1, characterized in that: The first sub-circuit includes a first transistor and a second transistor, wherein a first electrode of the first transistor is electrically connected to a first data line, a second electrode of the first transistor is electrically connected to one end of the fan-out line, a first electrode of the second transistor is electrically connected to a second data line, and a second electrode of the second transistor is electrically connected to a second electrode of the first transistor; The second sub-circuit includes transistor A and transistor B, the first electrode of transistor A is electrically connected to the first output pin, the second electrode of transistor A is electrically connected to the other end of the fan-out line, the gate of transistor A is electrically connected to the gate of the first transistor, the first electrode of transistor B is electrically connected to the second output pin, the second electrode of transistor B is electrically connected to the second electrode of transistor A, and the gate of transistor B is electrically connected to the gate of the second transistor.

5. The display panel according to claim 4, characterized in that: The first sub-circuit further includes a third transistor, a first electrode of the third transistor is electrically connected to the third data line, and a second electrode of the third transistor is electrically connected to the second electrode of the second transistor; The second sub-circuit includes a C transistor, a first electrode of the C transistor is electrically connected to the third output pin, a second electrode of the C transistor is electrically connected to the second electrode of the B transistor, and a gate of the C transistor is electrically connected to the gate of the third transistor.

6. The display panel according to claim 5, characterized in that: The first sub-circuit further includes a fourth transistor, a first electrode of the fourth transistor is electrically connected to the fourth data line, and a second electrode of the fourth transistor is electrically connected to the second electrode of the third transistor; The second sub-circuit includes a D transistor, a first electrode of the D transistor is electrically connected to the fourth output pin, a second electrode of the D transistor is electrically connected to the second electrode of the C transistor, and a gate of the D transistor is electrically connected to the gate of the fourth transistor.

7. The display panel according to claim 6, characterized in that: The first sub-circuit further includes a fifth transistor, a first electrode of the fifth transistor is electrically connected to the fifth data line, and a second electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor; The second sub-circuit includes a transistor E, a first electrode of the transistor E is electrically connected to the fifth output pin, a second electrode of the transistor E is electrically connected to the second electrode of the transistor D, and a gate of the transistor E is electrically connected to the gate of the fifth transistor.

8. The display panel according to claim 7, characterized in that: The first sub-circuit further includes a sixth transistor, a first electrode of the sixth transistor is electrically connected to the sixth data line, and a second electrode of the sixth transistor is electrically connected to the second electrode of the fifth transistor; The second sub-circuit includes a H transistor, a first electrode of the H transistor is electrically connected to the sixth output pin, a second electrode of the H transistor is electrically connected to the second electrode of the E transistor, and a gate of the H transistor is electrically connected to the gate of the sixth transistor.

9. The display panel according to any one of claims 1 to 8, characterized in that: The N transistors in the first sub-circuit are turned on in sequence and in a time-sharing manner, and / or the N transistors in the second sub-circuit are turned on in sequence and in a time-sharing manner.

10. A spliced ​​display screen, characterized in that: The spliced ​​display screen comprises a plurality of display panels according to any one of claims 1 to 9, wherein the first circuit is located in a display area of ​​the display panel, and the fan-out line and the second circuit are both located in a border area of ​​the display panel.

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