A single-pole eight-throw switch driving circuit

Abstract

The application discloses a single-pole eight-throw switch driving circuit and belongs to the technical field of electronic circuits. The single-pole eight-throw switch driving circuit comprises a single-pole eight-throw switch chip driving unit and a single-pole single-throw switch chip driving unit; the single-pole eight-throw switch chip driving unit is formed by cascading one 3-8 decoder N1, four two-way inverters N2-N5 and three demultiplexers N6-N8, and outputs eight control voltages VC1-VC8; the single-pole single-throw switch chip driving unit is formed by cascading one 3-8 decoder N1, four two-way inverters N2-N5 and six demultiplexers N9-N14, and outputs sixteen control voltages VS1-VS8 and VP1-VP8; the decoders and inverters in the single-pole eight-throw switch chip driving unit and the single-pole single-throw switch chip driving unit are common circuits. The application solves the problems of a large number of external I / O interface requirements, insufficient driving capacity and long time delay (including turn-on and turn-off).

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, specifically relating to a single-pole eight-throw switch driving circuit, which is particularly suitable as a switching module driving circuit for a satellite communication microwave channel switching matrix. Background Technology

[0002] The number, level, and drive capability of external control interfaces often do not match the requirements, so interface expansion and conversion need to be performed in the internal circuit.

[0003] Port expansion mainly involves a CPU and a decoder. The CPU can be a microcontroller, ARM, or FPGA, etc. This method requires the CPU to internally convert and output commands received from the host computer, given a defined interface protocol (RS485, RS422, or CAN, etc.). This method has a relatively complex protocol and program, a long latency (including on / off states), and a certain power consumption. The decoder includes 3-to-8 decoders, 4-to-10 decoders, NOT gates, etc., selected based on the number of ports to be expanded, ultimately achieving the purpose of interface expansion.

[0004] Potential shifting circuits can convert voltage levels, such as converting a single control voltage from +5V to -5V, or 0V to +5V; or converting complementary control voltages from 0V / 5V to 0V / -5V, etc. Potential shifting circuits are commonly implemented using diodes, transistors, field-effect transistors, and demultiplexers. Among these, potential shifting circuits using demultiplexers are widely used due to their high integration density. Summary of the Invention

[0005] This invention discloses a single-pole eight-throw switch driving circuit to solve the problems of existing switch driving circuits having a large number of external I / O interfaces, insufficient driving capability, and long delay (including turn-on and turn-off).

[0006] The technical solution of this invention is as follows:

[0007] A single-pole eight-throw switch driving circuit includes a single-pole eight-throw switch chip driving unit and a single-pole single-throw switch chip driving unit. The single-pole eight-throw switch chip driving unit is composed of a cascaded 3-8 decoder N1, four dual-channel inverters N2 to N5 and three demultiplexers N6 to N8. The single-pole single-throw switch chip driving unit is composed of a cascaded 3-8 decoder N1, four dual-channel inverters N2 to N5 and six demultiplexers N9 to N14. The 3-8 decoder N1 and the dual-channel inverters N2 to N5 in the two driving units are common circuits.

[0008] Furthermore, the input pins A, B, and C of the 3-8 decoder N1 are connected to input signals I / O1, I / O2, and I / O3, respectively. The enable pins E1 and E2 of the 3-8 decoder N1 are connected to ground. The power supply pin VCC and enable pin E3 of the 3-8 decoder N1 are both connected to +5V. The GND pin of the 3-8 decoder N1 is connected to ground. The output pin Y0 of the 3-8 decoder N1 is connected to the input pin 1A of the dual-channel inverter N2 and the input pin C of the demultiplexer N9, respectively. The output pin Y1 of the 3-8 decoder N1 is connected to the input pin 2A of the dual-channel inverter N2 and the input pin C of the demultiplexer N10, respectively. Y2 is connected to input pin 1A of the dual-channel inverter N3 and input pin B of the demultiplexer N10, respectively. Y3, the output pin of the 3-8 decoder N1, is connected to input pin 2A of the dual-channel inverter N3 and input pin B of the demultiplexer N11, respectively. Y4, the output pin of the 3-8 decoder N1, is connected to input pin 1A of the dual-channel inverter N4 and input pin A of the demultiplexer N11, respectively. Y5, the output pin of the 3-8 decoder N1, is connected to input pin 2A of the dual-channel inverter N4 and input pin A of the demultiplexer N12, respectively. Y6, the output pin of the 3-8 decoder N1, is connected to input pin 1A of the dual-channel inverter N5 and input pin C of the demultiplexer N13, respectively. The output pin Y7 of the 3-8 decoder N1 is connected to the input pin 2A of the dual-channel inverter N5 and the input pin B of the demultiplexer N14, respectively. The VCC pins of the dual-channel inverters N2 to N5 are all connected to +5V, and the GND pins of the dual-channel inverters N2 to N5 are all connected to ground. The output pin 1Y of the dual-channel inverter N2 is connected to the input pin B of the demultiplexer N9 and the input pin A of the demultiplexer N6, respectively. The output pin 2Y of the dual-channel inverter N2 is connected to the input pin A of the demultiplexer N9 and the input pin B of the demultiplexer N6, respectively. The output pin 1Y of the dual-channel inverter N3 is connected to the input pin A of the demultiplexer N10 and the input pin C of the demultiplexer N6, respectively. The output pin 2Y of the dual-channel inverter N3 is connected to the input pin C of the demultiplexer N11 and the input pin A of the demultiplexer N7, respectively. The output pin 1Y of the dual-channel inverter N4 is connected to the input pin C of the demultiplexer N12 and the input pin B of the demultiplexer N7, respectively. The output pin 2Y of the dual-channel inverter N4 is connected to the input pin B of the demultiplexer N12 and the input pin C of the demultiplexer N7, respectively. The output pin 1Y of the dual-channel inverter N5 is connected to the input pin B of the demultiplexer N13 and the input pin B of the demultiplexer N8, respectively. The output pin 2Y of the dual-channel inverter N5 is connected to the input pin C of the demultiplexer N14 and the input pin C of the demultiplexer N8, respectively.The power supply pin VDD of demultiplexers N9-N14 is connected to +5V. The X0, Y0, Z0, En, and GND pins of demultiplexers N9-N12 and the Y0, Z0, En, and GND pins of demultiplexers N13 and N14 are all connected to ground. The X1, Y1, Z1, and VEE pins of demultiplexers N9-N12 and the Y1, Z1, and VEE pins of demultiplexers N13 and N14 are all connected to -5V. The output pin X of demultiplexer N9 is connected to the output signal VP2. The output pin Y of demultiplexer N9 is connected to the output signal VP1. The output pin Z of demultiplexer N9 is connected to the output signal VS1. Demultiplexer N10's output pin X is connected to output signal VP3; demultiplexer N10's output pin Y is connected to output signal VS3; demultiplexer N10's output pin Z is connected to output signal VS2; demultiplexer N11's output pin X is connected to output signal VS5; demultiplexer N11's output pin Y is connected to output signal VS4; demultiplexer N11's output pin Z is connected to output signal VP4; demultiplexer N12's output pin X is connected to output signal VS6; demultiplexer N12's output pin Y is connected to output signal VP6; demultiplexer N12's output pin Z is connected to output signal VP5. The output pins of demultiplexers N13 and N14 are connected as follows: pin Y is connected to output signal VP7, pin Z is connected to output signal VS7, pin Y is connected to output signal VS8, and pin Z is connected to output signal VP8. The power supply pins VDD of demultiplexers N6-N8 are all connected to +5V. The En and GND pins of demultiplexers N6 and N8 are connected to ground. The X0, Y0, and Z0 pins of demultiplexers N6-N7 and the Y0 and Z0 pins of demultiplexer N8 are all connected to +5V. The X1, Y1, Z1, and VEE pins of demultiplexers N6 and N7 are connected to ground. The Y1, Z1, and VEE pins of demultiplexer N8 are all connected to -5V. The X output pin of demultiplexer N6 is connected to output signal VC1; the Y output pin of demultiplexer N6 is connected to output signal VC2; the Z output pin of demultiplexer N6 is connected to output signal VC3. The X output pin of demultiplexer N7 is connected to output signal VC4; the Y output pin of demultiplexer N7 is connected to output signal VC5; the Z output pin of demultiplexer N7 is connected to output signal VC6. The Y output pin of demultiplexer N8 is connected to output signal VC7; the Z output pin of demultiplexer N8 is connected to output signal VC8.

[0009] Furthermore, the switch driver circuit has 3 input I / O ports (I / O1 to I / O3) and 24 output I / O ports. Specifically, the single-pole eight-throw switch chip driver unit outputs 8 control voltages (VC1 to VC8), each controlling one RF channel; the single-pole single-throw switch chip driver unit outputs 16 control voltages (VS1 to VS8, VP1 to VP8), with each set of control voltages VSn and VPn (n = 1 to 8) controlling one RF channel.

[0010] Furthermore, the input port voltage (I / O1~I / O3) is +5V / 0V; the single-pole eight-throw switch chip driver unit realizes the transformation of the input voltage, and the final output voltage (VC1~VC8) is +5V / -5V; the single-pole single-throw switch chip driver unit realizes the expansion and transformation of the input voltage, and the final output voltage (VS1~VS8, VP1~VP8) is 0V / -5V, and the voltages VSn and VPn (n=1~8) of a certain channel are complementary.

[0011] Furthermore, the 3-8 decoder N1 is model 74HC138, the dual inverters (N2-N5) are model 74LVC2G04DBV, and the demultiplexer (N6-N14) is model 74HC4053D.

[0012] The beneficial effects of the above-mentioned technical solution of the present invention compared with the prior art are as follows:

[0013] The driving circuit provided by this invention drives a high-isolation single-pole eight-throw switch for switching. This single-pole eight-throw switch consists of one single-pole eight-throw switch chip and eight single-pole single-throw switch chips. Each RF channel of the single-pole eight-throw switch chip is cascaded with one single-pole single-throw switch chip to increase port isolation. The single-pole eight-throw switch chip includes eight control bits: VC1, VC2, VC3, VC4, VC5, VC6, VC7, and VC8; each single-pole single-throw switch chip includes two control bits: VS and VP.

[0014] In terms of the control logic of the single-pole eight-throw switch chip, when VC1 is -5V and the others are +5V, RF channel 1 is turned on; when VC2 is -5V and the others are +5V, RF channel 2 is turned on; when VC3 is -5V and the others are +5V, RF channel 3 is turned on; when VC4 is -5V and the others are +5V, RF channel 4 is turned on; when VC5 is -5V and the others are +5V, RF channel 5 is turned on; when VC6 is -5V and the others are +5V, RF channel 6 is turned on; when VC7 is -5V and the others are +5V, RF channel 7 is turned on; and when VC8 is -5V and the others are +5V, RF channel 8 is turned on.

[0015] In the control bits of the single-pole single-throw switch chip, the RF channel is turned on when VS is 0V and VP is -5V; the RF channel is turned off when VS is -5V and VP is 0V.

[0016] For a 3-to-8 decoder, input 000 corresponds to output 01111111; input 001 corresponds to output 10111111; input 010 corresponds to output 11011111; input 011 corresponds to output 11101111; input 100 corresponds to output 11110111; input 101 corresponds to output 11111011; input 110 corresponds to output 11111101; and input 111 corresponds to output 11111110. Here, low level 0 represents 0V, and high level 1 represents +5V.

[0017] For a NOT gate, there are two independent channels: 0 input and 1 output, or 1 input and 0 output. A low level (0) represents 0V, and a high level (1) represents +5V.

[0018] The corresponding demultiplexer contains 3 independent channels. When A is low, X switches to X0, and when A is high, X switches to X1; when B is low, Y switches to Y0, and when B is high, Y switches to Y1; when C is low, Z switches to Z0, and when C is high, Z switches to Z1. Attached Figure Description

[0019] Figure 1 This is the circuit schematic diagram of the present invention;

[0020] Figure 2 This is a partial schematic diagram of the single-pole eight-throw switch chip of the present invention;

[0021] Figure 3 This is a partial schematic diagram of the single-pole single-throw switch chip of the present invention;

[0022] Figure 4 This is a waveform diagram of the driving voltage of the single-pole eight-throw switch chip of the present invention;

[0023] Figure 5 This is a waveform diagram of the driving voltage of the single-pole single-throw switch chip of the present invention. Detailed Implementation

[0024] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0025] like Figures 1 to 3As shown, the present invention discloses a single-pole eight-throw switch driving circuit, comprising a single-pole eight-throw switch chip driving unit and a single-pole single-throw switch chip driving unit; characterized in that the single-pole eight-throw switch chip driving unit is composed of a cascaded 3-8 decoder (N1), four dual-channel inverters (N2-N5) and three demultiplexers (N6-N8), and the single-pole single-throw switch chip driving unit is composed of a cascaded 3-8 decoder (N1), four dual-channel inverters (N2-N5) and six demultiplexers (N9-N14), wherein the decoder and inverter in the two driving units are common circuits.

[0026] The switch driver circuit has 3 input I / O ports and 24 output I / O ports. Specifically, the single-pole eight-throw switch chip driver unit outputs 8 control voltages, each controlling one RF channel; the single-pole single-throw switch chip driver unit outputs 16 control voltages, with every 2 voltages controlling one RF channel.

[0027] The input pins A, B, and C of the 3-8 decoder N1 are connected to input signals I / O1, I / O2, and I / O3, respectively. The enable pins E1 and E2 of the 3-8 decoder N1 are connected to ground. The power supply pin VCC and enable pin E3 of the 3-8 decoder N1 are both connected to +5V. The GND pin of the 3-8 decoder N1 is connected to ground. The output pin Y0 of the 3-8 decoder N1 is connected to the input pin 1A of the dual-channel inverter N2 and the input pin C of the demultiplexer N9, respectively. The output pin Y1 of the 3-8 decoder N1 is connected to the input pin 2A of the dual-channel inverter N2 and the input pin C of the demultiplexer N10, respectively. The output pin Y2 of the 3-8 decoder N1 is connected to... The input pin Y3 of the 3-8 decoder N1 is connected to the input pin 1A of the dual-channel inverter N3 and the input pin B of the demultiplexer N10. The output pin Y4 of the 3-8 decoder N1 is connected to the input pin 1A of the dual-channel inverter N4 and the input pin A of the demultiplexer N11. The output pin Y5 of the 3-8 decoder N1 is connected to the input pin 2A of the dual-channel inverter N4 and the input pin A of the demultiplexer N12. The output pin Y6 of the 3-8 decoder N1 is connected to the input pin 1A of the dual-channel inverter N5 and the input pin C of the demultiplexer N13. The output pin Y7 of decoder N1 is connected to the input pin 2A of dual-channel inverter N5 and the input pin B of demultiplexer N14, respectively. The VCC pins of dual-channel inverters N2 to N5 are all connected to +5V, and the GND pins of dual-channel inverters N2 to N5 are all connected to ground. The output pin 1Y of dual-channel inverter N2 is connected to the input pin B of demultiplexer N9 and the input pin A of demultiplexer N6, respectively. The output pin 2Y of dual-channel inverter N2 is connected to the input pin A of demultiplexer N9 and the input pin B of demultiplexer N6, respectively. The output pin 1Y of dual-channel inverter N3 is connected to the input pin A of demultiplexer N10 and the input pin C of demultiplexer N6, respectively. The output pin 2Y of the dual-channel inverter N3 is connected to the input pin C of the demultiplexer N11 and the input pin A of the demultiplexer N7, respectively. The output pin 1Y of the dual-channel inverter N4 is connected to the input pin C of the demultiplexer N12 and the input pin B of the demultiplexer N7, respectively. The output pin 2Y of the dual-channel inverter N4 is connected to the input pin B of the demultiplexer N12 and the input pin C of the demultiplexer N7, respectively. The output pin 1Y of the dual-channel inverter N5 is connected to the input pin B of the demultiplexer N13 and the input pin B of the demultiplexer N8, respectively. The output pin 2Y of the dual-channel inverter N5 is connected to the input pin C of the demultiplexer N14 and the input pin C of the demultiplexer N8, respectively.The power supply pin VDD of demultiplexers N9-N14 is connected to +5V. The X0, Y0, Z0, En, and GND pins of demultiplexers N9-N12 and the Y0, Z0, En, and GND pins of demultiplexers N13 and N14 are all connected to ground. The X1, Y1, Z1, and VEE pins of demultiplexers N9-N12 and the Y1, Z1, and VEE pins of demultiplexers N13 and N14 are all connected to -5V. The output pin X of demultiplexer N9 is connected to the output signal VP2. The output pin Y of demultiplexer N9 is connected to the output signal VP1. The output pin Z of demultiplexer N9 is connected to the output signal VS1. Demultiplexer N10's output pin X is connected to output signal VP3; demultiplexer N10's output pin Y is connected to output signal VS3; demultiplexer N10's output pin Z is connected to output signal VS2; demultiplexer N11's output pin X is connected to output signal VS5; demultiplexer N11's output pin Y is connected to output signal VS4; demultiplexer N11's output pin Z is connected to output signal VP4; demultiplexer N12's output pin X is connected to output signal VS6; demultiplexer N12's output pin Y is connected to output signal VP6; demultiplexer N12's output pin Z is connected to output signal VP5. The output pins of demultiplexers N13 and N14 are connected as follows: pin Y is connected to output signal VP7, pin Z is connected to output signal VS7, pin Y is connected to output signal VS8, and pin Z is connected to output signal VP8. The power supply pins VDD of demultiplexers N6-N8 are all connected to +5V. The En and GND pins of demultiplexers N6 and N8 are connected to ground. The X0, Y0, and Z0 pins of demultiplexers N6-N7 and the Y0 and Z0 pins of demultiplexer N8 are all connected to +5V. The X1, Y1, Z1, and VEE pins of demultiplexers N6 and N7 are connected to ground. The Y1, Z1, and VEE pins of demultiplexer N8 are all connected to -5V. The X output pin of demultiplexer N6 is connected to output signal VC1; the Y output pin of demultiplexer N6 is connected to output signal VC2; the Z output pin of demultiplexer N6 is connected to output signal VC3. The X output pin of demultiplexer N7 is connected to output signal VC4; the Y output pin of demultiplexer N7 is connected to output signal VC5; the Z output pin of demultiplexer N7 is connected to output signal VC6. The Y output pin of demultiplexer N8 is connected to output signal VC7; the Z output pin of demultiplexer N8 is connected to output signal VC8.

[0028] The working principle of this invention is as follows:

[0029] 1. This invention uses a combination of decoder, inverter and demultiplexer to drive a single-pole eight-throw switch, and outputs different TTL level combinations according to the different level configurations of the three I / O ports of the host computer.

[0030] When input 2.000, VC1 is -5V, VC2-VC8 are +5V, VS1 is 0V, VS2-VS8 are -5V, VP1 is -5V, and VP2-VP8 are 0V. At this time, RF channel 1 is activated. When input 001, VC2 is -5V, VC1, VC3-VC8 are +5V, VS2 is 0V, VS1, VS3-VS8 are -5V, VP2 is -5V, and VP1, VP3-VP8 are 0V. At this time, RF channel 2 is activated. When input 010, VC3 is -5V, V... When C1-VC2 and VC4-VC8 are +5V, VS3 is 0V, VS1-VS2 and VS4-VS8 are -5V, VP3 is -5V, and VP1-VP2 and VP4-VP8 are 0V, the RF channel 3 is activated. With input 011, VC4 is -5V, VC1-VC3 and VC5-VC8 are +5V, VS4 is 0V, VS1-VS3 and VS5-VS8 are -5V, VP4 is -5V, and VP1-VP3 and VP5-VP8 are 0V, the RF channel 4 is activated. With input 100, VC5 is -5V, VC1~VC4 and VC6~VC8 are +5V, VS5 is 0V, VS1~VS4 and VS6~VS8 are -5V, VP5 is -5V, and VP1~VP4 and VP6~VP8 are 0V. At this time, drive RF channel 5 is turned on. With input 101, VC6 is -5V, VC1~VC5 and VC7~VC8 are +5V, VS6 is 0V, VS1~VS5 and VS7~VS8 are -5V, VP6 is -5V, and VP1~VP5 and VP7~... When VP8 is 0V, RF channel 6 is turned on. When input 110, VC7 is -5V, VC1~VC6 and VC8 are +5V, VS7 is 0V, VS1~VS6 and VS8 are -5V, VP7 is -5V, VP1~VP6 and VP8 are 0V, and RF channel 7 is turned on. When input 111, VC8 is -5V, VC1~VC7 are +5V, VS8 is 0V, VS1~VS7 are -5V, VP8 is -5V, and VP1~VP7 are 0V, and RF channel 8 is turned on.

[0031] The present invention was simulated, and the simulation curves are as follows: Figures 4-5 As shown in the figure, the voltage output waveforms of the two driving circuits match the logic truth table of the chip, enabling normal switching. The propagation delay of the 3-8 decoder 74HC138 is about 20ns, the propagation delay of the dual inverter 74LVC2G04DBV is about 3ns, and the propagation delay of the demultiplexer 74HC4053D is about 18ns. The total propagation delay of this driving circuit is about 40ns.

[0032] In summary, compared with the prior art, the present invention has the advantages of simple port and flexible configuration, and is an important improvement of the prior art.

[0033] It should be understood that the above description of the specific embodiments of this patent is merely an exemplary description provided to facilitate understanding of the patent solution by those skilled in the art, and does not imply that the scope of protection of this patent is limited to these specific examples. Those skilled in the art can obtain more specific embodiments without any creative effort by combining technical features, replacing some technical features, adding more technical features, etc., of the various examples listed in this patent, provided that they have a full understanding of the technical solution of this patent. All of these specific embodiments are within the scope of the claims of this patent, and therefore, these new specific embodiments should also be within the scope of protection of this patent.

Claims

1. A single-pole eight-throw switch driving circuit, comprising a single-pole eight-throw switch chip driving unit and a single-pole single-throw switch chip driving unit; characterized in that, The single-pole eight-throw switch chip driving unit is composed of a cascaded 3-to-8 decoder (N1), four dual-channel inverters (N2-N5) and three demultiplexers (N6-N8); The single-pole single-throw switch chip driver unit is composed of a cascaded 3-8 decoder (N1), four dual-channel inverters (N2-N5) and six demultiplexers (N9-N14). The 3-8 decoder (N1) and dual-channel inverters (N2-N5) in the single-pole single-throw switch chip driver unit and the single-pole single-throw switch chip driver unit are common circuits.

2. The single-pole eight-throw switch driving circuit according to claim 1, characterized in that, The input pins A, B, and C of the 3-8 decoder (N1) are connected to input signals I / O1, I / O2, and I / O3, respectively. The enable pins E1 and E2 of the 3-8 decoder (N1) are connected to ground. The power supply pin VCC and enable pin E3 of the 3-8 decoder (N1) are both connected to +5V. The GND pin of the 3-8 decoder (N1) is connected to ground. The output pin Y0 of the 3-8 decoder (N1) is connected to the input pin 1A of the dual-channel inverter (N2) and the input pin C of the demultiplexer (N9), respectively. The output pin Y1 of the 3-8 decoder (N1) is connected to the input pin 2A of the dual-channel inverter (N2) and the input pin C of the demultiplexer (N10), respectively. The output pin Y2 of the 3-8 decoder (N1) is connected to the input pin 1A of the dual-channel inverter (N3) and the input pin C of the demultiplexer (N10), respectively. The input pin B is connected, and the output pin Y3 of the 3-8 decoder (N1) is connected to the input pin 2A of the dual-channel inverter (N3) and the input pin B of the demultiplexer (N11), respectively. The output pin Y4 of the 3-8 decoder (N1) is connected to the input pin 1A of the dual-channel inverter (N4) and the input pin A of the demultiplexer (N11), respectively. The output pin Y5 of the 3-8 decoder (N1) is connected to the input pin 2A of the dual-channel inverter (N4) and the input pin A of the demultiplexer (N12), respectively. The output pin Y6 of the 3-8 decoder (N1) is connected to the input pin 1A of the dual-channel inverter (N5) and the input pin C of the demultiplexer (N13), respectively. The output pin Y7 of the 3-8 decoder (N1) is connected to the input pin 2A of the dual-channel inverter (N5) and the input pin B of the demultiplexer (N14), respectively. The VCC pins of the dual-channel inverters (N2-N5) are all connected to +5V, and the GND pins of the dual-channel inverters (N2-N5) are all connected to ground. The output pin 1Y of the dual-channel inverter (N2) is connected to the input pin B of the demultiplexer (N9) and the input pin A of the demultiplexer (N6), respectively. The output pin 2Y of the dual-channel inverter (N2) is connected to the input pin A of the demultiplexer (N9) and the input pin B of the demultiplexer (N6), respectively. The output pin 1Y of the dual-channel inverter (N3) is connected to the input pin A of the demultiplexer (N10) and the input pin C of the demultiplexer (N6), respectively. The output pin 2Y of the dual-channel inverter (N3) is connected to the demultiplexer (N11), respectively. The input pin C of the inverter (N4) is connected to the input pin A of the demultiplexer (N7). The output pin 1Y of the dual-channel inverter (N4) is connected to the input pin C of the demultiplexer (N12) and the input pin B of the demultiplexer (N7). The output pin 2Y of the dual-channel inverter (N4) is connected to the input pin B of the demultiplexer (N12) and the input pin C of the demultiplexer (N7). The output pin 1Y of the dual-channel inverter (N5) is connected to the input pin B of the demultiplexer (N13) and the input pin B of the demultiplexer (N8). The output pin 2Y of the dual-channel inverter (N5) is connected to the input pin C of the demultiplexer (N14) and the input pin C of the demultiplexer (N8).The power supply pin VDD of demultiplexers (N9-N14) is connected to +5V. The X0, Y0, Z0, En, and GND pins of demultiplexers (N9-N12) and the Y0, Z0, En, and GND pins of demultiplexers (N13 and N14) are all connected to ground. The X1, Y1, Z1, and VEE pins of demultiplexers (N9-N12) and the Y1, Z1, and VEE pins of demultiplexers (N13 and N14) are all connected to -5V. The output pin X of demultiplexer (N9) is connected to the output signal VP2. The output pin Y of demultiplexer (N9) is connected to the output signal VP1. The output pin Z of demultiplexer (N9) is connected to the output signal VS1. The output pin X of demultiplexer (N10) is connected to the output signal VP3. The output pin Y of demultiplexer (N10) is connected to the output signal VS3. The output pin Z of demultiplexer (N10) is connected to the output signal VS2. The output pin X of demultiplexer (N11) is connected to the output signal VS5. The output pin Y of demultiplexer (N11) is connected to the output signal VS4. The output pin Z of demultiplexer (N11) is connected to the output signal VP4. The output pin X of demultiplexer (N12) is connected to the output signal VS6. The output pin Y of demultiplexer (N12) is connected to the output signal VP6. The output pin Z of demultiplexer (N12) is connected to the output signal VP5. The output pin Y of demultiplexer (N13) is connected to the output signal VP7, and the output pin Z of demultiplexer (N13) is connected to the output signal VS7. The output pin Y of demultiplexer (N14) is connected to the output signal VS8, and the output pin Z of demultiplexer (N14) is connected to the output signal VP8. The power supply pin VDD of demultiplexers (N6~N8) is connected to +5V. The En and GND pins of demultiplexers (N6 and N8) are connected to ground. The X0, Y0, and Z0 pins of demultiplexers (N6 and N7) and the Y0 and Z0 pins of demultiplexer (N8) are connected to +5V. The X1, Y1, Z1, and VEE pins of demultiplexers (N6 and N7) are connected to +5V. The Y1, Z1, and VEE pins of the demultiplexer (N8) are all connected to -5V. The X output pin of the demultiplexer (N6) is connected to output signal VC1; the Y output pin of the demultiplexer (N6) is connected to output signal VC2; the Z output pin of the demultiplexer (N6) is connected to output signal VC3. The X output pin of the demultiplexer (N7) is connected to output signal VC4; the Y output pin of the demultiplexer (N7) is connected to output signal VC5; the Z output pin of the demultiplexer (N7) is connected to output signal VC6. The Y output pin of the demultiplexer (N8) is connected to output signal VC7; the Z output pin of the demultiplexer (N8) is connected to output signal VC8.

3. The single-pole eight-throw switch driving circuit according to claim 2, characterized in that, The switch driver circuit has 3 input I / O ports, namely I / O1 to I / O3, and the number of output I / O ports is expanded to 24. Among them, the single-pole eight-throw switch chip driver unit outputs 8 control voltages VC1 to VC8, each voltage controlling 1 RF channel; the single-pole single-throw switch chip driver unit outputs 16 control voltages VS1 to VS8 and VP1 to VP8, each control voltage VSn and VPn controlling 1 RF channel, where n = 1 to 8.

4. The single-pole eight-throw switch driving circuit according to claim 3, characterized in that, The input port voltages I / O1 to I / O3 are +5V / 0V; the single-pole eight-throw switch chip driver unit realizes the transformation of the input voltage, and the final output voltages VC1 to VC8 are +5V / -5V; the single-pole single-throw switch chip driver unit realizes the expansion and transformation of the input voltage, and the final output voltages VS1 to VS8 and VP1 to VP8 are 0V / -5V, and controls each group of voltages VSn and VPn of one channel to be complementary, where n = 1 to 8.

5. A single-pole eight-throw switch driving circuit according to claim 1, characterized in that, The 3-8 decoder (N1) is model 74HC138, the dual inverters (N2-N5) are model 74LVC2G04DBV, and the demultiplexer (N6-N14) is model 74HC4053D.

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