Fuse status detection circuit

Abstract

The present application provides a fuse state detection circuit, which includes a bias current generating circuit, a current subtractor, and a processing module; the bias current generating circuit is used to provide an adjustable bias current; the current subtractor is used to generate a fuse state detection current, the fuse state detection current being the difference between the rated current provided by the current subtractor and the bias current provided by the pre-stage bias current generating circuit; the second output end of the processing module is used to electrically connect to the fuse under test; when the state of the fuse under test is in a burned state, the output end of the processing module outputs a logic high level; when the state of the fuse under test is in an unburned state, the output end of the processing module outputs a logic low level. This allows for better detection of the state of the fuse under test, thereby resolving the problem in existing solutions of difficulty in controlling the magnitude of the fuse state detection current.

Description

Technical Field

[0001] The present application relates to the technical field of fuses, and in particular to a circuit for detecting the fuse status of a fuse. Background Art

[0002] For polysilicon fuses, the typical resistance is about tens to hundreds of ohms; for metal fuses, the typical resistance is usually lower. During the programming process, a rated programming voltage is applied to both ends of the fuse through solder pads (pads) connected to both ends of the fuse, or a rated fuse state detection current (the bias current of the current comparator in the unprogrammed state) is applied to the fuse for a certain period of time. At this time, the fuse will undergo certain physical changes, characterized by a significant increase in impedance. The current size selection in the existing solution is difficult to control. If the current margin is too large, the static power consumption will increase significantly in cases where multi-bit fuses are required. If the margin is too small, there is a risk that process fluctuations will cause the state readout circuit to fail to flip normally, resulting in a decrease in product yield. Summary of the Invention

[0003] The main purpose of the present application is to provide a circuit for detecting the fuse status of a fuse, so as to solve the problem in the existing solution that the magnitude of the fuse status detection current is difficult to control.

[0004] According to one aspect of an embodiment of the present invention, a circuit for detecting the fuse state is provided. The circuit for detecting the fuse state includes a bias current generating circuit, a current subtractor, and a processing module. The bias current generating circuit is used to provide an adjustable bias current. The current subtractor has an input terminal, a first output terminal, and a second output terminal. The current subtractor is used to generate a fuse state detection current (a bias current of a current comparator in an unwritten state). The fuse state detection current is the difference between a rated current provided by the current subtractor and the bias current. The input terminal of the current subtractor is electrically connected to the bias current generating circuit. The first output terminal of the current subtractor is used to output a bias voltage. The second output end of the current subtractor is used to output the fuse state detection current of the fuse (the bias current of the current comparator in the unwritten state); the processing module has a first input end, a second input end, a first output end and a second output end. The first input end of the processing module is electrically connected to the first output end of the current subtractor, the second input end of the processing module is electrically connected to the second output end of the current subtractor, and the second output end of the processing module is used to be electrically connected to the fuse under test. When the state of the fuse under test is a written state, the output end of the processing module outputs a logic high level; when the state of the fuse under test is an unwritten state, the output end of the processing module outputs a logic low level.

[0005] Optionally, the processing module includes a current comparator and a two-stage inverting circuit; the current comparator has a first input terminal, a second input terminal, a first output terminal, a second output terminal and a third output terminal, the first input terminal of the current comparator is electrically connected to the first output terminal of the current subtractor, the second input terminal of the current comparator is electrically connected to the second output terminal of the current subtractor, the third output terminal of the current comparator is used to be electrically connected to the fuse under test, and the current comparator is used to output a high level at the second output terminal of the current comparator when the fuse state detection current is greater than the actual current of the fuse, and output a low level when the fuse state detection current is less than the saturation pull-down current. The second output terminal of the current comparator outputs a low level; the two-stage inverter circuit has a first input terminal, a second input terminal and an output terminal, the first input terminal of the two-stage inverter circuit is electrically connected to the first output terminal of the current comparator, and the second input terminal of the two-stage inverter circuit is electrically connected to the second output terminal of the current comparator. The two-stage inverter circuit is used to invert the logic level output by the second output terminal of the current comparator twice. When the state of the fuse under test is a burned state, the output terminal of the two-stage inverter circuit outputs a logic high level. When the state of the fuse under test is an unburned state, the output terminal of the two-stage inverter circuit outputs a logic low level.

[0006] Optionally, the bias current generating circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a current regulator, the source of the first transistor and the source of the second transistor are respectively electrically connected to a voltage source, the gate of the first transistor is respectively electrically connected to the gate of the second transistor, the drain of the second transistor and the drain of the fourth transistor, the drain of the first transistor is respectively electrically connected to the gate of the fourth transistor and the drain of the third transistor, the source of the third transistor and the source of the fifth transistor are respectively grounded, the gate of the third transistor is respectively electrically connected to the drain of the fourth transistor, the current regulator and the gate of the fifth transistor, and the drain of the fifth transistor is electrically connected to the input terminal of the current subtractor.

[0007] Optionally, the current regulator includes a first resistance module, a second resistance module, a third resistance module, a first fuse, a second fuse and a third fuse, the first end of the first resistance module is electrically connected to the gate of the third transistor and the first end of the first fuse, respectively, the second end of the first resistance module is electrically connected to the second end of the first fuse, the first end of the second resistance module and the first end of the second fuse, respectively, the second end of the second resistance module is electrically connected to the second end of the second fuse, the first end of the third resistance module and the first end of the third fuse, respectively, and the second end of the third resistance module and the second end of the third fuse are grounded, respectively.

[0008] Optionally, the resistance of the first resistance module is twice the resistance of the second resistance module, and the resistance of the second resistance module is twice the resistance of the third resistance module.

[0009] Optionally, the bias current generating circuit further includes a fourth resistance module, a first end of the fourth resistance module is electrically connected to the gate of the third transistor, and a second end of the fourth resistance module is electrically connected to the first end of the first resistance module.

[0010] Optionally, the current subtractor includes a current source, a sixth transistor, a seventh transistor, an eighth transistor, a fifth resistor module and a sixth resistor module, the drain of the sixth transistor is electrically connected to the gate of the sixth transistor, the gate of the seventh transistor, the bias current generating circuit and the current source respectively, the drain of the sixth transistor serves as the input end of the current subtractor, the gate of the seventh transistor serves as the second output end of the current subtractor, the source of the sixth transistor is electrically connected to the first end of the fifth resistor module, the source of the seventh transistor is electrically connected to the first end of the sixth resistor module, the gate of the eighth transistor serves as the first output end of the current subtractor, the gate of the eighth transistor is also electrically connected to the drain of the eighth transistor and the drain of the seventh transistor respectively, the source of the eighth transistor is electrically connected to the voltage source, and the second end of the fifth resistor module and the second end of the sixth resistor module are grounded respectively.

[0011] Optionally, the current comparator includes a ninth transistor, a tenth transistor and a seventh resistor module, the gate of the ninth transistor serves as the first input terminal and the first output terminal of the current comparator, the gate of the tenth transistor serves as the second input terminal of the current comparator, the drain of the tenth transistor serves as the second output terminal of the current comparator, the drain of the tenth transistor is also electrically connected to the drain of the ninth transistor, the source of the ninth transistor is electrically connected to the voltage source, the source of the tenth transistor is electrically connected to the first end of the seventh resistor module, and the second end of the seventh resistor module is used to be electrically connected to the fuse under test.

[0012] Optionally, the two-stage inverter circuit includes an eleventh transistor, a twelfth transistor and an inverter, the gate of the eleventh transistor serves as the first input terminal of the two-stage inverter circuit, the gate of the twelfth transistor serves as the second input terminal of the two-stage inverter circuit, the output terminal of the inverter serves as the output terminal of the two-stage inverter circuit, the source of the eleventh transistor is electrically connected to the voltage source, the drain of the eleventh transistor is electrically connected to the drain of the twelfth transistor and the input terminal of the inverter respectively, and the source of the twelfth transistor is grounded.

[0013] Optionally, the detection circuit for the fuse fuse state also includes a first enabling power switch and a second enabling power switch, wherein the first enabling power switch is electrically connected between the second output terminal of the current comparator and the gate of the twelfth transistor, and the second enabling power switch is electrically connected between the drain of the twelfth transistor and the input terminal of the inverter.

[0014] In an embodiment of the present invention, a variable detection current is given to the fuse under test through a bias current generating circuit and a current subtractor. At the same time, when the state of the fuse under test is a burned state, the output end of the processing module outputs a logic high level, and when the state of the fuse under test is an unburned state, the output end of the processing module outputs a logic low level, thereby enabling better detection of the state of the fuse under test, thereby solving the problem in the existing solution that the size of the fuse fuse state detection current is difficult to control. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0016] Figure 1 A schematic diagram of a fuse state detection circuit according to an embodiment of the present application is shown;

[0017] Figure 2A schematic diagram showing a first connection method between the fuse Pad and the ground Pad is shown;

[0018] Figure 3 FIG. 4 is a schematic diagram showing a second connection method between the fuse Pad and the ground Pad.

[0019] The above drawings include the following reference numerals:

[0020] 100 , bias current generating circuit; 110 , current regulator; 200 , current subtractor; 300 , processing module; 310 , current comparator; 320 , two-stage inverter circuit; 400 , first enabling power switch; 500 , second enabling power switch. DETAILED DESCRIPTION

[0021] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0022] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0024] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element or intervening elements may be present. Moreover, in the specification and claims, when it is described that an element is "connected to" another element, the element may be "directly connected to" the other element or "connected to" the other element through a third element.

[0025] As mentioned in the background technology, the current size in the existing solution is difficult to control. If the current margin is too large, the static power consumption will increase significantly in the case where a multi-bit fuse is required; if the margin is too small, there is a risk that the state readout circuit cannot be flipped normally due to process fluctuations, resulting in a decrease in product yield. In order to solve the problem that the size of the fuse state detection current is difficult to control in the existing solution, a typical embodiment of the present application provides a fuse state detection circuit.

[0026] According to an embodiment of the present application, a circuit for detecting the fuse status of a fuse is provided, such as Figure 1 As shown, the detection circuit for the fuse state includes a bias current generating circuit 100, a current subtractor 200 and a processing module 300; the bias current generating circuit 100 is used to provide an adjustable bias current; the current subtractor 200 has an input end, a first output end and a second output end, the current subtractor 200 is used to generate a fuse state detection current (a bias current of the current comparator in an unwritten state), the fuse state detection current is the difference between the rated current provided by the current subtractor 200 and the bias current, the input end of the current subtractor 200 is electrically connected to the bias current generating circuit 100, the first output end of the current subtractor 200 is used to output a bias voltage, and the second output end of the current subtractor 200 is used to Output the above-mentioned fuse fuse state detection current (bias current of the current comparator in the unwritten state); the processing module 300 has a first input end, a second input end, a first output end and a second output end. The first input end of the above-mentioned processing module 300 is electrically connected to the first output end of the above-mentioned current subtractor 200, and the second input end of the above-mentioned processing module 300 is electrically connected to the second output end of the above-mentioned current subtractor 200. The second output end of the above-mentioned processing module 300 is used to be electrically connected to the fuse under test FU. When the state of the above-mentioned fuse under test FU is a written state, the output end of the above-mentioned processing module 300 outputs a logic high level. When the state of the above-mentioned fuse under test FU is an unwritten state, the output end of the above-mentioned processing module 300 outputs a logic low level.

[0027] In the above circuit, a variable detection current is given to the fuse under test through the bias current generating circuit and the current subtractor. At the same time, when the state of the fuse under test is in the burned state, the output end of the processing module outputs a logic high level. When the state of the fuse under test is in the unburned state, the output end of the processing module outputs a logic low level, thereby better detecting the state of the fuse under test, thereby solving the problem of difficult control of the size of the fuse fuse state detection current in the existing solution.

[0028] According to the actual manufacturing process deviation of the fuse element (i.e., the fuse under test) and taking into account the appropriate fuse burning conditions, the fuse state detection current can be adjusted through the adjustable bias current circuit, so that the fuse state detection circuit can read the fuse burning state within a larger range of changes in the fuse impedance after burning. Under the premise of optimizing power consumption, the redundancy of the readout circuit is increased; the power consumption and yield of the overall circuit are balanced and optimized, and the reliability of the solution is significantly improved, thereby increasing the success rate of the product's first-time material feeding.

[0029] In one embodiment of the present application, Figure 1 As shown, the processing module 300 includes a current comparator 310 and a two-stage inverting circuit 320; the current comparator 310 has a first input terminal, a second input terminal, a first output terminal, a second output terminal and a third output terminal. The first input terminal of the current comparator 310 is electrically connected to the first output terminal of the current subtractor 200, the second input terminal of the current comparator 310 is electrically connected to the second output terminal of the current subtractor 200, and the third output terminal of the current comparator 310 is used to be electrically connected to the fuse under test FU. The current comparator 310 is used to compare the fuse state detection current (the bias current of the current comparator in the unburned state) and the actual fuse current. When the detection current is greater than the actual fuse current, the second output terminal of the current comparator 310 outputs a high level. When the fuse state detection current is greater than the actual fuse current, the second output terminal of the current comparator 310 outputs a high level. When the measured current is less than the saturation current of M10, the second output terminal of the current comparator 310 outputs a low level; the two-stage inverter circuit 320 has a first input terminal, a second input terminal and an output terminal, the first input terminal of the two-stage inverter circuit 320 is electrically connected to the first output terminal of the current comparator 310, and the second input terminal of the two-stage inverter circuit 320 is electrically connected to the second output terminal of the current comparator 310. The two-stage inverter circuit 320 is used to invert the logic level output by the second output terminal of the current comparator 310 twice. When the state of the fuse FU under test is a burned state, the output terminal of the two-stage inverter circuit 320 outputs a more ideal logic high level. When the state of the fuse FU under test is an unburned state, the output terminal of the two-stage inverter circuit 320 outputs a more ideal logic low level.

[0030] The processing module is not limited to the above structure, and can also be implemented by integrating a chip that can realize the above functions.

[0031] The output current of the bias current generation circuit can be estimated using the following formula: Iout = Ids_M5 ≈ Vth_M3 / Rtrim. It can be seen that Iout is almost independent of the power supply voltage Vdd. Ids_M5 is the drain current of M5, and Iout is the current of the port connected to the drain terminal of M5. Vth_M3 specifically refers to M3, the threshold voltage of the NMOS transistor. In the bias current generation circuit, Rtrim is actually composed of weighted resistors connected in series. The weighted resistors (i.e., the first resistor module R1, the second resistor module R2, and the third resistor module R3) are connected in parallel with fuses (the first fuse FU1, the second fuse FU2, and the third fuse FU3), and the fuses are connected in series with each other. By burning the fuses in the bias current generation circuit, Rtrim can be increased, the output current Iout can be reduced, and the fuse state detection current Ib flowing through the current comparator can be increased. When selecting Ib, ensure that: Ib>ΔV / Rfuse_off_min, where Rfuse_off_min is the minimum impedance value of the fuse after burning.

[0032] In the above formula, ΔV is the difference in the Vgs voltage between MN6 and MN10 when the saturation current is Ib. ΔV = Vgs6 - Vgs10, and Rfuse is the resistance of the fuse. When Rfuse > ΔV / Ib, the logic level flips. Ib is the output current of the current subtractor.

[0033] It can be seen that after introducing the bias current generation circuit, the fuse state detection current Ib can be increased within a certain range, thereby adapting to the fluctuation of the fuse impedance after programming within a wider range. Based on the actual manufacturing process deviation of the fuse element and considering the appropriate fuse programming conditions, the final Ib selection can better balance and optimize the design power consumption and yield, and significantly improve the reliability of the solution.

[0034] In one embodiment of the present application, Figure 1As shown, the bias current generating circuit 100 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a current regulator 110. The source of the first transistor M1 and the source of the second transistor M2 are electrically connected to a voltage source Vdd, respectively. The gate of the first transistor M1 is electrically connected to the gate of the second transistor M2, the drain of the second transistor M2, and the drain of the fourth transistor M4, respectively. The drain of the first transistor M1 is electrically connected to the gate of the fourth transistor M4 and the drain of the third transistor M3, respectively. The source of the third transistor M3 and the source of the fifth transistor M5 are grounded, respectively. The gate of the third transistor M3 is electrically connected to the drain of the fourth transistor M4, the current regulator 110, and the gate of the fifth transistor M5, respectively. The drain of the fifth transistor M5 is electrically connected to the input terminal of the current subtractor 200. A bias circuit that is insensitive to power supply voltage and has adjustable output current is implemented in a compact circuit.

[0035] In one embodiment of the present application, Figure 1 As shown, the current regulator 110 includes a first resistor module R1, a second resistor module R2, a third resistor module R3, a first fuse FU1, a second fuse FU2, and a third fuse FU3. The first end of the first resistor module R1 is electrically connected to the gate of the third transistor M3 and the first end of the first fuse FU1, respectively. The second end of the first resistor module R1 is electrically connected to the second end of the first fuse FU1, the first end of the second resistor module R2, and the first end of the second fuse FU2, respectively. The second end of the second resistor module R2 is electrically connected to the second end of the second fuse FU2, the first end of the third resistor module R3, and the first end of the third fuse FU3, respectively. The second end of the third resistor module R3 and the second end of the third fuse FU3 are grounded. By programming FU1, FU2, and FU3, the output of the bias current generating circuit can be adjusted within a wide range.

[0036] In one embodiment of the present application, the resistance of the first resistor module is twice the resistance of the second resistor module, and the resistance of the second resistor module is twice the resistance of the third resistor module.

[0037] In one embodiment of the present application, Figure 1As shown, the bias current generating circuit 100 further includes a fourth resistor module R4. A first end of the fourth resistor module R4 is electrically connected to the gate of the third transistor M3, and a second end of the fourth resistor module R4 is electrically connected to the first end of the first resistor module R1. The fourth resistor module R4 is used to determine a reference current value and also provides short-circuit protection.

[0038] In one embodiment of the present application, Figure 1 As shown, the current subtractor 200 includes a current source IS, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a fifth resistor module R5, and a sixth resistor module R6. The drain of the sixth transistor M6 is electrically connected to the gate of the sixth transistor M6, the gate of the seventh transistor M7, the bias current generating circuit 100, and the current source IS, respectively. The drain of the sixth transistor M6 serves as the input terminal of the current subtractor 200, and the gate of the seventh transistor M7 serves as the second output terminal of the current subtractor 200. The source of the sixth transistor M6 is electrically connected to the first end of the fifth resistor module R5. The source of the seventh transistor M7 is electrically connected to the first end of the sixth resistor module R6. The gate of the eighth transistor M8 serves as the first output end of the current subtractor 200. The gate of the eighth transistor M8 is also electrically connected to the drain of the eighth transistor M8 and the drain of the seventh transistor M7, respectively. The source of the eighth transistor M8 is electrically connected to the voltage source Vdd. The second end of the fifth resistor module R5 and the second end of the sixth resistor module R6 are grounded. This implements the core current comparison function of the processing module in its simplest form.

[0039] In one embodiment of the present application, Figure 1 As shown, the current comparator 310 includes a ninth transistor M9, a tenth transistor M10, and a seventh resistor module R7. The gate of the ninth transistor M9 serves as the first input terminal and the first output terminal of the current comparator 310. The gate of the tenth transistor M10 serves as the second input terminal of the current comparator 310. The drain of the tenth transistor M10 serves as the second output terminal of the current comparator 310. The drain of the tenth transistor M10 is also electrically connected to the drain of the ninth transistor M9. The source of the ninth transistor M9 is electrically connected to the voltage source Vdd. The source of the tenth transistor M10 is electrically connected to the first terminal of the seventh resistor module R7. The second terminal of the seventh resistor module R7 is used to be electrically connected to the fuse under test FU. The core current comparison function of the processing module is implemented in the simplest form.

[0040] The above-mentioned sixth transistor, seventh transistor and tenth transistor match each other, and the ratio of the number of basic units included is 1:1:2 (the ratio of the width-to-length ratio of the device is 1:1:2); the above-mentioned eighth transistor and ninth transistor match each other, and the ratio of the number of basic units included is 1:1 (the ratio of the width-to-length ratio of the device is 1:1).

[0041] In one embodiment of the present application, Figure 1 As shown, the two-stage inverter circuit 320 includes an eleventh transistor M11, a twelfth transistor M12 and an inverter Q1. The gate of the eleventh transistor M11 serves as the first input terminal of the two-stage inverter circuit 320, the gate of the twelfth transistor M12 serves as the second input terminal of the two-stage inverter circuit 320, the output terminal of the inverter Q1 serves as the output terminal of the two-stage inverter circuit 320, the source of the eleventh transistor M11 is electrically connected to the voltage source Vdd, the drain of the eleventh transistor M11 is electrically connected to the drain of the twelfth transistor M12 and the input terminal of the inverter Q1, and the source of the twelfth transistor M12 is grounded.

[0042] In one embodiment of the present application, Figure 1 As shown, the detection circuit for the fuse status further includes a first enabling power switch 400 and a second enabling power switch 500. The first enabling power switch 400 is electrically connected between the second output terminal of the current comparator 310 and the gate of the twelfth transistor M12, and the second enabling power switch 500 is electrically connected between the drain of the twelfth transistor M12 and the input terminal of the inverter.

[0043] like Figure 2 and Figure 3 The figure shows the connection between the ground pad (pad) and the fuse pad. Multiple fuses can be connected in series or all fuses can be grounded. The pad is used to apply a high pulse voltage or current externally, causing physical and chemical changes in the fuse, which increases the fuse resistance sharply and ultimately "blows" the fuse.

[0044] It should be noted that the above electrical connection can be a direct electrical connection or an indirect electrical connection. Direct electrical connection means that two devices are directly connected, and indirect electrical connection means that other devices such as capacitors and resistors are connected between the connected A and B.

[0045] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0046] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0047] 1) The fuse state detection circuit of the present application provides a variable detection current to the fuse under test through a bias current generating circuit and a current subtractor. At the same time, when the state of the above-mentioned fuse under test is in a burned state, the output end of the processing module outputs a logic high level. When the state of the above-mentioned fuse under test is in an unburned state, the output end of the processing module outputs a logic low level, thereby better detecting the state of the fuse under test, thereby solving the problem of difficult control of the size of the fuse state detection current in the existing solution.

[0048] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A circuit for detecting the fuse status of a fuse, characterized in that: include: A bias current generating circuit for providing an adjustable bias current; a current subtractor having an input end, a first output end, and a second output end, the current subtractor being used to generate a fuse state detection current, the fuse state detection current being the difference between a rated current provided by the current subtractor and the bias current, the input end of the current subtractor being electrically connected to the bias current generating circuit, the first output end of the current subtractor being used to output a bias voltage, and the second output end of the current subtractor being used to output the fuse state detection current; A processing module has a first input end, a second input end, a first output end, and a second output end. The first input end of the processing module is electrically connected to the first output end of the current subtractor, the second input end of the processing module is electrically connected to the second output end of the current subtractor, and the second output end of the processing module is used to be electrically connected to the fuse under test. When the state of the fuse under test is a burned state, the output end of the processing module outputs a logic high level; when the state of the fuse under test is an unburned state, the output end of the processing module outputs a logic low level.

2. The fuse status detection circuit according to claim 1, characterized in that: The processing module includes: a current comparator having a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a third output terminal, wherein the first input terminal of the current comparator is electrically connected to the first output terminal of the current subtractor, the second input terminal of the current comparator is electrically connected to the second output terminal of the current subtractor, and the third output terminal of the current comparator is used to be electrically connected to the fuse under test, and the current comparator is used to output a high level at the second output terminal of the current comparator when the fuse state detection current is greater than the actual fuse current, and output a low level at the second output terminal of the current comparator when the fuse state detection current is less than the saturation pull-down current; A two-stage inverter circuit has a first input terminal, a second input terminal and an output terminal, the first input terminal of the two-stage inverter circuit is electrically connected to the first output terminal of the current comparator, and the second input terminal of the two-stage inverter circuit is electrically connected to the second output terminal of the current comparator. The two-stage inverter circuit is used to invert the logic level output by the second output terminal of the current comparator twice. When the state of the fuse under test is a burned state, the output terminal of the two-stage inverter circuit outputs a logic high level. When the state of the fuse under test is an unburned state, the output terminal of the two-stage inverter circuit outputs a logic low level.

3. The fuse status detection circuit according to claim 1, characterized in that: The bias current generating circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a current regulator. The source of the first transistor and the source of the second transistor are electrically connected to a voltage source, respectively. The gate of the first transistor is electrically connected to the gate of the second transistor, the drain of the second transistor, and the drain of the fourth transistor, respectively. The drain of the first transistor is electrically connected to the gate of the fourth transistor and the drain of the third transistor, respectively. The source of the third transistor and the source of the fifth transistor are grounded, respectively. The gate of the third transistor is electrically connected to the drain of the fourth transistor, the current regulator, and the gate of the fifth transistor, respectively. The drain of the fifth transistor is electrically connected to the input terminal of the current subtractor.

4. The fuse status detection circuit according to claim 3, characterized in that: The current regulator includes a first resistance module, a second resistance module, a third resistance module, a first fuse, a second fuse and a third fuse, the first end of the first resistance module is electrically connected to the gate of the third transistor and the first end of the first fuse, respectively, the second end of the first resistance module is electrically connected to the second end of the first fuse, the first end of the second resistance module and the first end of the second fuse, respectively, the second end of the second resistance module is electrically connected to the second end of the second fuse, the first end of the third resistance module and the first end of the third fuse, respectively, the second end of the third resistance module and the second end of the third fuse are grounded, respectively.

5. The fuse status detection circuit according to claim 4, characterized in that: The resistance of the first resistance module is twice the resistance of the second resistance module, and the resistance of the second resistance module is twice the resistance of the third resistance module.

6. The circuit for detecting the fuse status of a fuse according to claim 4, wherein: The bias current generating circuit further includes a fourth resistance module, a first end of the fourth resistance module is electrically connected to the gate of the third transistor, and a second end of the fourth resistance module is electrically connected to the first end of the first resistance module.

7. The fuse status detection circuit according to claim 1, characterized in that: The current subtractor includes a current source, a sixth transistor, a seventh transistor, an eighth transistor, a fifth resistor module, and a sixth resistor module. The drain of the sixth transistor is electrically connected to the gate of the sixth transistor, the gate of the seventh transistor, the bias current generating circuit, and the current source, respectively. The drain of the sixth transistor serves as the input end of the current subtractor, and the gate of the seventh transistor serves as the second output end of the current subtractor. The source of the sixth transistor is electrically connected to the first end of the fifth resistor module, the source of the seventh transistor is electrically connected to the first end of the sixth resistor module, and the gate of the eighth transistor serves as the first output end of the current subtractor. The gate of the eighth transistor is also electrically connected to the drain of the eighth transistor and the drain of the seventh transistor, respectively. The source of the eighth transistor is electrically connected to a voltage source. The second end of the fifth resistor module and the second end of the sixth resistor module are grounded, respectively.

8. The fuse status detection circuit according to claim 2, characterized in that: The current comparator includes a ninth transistor, a tenth transistor and a seventh resistance module, the gate of the ninth transistor serves as the first input terminal and the first output terminal of the current comparator, the gate of the tenth transistor serves as the second input terminal of the current comparator, the drain of the tenth transistor serves as the second output terminal of the current comparator, the drain of the tenth transistor is also electrically connected to the drain of the ninth transistor, the source of the ninth transistor is electrically connected to a voltage source, the source of the tenth transistor is electrically connected to the first end of the seventh resistance module, and the second end of the seventh resistance module is used to be electrically connected to the fuse under test.

9. The fuse status detection circuit according to claim 2, characterized in that: The two-stage inverter circuit includes an eleventh transistor, a twelfth transistor and an inverter, the gate of the eleventh transistor serves as the first input terminal of the two-stage inverter circuit, the gate of the twelfth transistor serves as the second input terminal of the two-stage inverter circuit, the output terminal of the inverter serves as the output terminal of the two-stage inverter circuit, the source of the eleventh transistor is electrically connected to a voltage source, the drain of the eleventh transistor is electrically connected to the drain of the twelfth transistor and the input terminal of the inverter, respectively, and the source of the twelfth transistor is grounded.

10. The fuse state detection circuit according to claim 9, characterized in that: The detection circuit for the fuse fuse state also includes a first enabling power switch and a second enabling power switch, wherein the first enabling power switch is electrically connected between the second output terminal of the current comparator and the gate of the twelfth transistor, and the second enabling power switch is electrically connected between the drain of the twelfth transistor and the input terminal of the inverter.

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