Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, including a substrate and a bottom fin material layer on the substrate, the substrate including a first device region and a second device region; forming a first fin material layer on the bottom fin material layer, the material of the first fin material layer being different from the material of the bottom fin material layer; removing the first fin material layer located at the second device region to form an opening exposing a top of the bottom fin material layer; forming a second fin material layer in the opening; and performing a fin patterning process to pattern the bottom fin material layer into a bottom fin, the first fin material layer into a first device fin standing on the bottom fin of the first device region, and the second fin material layer into a second device fin standing on the bottom fin of the second device region. The formed second device fin and the contact surface of the first device fin with the bottom fin are both relatively flat, improving the height consistency of the second device fin and the first device fin.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Transistors, as one of the basic semiconductor devices, are currently widely used. Therefore, as the density and integration of semiconductor devices increase, the gate size of planar transistors is becoming shorter and shorter. The ability of traditional planar transistors to control channel current weakens, resulting in short-channel effects, which increase leakage current and ultimately affect the electrical performance of semiconductor devices.

[0003] To better adapt to the shrinking feature size, semiconductor processes have gradually transitioned from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. However, with further reductions in feature size, it is difficult to further improve the performance of FinFETs. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the working performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, including a base plate, the substrate including a first device region for forming a first transistor and a second device region for forming a second transistor; and a fin protruding from the substrate, the fin comprising a bottom fin protruding from the substrate and a device fin located on the bottom fin, the device fin comprising a first device fin located in the first device region and a second device fin located in the second device region, wherein the contact surfaces of the device fin and the bottom fin are both planar, and the materials of the first device fin and the bottom fin are different.

[0006] Accordingly, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate and a bottom fin material layer located on the substrate, the substrate including a first device region for forming a first transistor and a second device region adjacent to the first device region for forming a second transistor; forming a first fin material layer on the bottom fin material layer, the material of the first fin material layer being different from the material of the bottom fin material layer; removing the first fin material layer located in the second device region, retaining the first fin material layer located in the first device region, forming an opening exposing the top of the bottom fin material layer; forming a second fin material layer in the opening; performing fin patterning processing, patterning the first fin material layer, the second fin material layer, and the bottom fin material layer, patterning the bottom fin material layer as bottom fins protruding from the substrates of the first device region and the second device region respectively, patterning the first fin material layer as a first device fin protruding from the bottom fin of the first device region, and patterning the second fin material layer as a second device fin protruding from the bottom fin of the second device region.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the semiconductor structure provided by this invention, the contact surfaces of the device fins and the bottom fins are both planar. This results in relatively smooth contact surfaces between the device fins and the bottom fins, which improves the height consistency of the first and second device fins. Consequently, it improves the uniformity of the height of the effective fins of the first and second transistors, thereby helping to ensure the working performance of the semiconductor structure. At the same time, since the device fins protrude from the bottom fins, it is easy to flexibly select the materials for the first and second device fins. This allows the first and second device fins to be used to meet the performance requirements of the first and second transistors respectively, thereby improving the performance of different transistors and further enhancing the working performance of the semiconductor structure.

[0009] In the forming method provided by this embodiment of the invention, the material of the first fin material layer is different from the material of the bottom fin material layer. Therefore, during the removal of the first fin material layer located in the second device region, the top surface of the bottom fin material layer can be used as the etching stop surface, resulting in a higher verticality of the sidewalls of the opening. This improves the flatness of the bottom surface of the remaining first fin material layer in the first device region. Correspondingly, the sidewalls of the second fin material layer formed in the opening have a higher verticality, and the bottom surface of the second fin material layer also has a higher flatness. Therefore, after fin patterning, the formed second device fin and the contact surfaces between the first device fin and the bottom fin are relatively flat, thereby improving the flatness of both the second device fin and the first device fin. The high uniformity of the fin height of the first and second transistors is improved accordingly. Moreover, by using the top surface of the bottom fin material layer as the etching stop surface, the depth of the openings in different regions is more consistent, resulting in better height consistency of the second fin material layer formed in the openings. This further improves the height consistency of the formed second device fin, which helps to ensure the working performance of the semiconductor structure. At the same time, the embodiments of the present invention allow for flexible selection of the materials of the first and second device fins, so that the first and second device fins can be used to meet the performance requirements of the first and second transistors respectively, thereby improving the performance of different transistors and further enhancing the working performance of the semiconductor structure. Attached Figure Description

[0010] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0011] Figure 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0012] Figures 6 to 21 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons for this need to improve performance using a semiconductor structure formation method as an example.

[0014] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1A substrate (not shown) is provided, including a substrate 10 and a first fin material layer 11 located on the substrate 10. The substrate 10 and the first fin material layer 11 are integral structures. The substrate includes a first device region 10N for forming a first transistor and a second device region 10P adjacent to the first device region 10N for forming a second transistor.

[0016] The substrate 10 and the first fin material layer 11 are typically formed in the same process, and the substrate 10 and the first fin material layer 11 are made of the same material and are an integral structure.

[0017] refer to Figure 2 Remove the first fin material layer 11 located in the second device region 10P to form an opening 23.

[0018] Since the substrate 10 and the first fin material layer 11 are made of the same material and are an integral structure, the etching rates of the top and sides of the etching opening 23 are relatively consistent. Therefore, a rounded corner morphology is easily formed at the junction of the bottom surface and the sidewall of the opening 23 (e.g., Figure 2 As shown by the dashed circle in the middle, this results in poor verticality of the sidewalls of opening 23 and poor flatness of the bottom surface of opening 23. Moreover, during the formation of opening 23, it is difficult to uniformly remove the thickness of the first fin material layer 11 in each of the second device regions 10P, resulting in uneven depth dimensions of opening 23 (e.g., ...). Figure 2 As shown in the dashed box, the bottom of the opening 23 of the different second device regions 10P has a height difference.

[0019] refer to Figure 3 A second fin material layer 12 is formed in the opening 23.

[0020] Because the sidewall verticality and bottom flatness of the opening 23 are poor, the sidewall verticality and bottom flatness of the formed second fin material layer 12 are also poor. Moreover, the depth dimension of the opening 23 is not uniform, which leads to the thickness dimension of the second fin material layer 12 being not uniform.

[0021] refer to Figure 4 The first fin material layer 11, the second fin material layer 12, and a partially thick substrate 10 are patterned. The partially thick substrate 10 is patterned as a bottom fin 20 protruding from the remaining substrate 10. The first fin material layer 11 is patterned as a first device fin 21 protruding from the bottom fin 20 in the first device region 10P. The second fin material layer 12 is patterned as a second device fin 22 protruding from the bottom fin 20 in the second device region 10N.

[0022] Because the sidewall verticality and bottom surface flatness of the second fin material layer 12 are also poor, the bottom of the formed second device fin 22 has an arc-shaped morphology (e.g., Figure 4(As shown by the dashed coil in the middle), that is to say, the flatness of the contact surface between the second device fin 22 and the bottom fin 20 is poor, which can easily lead to poor uniformity of the effective fin height of the second transistor and affect the performance of the semiconductor structure.

[0023] To address the aforementioned technical problem, this invention provides a method for forming a semiconductor structure. In this embodiment, the material of the first fin material layer is different from that of the bottom fin material layer. Therefore, during the removal of the first fin material layer located in the second device region, the top surface of the bottom fin material layer can be used as the etching stop surface, resulting in a higher verticality of the sidewalls of the opening. This improves the flatness of the bottom surface of the remaining first fin material layer in the first device region. Correspondingly, the sidewalls of the second fin material layer formed in the opening also have higher verticality, and the bottom surface of the second fin material layer is also flatter. Therefore, after fin patterning, the formed second device fin and the contact surfaces between the first device fin and the bottom fin are relatively flat, thereby improving the flatness of the second device fin. The height consistency between the first device fin and the second device fin improves the uniformity of the effective fin height of the first transistor and the second transistor. Furthermore, using the top surface of the bottom fin material layer as the etching stop surface ensures better consistency in the depth of the openings in different regions, resulting in better height consistency of the second fin material layer formed in the openings. This further improves the height consistency of the formed second device fin, which helps to ensure the working performance of the semiconductor structure. At the same time, the embodiments of the present invention allow for flexible selection of the materials of the first device fin and the second device fin, enabling the first device fin and the second device fin to be used to meet the performance requirements of the first transistor and the second transistor respectively, thereby improving the performance of different transistors and further enhancing the working performance of the semiconductor structure.

[0024] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0025] Figure 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0026] The semiconductor structure includes: a substrate (not shown), including a substrate 101, the substrate 101 including a first device region 101P for forming a first transistor and a second device region 101N for forming a second transistor; and a fin (not shown), protruding from the substrate 101, the fin including a bottom fin 601 protruding from the substrate 101 and a device fin 631 located on the bottom fin 601, the device fin 631 including a first device fin 611 located in the first device 101P region and a second device fin 621 located in the second device region 101N, the contact surfaces of the device fin 631 and the bottom fin 601 are both planar, and the materials of the first device fin 611 and the bottom fin 601 are different.

[0027] The substrate provides the basis for the process operations of forming the semiconductor structure. The semiconductor structure includes a FinFET (Fin Field-Effect Transistor).

[0028] In this embodiment, the substrate 101 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the substrate 101 may be suitable for process requirements or easy to integrate.

[0029] In this embodiment, the substrate 101 includes a first device region 101P for forming a first transistor and a second device region 101N for forming a second transistor. The first transistor and the second transistor have different channel conductivity types, including N-type and P-type. As an example, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

[0030] In this embodiment, the substrate further includes: an etch stop layer 111 located on the substrate 101; and a bottom fin 601 protruding from the etch stop layer 111.

[0031] Typically, the steps of forming the bottom fin 601 and the device fin 631 include: forming a bottom fin material layer (not shown), a first fin material layer (not shown), and a second fin material layer (not shown) on the substrate 101; performing fin patterning processing to pattern the first fin material layer, the second fin material layer, and the bottom fin material layer, patterning the bottom fin material layer into a bottom fin 601 protruding from the substrate 101 of the first device region 101P and the second device region 101N respectively, patterning the first fin material layer into a first device fin 611 protruding from the bottom fin 601 of the first device region 101P, and patterning the second fin material layer into a second device fin 621 protruding from the bottom fin 601 of the second device region 101N.

[0032] The etch stop layer 111 is used as the stop position for etching the bottom fin material layer during fin patterning. Therefore, after fin patterning, the top surface of the etch stop layer 110 has a high flatness, and the total height of the first device fin 611 and the bottom fin 601, as well as the total height of the second device fin 621 and the bottom fin 601, are relatively uniform. This is beneficial to the uniformity of the effective fin height of the first transistor and the second transistor, thereby improving the performance of the semiconductor structure.

[0033] In this embodiment, the etch stop layer 111 is made of phosphorus-doped silicon, arsenic-doped silicon, carbon-doped silicon, or boron-doped silicon. In this embodiment, the etch stop layer 111 is formed by ion implantation of the substrate 101, with implanted ions including phosphorus, arsenic, carbon, or boron. Therefore, the material of the etch stop layer 111 includes phosphorus-doped silicon, arsenic-doped silicon, carbon-doped silicon, or boron-doped silicon. Furthermore, the phosphorus-doped silicon, arsenic-doped silicon, carbon-doped silicon, or boron-doped silicon has high hardness and can form a large etch selectivity ratio with the material of the bottom fin 601, thereby achieving a better etch stop effect. In other embodiments, depending on the actual situation, the semiconductor structure may not contain the etch stop layer.

[0034] In this embodiment, the material of the bottom fin 601 includes silicon, germanium, silicon germanide, or a group III-V semiconductor material. As an example, the material of the bottom fin 601 is the same as the material of the substrate 101, which is silicon, and the material of the bottom fin 601 is also silicon.

[0035] Device fin 631 is used to provide the channel of fin field-effect transistor, wherein the first device fin 611 and the second device fin 621 are used to provide the channels of the first transistor and the second transistor, respectively.

[0036] Specifically, the first device fin 611 includes a first middle fin (not shown) and a first top fin (not shown), and the second device fin 621 includes a second middle fin (not shown) and a second top fin (not shown). The first middle fin and the first top fin together serve as the channel of the first transistor. The first middle fin includes a sidewall, and the first top fin includes a sidewall and an arc-shaped top surface. Therefore, the first middle fin and the first top fin provide different channel stresses for the first transistor. Correspondingly, the second middle fin and the second top fin together serve as the channel of the second transistor. The second middle fin includes a sidewall, and the second top fin includes a sidewall and an arc-shaped top surface. Therefore, the second middle fin and the second top fin provide different channel stresses for the second transistor.

[0037] In this embodiment, the contact surfaces of the device fin 631 and the bottom fin 601 are both planar. This results in a relatively smooth contact surface, improving the height consistency of the first device fin 611 and the second device fin 621. Consequently, it enhances the uniformity of the effective fin height of the first transistor and the second transistor, thus helping to ensure the working performance of the semiconductor structure. Furthermore, since the device fin 631 protrudes from the bottom fin 601, it is easy to flexibly select the materials for the first device fin 611 and the second device fin 621. This allows the first device fin 611 and the second device fin 621 to be used respectively to meet the performance requirements of the first transistor and the second transistor, thereby improving the performance of different transistors and further enhancing the working performance of the semiconductor structure.

[0038] Specifically, in this embodiment, the steps of forming the first fin material layer and the second fin material layer include: forming the first fin material layer on the bottom fin material layer; removing the first fin material layer located in the second device region 101N, retaining the first fin material layer located in the first device region 101P, forming an opening (not shown) exposing the top of the bottom fin material layer; and forming the second fin material layer in the opening. In this embodiment, the first device fin 611 and the bottom fin 601 are made of different materials. Therefore, the first fin material layer and the bottom fin material layer can have a large etching selectivity ratio. Thus, during the formation of the opening, the bottom fin material layer can be used as the etching stop layer to etch the first fin material layer, resulting in better sidewall verticality and bottom surface flatness of the opening. At the same time, the bottom surface flatness of the remaining first fin material layer in the first device region 101P is improved. Correspondingly, after the second fin material layer is formed in the opening, the sidewall verticality and bottom surface flatness of the second fin material layer are better. Thus, after fin patterning, the contact surface between the device fin 631 and the bottom fin 601 is relatively flat.

[0039] In this embodiment, the material of the first device fin 611 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials; the material of the second device fin 621 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.

[0040] In this embodiment, the material of the first device fin 611 is different from the material of the second device fin 621. That is, the channel materials of the first transistor and the second transistor are different. Specifically, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor. Therefore, in this embodiment, the material of the first device fin 611 is silicon germanide, and the material of the second device fin 621 is silicon. By using silicon germanide for the device fins of the PMOS transistor, the channel mobility of the PMOS transistor is improved. At the same time, it helps to improve the negative bias temperature instability (NBTI) problem of the PMOS transistor, thereby improving the performance of the PMOS transistor.

[0041] Therefore, in this embodiment, the material of the bottom fin 601 is the same as the material of the second device fin 621. Furthermore, the second fin material layer is typically formed in the opening using an epitaxial growth process, with the bottom of the opening being the bottom fin material layer. Thus, the fact that the material of the bottom fin 601 is the same as the material of the second device fin 621 is beneficial for the growth of the second fin material layer, resulting in a higher quality second device fin 621. In other embodiments, depending on process requirements, the material of the bottom fin may also be different from the material of the second device fin.

[0042] In this embodiment, the semiconductor structure further includes an isolation layer 121, which is located on the etch stop layer 111 and covers the sidewalls of the bottom fin 601. The isolation layer 121 serves as a shallow trench isolation (STI) structure to isolate adjacent transistors. In this embodiment, the isolation layer 121 covers the sidewalls of the bottom fin 601, thereby enabling the first transistor to use only the first device fin 611 as a trench and the second transistor to use only the second device fin 621 as a channel.

[0043] In this embodiment, the portion of the device fin 631 exposed above the isolation layer 121 is designated as an effective fin. That is, the portion of the device fin 631 exposed above the isolation layer 121 is used to be covered by the device gate structure. Depending on actual needs, the top of the isolation layer 121 is higher than or flush with the bottom of the first device fin 611 and the second device fin 621. In other words, the isolation layer 121 exposes the entire or part of the sidewalls of the first device fin 611 and the second device fin 621. As an example, Figure 5 The top of the isolation layer 121 is shown to be flush with the bottom of the first device fin 611 and the second device fin 621.

[0044] In this embodiment, the material of the isolation layer 121 is silicon oxide. In other embodiments, the material of the isolation layer may also be other insulating materials such as silicon nitride or silicon oxynitride.

[0045] Figures 6 to 21 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0046] Reference Figures 6 to 9 A substrate (not shown) is provided, the substrate including a substrate 100 and a bottom fin material layer 200 located on the substrate 100, the substrate 100 including a first device region 100P for forming a first transistor, and a second device region 100N adjacent to the first device region 100P for forming a second transistor.

[0047] The substrate provides the basis for the process operation of forming the semiconductor structure. The semiconductor structure includes a finned field-effect transistor.

[0048] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the substrate 100 may be suitable for process requirements or easy to integrate.

[0049] In this embodiment, the substrate 100 includes a first device region 100P for forming a first transistor and a second device region 100N for forming a second transistor. The first transistor and the second transistor have different channel conductivity types, including N-type and P-type. As an example, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

[0050] The bottom fin material layer 200 is used for subsequent formation of the bottom fins. When the first fin material layer located in the second device region 100N is subsequently removed, the bottom fin material layer 200 also serves as an etching stop layer. In this embodiment, the material of the bottom fin material layer 200 includes silicon, germanium, silicon germanide, or a group III-V semiconductor material. As an example, the material of the bottom fin material layer 200 is the same as the material of the substrate 100, which is silicon, and the material of the bottom fin material layer 200 is also silicon.

[0051] In this embodiment, during the step of providing the substrate, the substrate further includes an etch stop layer 110 located between the substrate 100 and the bottom fin material layer 200.

[0052] Typically, subsequent processes also include: forming a first fin material layer on the bottom fin material layer 200 of the first device region 100P, forming a second fin material layer on the bottom fin material layer 200 of the second device region 100N; performing fin patterning processing to pattern the first fin material layer, the second fin material layer, and the bottom fin material layer 200, patterning the bottom fin material layer 200 as bottom fins protruding from the substrates 100 of the first device region 100P and the second device region 100N respectively, patterning the first fin material layer as a first device fin protruding from the bottom fin of the first device region 100P, and patterning the second fin material layer as a second device fin protruding from the bottom fin of the second device region 100N.

[0053] The etch stop layer 110 is used as the stop position for etching the bottom fin material layer 200 during fin patterning. Therefore, after fin patterning, the top surface of the etch stop layer 110 has high flatness, and the total height of the first device fin and the bottom fin, as well as the total height of the second device fin and the bottom fin, are relatively uniform. This is beneficial to making the effective fin height of the first transistor and the second transistor more uniform, thereby improving the performance of the semiconductor structure.

[0054] Specifically, refer to Figure 6 The step of providing the substrate includes: providing a substrate 100; and referring to a reference. Figure 7 and Figure 8 The surface of the substrate 100 is modified to transform the top portion of the substrate 100 into an etch stop layer 110.

[0055] In this embodiment, in the step of modifying the surface of the substrate 100, an ion implantation process is used to convert the top portion of the substrate 100 into an etch stop layer.

[0056] The ion implantation process features uniform, large-area ion implantation, more accurate control of ion doping depth, and high repeatability. In this embodiment, the ion implantation process can effectively control the thickness of the formed etch stop layer 110 and the uniformity of its surface.

[0057] In this embodiment, the implanted ions in the ion implantation process include boron ions, carbon ions, arsenic ions, or phosphorus ions. Implanting boron ions, carbon ions, arsenic ions, or phosphorus ions can form a hard etch stop layer 110, and create a large etch selectivity ratio between the etch stop layer 110 and the material of the bottom fin material layer 200, thereby achieving a better etch stop effect. Therefore, in this embodiment, the material of the etch stop layer 110 includes phosphorus-doped silicon, arsenic-doped silicon, carbon-doped silicon, or boron-doped silicon.

[0058] It should be noted that the implantation energy in the ion implantation process should not be too high or too low. If the implantation energy is too high, the ion implantation area will be too large, making the process difficult to control and resulting in an excessively thick etch stop layer 110. If the implantation energy is too low, the ion implantation reaction time will be too long, reducing the efficiency of the process and affecting the thickness of the etch stop layer 110, thus failing to achieve the desired process effect. Therefore, in this embodiment, the implantation energy ranges from 1 keV to 600 keV.

[0059] It should also be noted that the implantation dose in the ion implantation process should not be too large or too small. If the implantation dose is too large, the ion implantation range will be too large, making the process difficult to control, and consequently, the thickness of the etch stop layer 110 will be too large. If the implantation dose is too small, the ion implantation reaction time will be too long, reducing the efficiency of the process, affecting the thickness of the etch stop layer 110, failing to achieve the desired process effect, and easily causing the etch stop layer 110 to have an etch rate close to that of the substrate 100, making it difficult to form the etch stop surface of the bottom fin material layer 200 during subsequent fin patterning. Therefore, in this embodiment, the implantation dose range is 1×10⁻⁶. 12 ions / cm 2 Up to 2×10 18 ions / cm 2 Among them, ions / cm 2 This refers to the number of ions per square centimeter.

[0060] refer to Figure 9 A bottom fin material layer 200 is formed on the etching stop layer 110.

[0061] In this embodiment, an epitaxial growth process is used to form the bottom fin material layer 200 on the substrate 100. The epitaxial growth process allows for better control of process parameters, has high process controllability, and easily obtains precise film thickness dimensions. Furthermore, the epitaxial growth process readily forms a film layer with fewer impurities, resulting in a high-quality bottom fin material layer 200.

[0062] In this embodiment, after the etching stop layer 110 is formed, a bottom fin material layer 200 is formed on the etching stop layer 110.

[0063] It should be noted that in this embodiment, the etch stop layer 200 is formed by ion implantation of the substrate 100. Compared with depositing a new film layer on the substrate as an etch stop layer, the material of the etch stop layer 110 after it is formed in this embodiment is a semiconductor material doped with ions. This is beneficial for the epitaxial growth of the bottom fin material layer 200 on the surface of the etch stop layer 110, resulting in a bottom fin material layer 200 with higher film quality.

[0064] It should also be noted that in this embodiment, the substrate 100 is first ion implanted to form an etch stop layer 110, and then the bottom fin material layer 200 is epitaxially grown. Compared with the scheme of forming an integral structure of the substrate and the bottom fin material layer, and then implanting ions to a certain depth to form an etch stop layer in the substrate, this embodiment performs ion implantation before forming the bottom fin material layer 200. This is beneficial to reduce or avoid the impact of the ion implantation process on the bottom fin material layer 200, ensuring the formation quality of the bottom fin material layer 200. Moreover, it is beneficial to accurately control the doping concentration of ions in the etch stop layer 110, the thickness of the etch stop layer 110, and the formation position of the etch stop layer 110.

[0065] In this embodiment, after forming the bottom fin material layer 200 on the substrate 100 using an epitaxial growth process, the method further includes: planarizing the top surface of the bottom fin material layer 200.

[0066] Compared to directly forming the bottom fin material layer 200 of the target thickness, this embodiment performs planarization treatment on the bottom fin material layer 200 after epitaxial growth. This is beneficial for more precise control of the thickness of the bottom fin material layer 200. Furthermore, the planarization treatment improves the flatness of the top surface of the bottom fin material layer 200, which is beneficial for improving the height consistency of the subsequently formed bottom fin.

[0067] In other embodiments, the bottom fin material layer and the substrate can be an integral structure, that is, the substrate and the bottom fin material layer can be formed in the same process, and then ions can be implanted to a certain depth to perform ion implantation on the substrate to form an etching stop layer on the top of the substrate.

[0068] refer to Figure 10 A first fin material layer 210 is formed on the bottom fin material layer 200, and the material of the first fin material layer 210 is different from the material of the bottom fin material layer 200.

[0069] The first fin material layer 210 is used to subsequently form the first device fin.

[0070] In this embodiment of the invention, it is further necessary to remove the first fin material layer 210 located in the second device region 100N to form an opening exposing the top of the bottom fin material layer 200. A second fin material layer is then formed within this opening. The first fin material layer 210, the second fin material layer, and the bottom fin material layer 200 are patterned. Since the material of the first fin material layer 210 is different from that of the bottom fin material layer 200, during the removal of the first fin material layer 210 located in the second device region 100N, the top surface of the bottom fin material layer 200 can be used as the etching stop surface. This results in a higher verticality of the sidewalls of the opening, reducing the probability of arc-shaped morphology at the corners of the opening. This improves the flatness of the bottom surface of the remaining first fin material layer 210 in the first device region 100P. Consequently, the sidewalls of the second fin material layer formed in the opening have a higher verticality, and the bottom surface of the second fin material layer also has a higher flatness. Therefore, during the fin patterning process... After the etching process, the contact surfaces between the formed second device fin and the first device fin and the bottom fin are relatively flat, thereby improving the height consistency of the second device fin and the first device fin. This correspondingly improves the uniformity of the effective fin height of the first transistor and the second transistor. Moreover, using the top surface of the bottom fin material layer 200 as the etching stop surface, the depth consistency of the openings in different regions is better, resulting in better height consistency of the second fin material layer formed in the openings. This further improves the height consistency of the formed second device fin, which is beneficial to ensuring the working performance of the semiconductor structure. At the same time, this embodiment allows for flexible selection of the materials for the first device fin and the second device fin, enabling the first device fin and the second device fin to be used to meet the performance requirements of the first transistor and the second transistor, respectively, thereby improving the performance of different transistors and further enhancing the working performance of the semiconductor structure.

[0071] In this embodiment, the first fin material layer 210 is formed by an epitaxial growth process.

[0072] The epitaxial growth process can better control the process parameters, has high process controllability, and is easy to obtain a more accurate film thickness. In addition, the epitaxial growth process is easy to form a film with fewer impurities, resulting in a higher quality of the first fin material layer 210.

[0073] In this embodiment, after forming the first fin material layer 210 using an epitaxial growth process, the method further includes: planarizing the top surface of the first fin material layer 210.

[0074] Compared to directly forming the first fin material layer 210 of the target thickness, this embodiment performs planarization treatment on the first fin material layer 210 after epitaxial growth. This is beneficial for accurately controlling the thickness of the first fin material layer 210. Furthermore, the planarization treatment improves the flatness of the top surface of the first fin material layer 210, which is beneficial for improving the height consistency of the first device fins formed subsequently.

[0075] In this embodiment, the material of the first fin material layer 210 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.

[0076] In this embodiment, the first transistor is a PMOS transistor. Therefore, the material of the first fin material layer 210 is silicon germanide, and thus the material of the subsequently formed first device fin is also silicon germanide. By using silicon germanide for the device fin of the PMOS transistor, the channel mobility of the PMOS transistor is improved. At the same time, it helps to improve the negative bias temperature instability problem of the PMOS transistor, thereby improving the performance of the PMOS transistor.

[0077] Reference Figures 11 to 13 Remove the first fin material layer 210 located in the second device region 100N to form an opening 230 that exposes the top of the bottom fin material layer 200.

[0078] The opening 230 is used to provide space for the subsequent formation of the second fin material layer.

[0079] In this embodiment, a dry etching process is used to remove the first fin material layer 210 located in the second device region 100N. The dry etching process is an anisotropic etching process, which helps to reduce damage to the bottom fin material layer 200. At the same time, the dry etching process is more directional, which can improve the sidewall morphology quality and dimensional accuracy of the opening 230.

[0080] Specifically, the first fin material layer 210 is etched with the top of the bottom fin material layer 200 as the etching stop position.

[0081] Specifically, in conjunction with reference Figure 11 and Figure 12 The step of removing the first fin material layer 210 located in the second device region 100N includes: forming a first mask layer 310 on the first fin material layer 210.

[0082] The first mask layer 310 is used as an etching mask to remove the first fin material layer 210 located in the second device region 100N.

[0083] Specifically, refer to Figure 11A pattern transfer layer 300 is also formed on the first mask layer 310.

[0084] The graphics transfer layer 300 is used as a mask for the graphics first mask layer 310.

[0085] In this embodiment, the pattern transfer layer 300 is a stacked structure, and the pattern transfer layer 300 includes a planarization layer 320, an anti-reflection coating 330 on the planarization layer 320, and a photoresist layer 340 on the anti-reflection coating 330.

[0086] The photoresist layer 340 has a pattern transfer opening 350, through which the anti-reflective coating 330 and planarization layer 320 are sequentially etched to transfer the pattern to the first mask layer 310.

[0087] In this embodiment, the planarization layer 320 is made of spin-on carbon (SOC). Spin-on carbon is formed by a spin coating process, which has a low processing cost. Moreover, by using spin-on carbon, the flatness of the top surface of the planarization layer 320 is improved, thereby providing a good interface for the process of transferring patterns. In this embodiment, the anti-reflective layer 330 is made of Si-ARC (silicon-containing anti-reflective coating).

[0088] refer to Figure 12 The first mask layer 310 is patterned, and a mask opening 370 is formed in the first mask layer 310. The mask opening 370 exposes the first fin material layer 210 of the second device region 100N in preparation for removing the first fin material layer 210 located in the second device region 100N.

[0089] Specifically, using the photoresist layer 340 as a mask, the anti-reflective coating 330 and planarization layer 320 at the bottom of the pattern transfer opening 350 are etched sequentially. Then, using the remaining pattern transfer layer 300 as a mask, the first mask layer 310 is etched to form a mask opening 370 in the first mask layer 310.

[0090] In this embodiment, after forming the mask opening 370 in the first mask layer 310, the method further includes: removing the remaining pattern transfer layer 300.

[0091] refer to Figure 13 The first fin material layer 210 located in the second device region 100N is removed along the mask opening 370 to form an opening 230 that exposes the top of the bottom fin material layer 200, which helps to improve the dimensional accuracy and morphological quality of the formed opening 230.

[0092] In this embodiment, after the opening 230 is formed, the first mask layer 310 is removed.

[0093] refer to Figure 14 A second fin material layer 220 is formed in the opening 230.

[0094] The second fin material layer 220 is used to subsequently form the second device fin.

[0095] In this embodiment, an epitaxial growth process is used to form a second fin material layer 220 in the opening 230. The epitaxial growth process allows for better control of process parameters, has high process controllability, and easily obtains precise film thickness dimensions. Furthermore, the epitaxial growth process tends to form a film layer with fewer impurities, resulting in a high-quality second fin material layer 220.

[0096] In this embodiment, the material of the second fin material layer 220 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.

[0097] In this embodiment, the material of the second fin material layer 220 is different from the material of the first fin material layer 210. That is, the channel materials of the first transistor and the second transistor are different to meet the process requirements of different transistors. Specifically, the first transistor is a PMOS transistor and the second transistor is an NMOS transistor. Therefore, in this embodiment, the material of the first fin material layer 210 is silicon germanide, and the material of the second fin material layer 220 is silicon.

[0098] Therefore, in this embodiment, the material of the bottom fin material layer 200 is the same as the material of the second fin material layer 220. Simultaneously, the second fin material layer 220 is formed in the opening 230 using an epitaxial growth process, and the bottom of the opening 230 is the bottom fin material layer 200. Since the material of the bottom fin material layer 200 is the same as the material of the second fin material layer 220, it is beneficial for the growth of the second fin material layer 220, resulting in a higher quality second fin material layer 220. In other embodiments, depending on process requirements, the material of the bottom fin material layer may also be different from the material of the second fin material layer.

[0099] Specifically, the step of forming the second fin material layer 220 in the opening 230 includes: filling the opening 230 with the second fin material layer 220 using an epitaxial growth process, wherein the second fin material layer 220 also covers the top of the first fin material layer 210 located in the first device region 100N; planarizing the second fin material layer 220; and removing the second fin material layer 220 located on top of the first fin material layer 210 located in the first device region 100P.

[0100] Compared to directly forming the second fin material layer in the opening, in this embodiment, the second fin material layer 220 firstly covers the top of the first fin material layer 210 in the first device region 100N, and then the second fin material layer 220 on top of the first fin material layer 210 in the first device region 100P is removed. This facilitates precise control of the thickness of the second fin material layer 220 in the opening 230. The planarization process improves the flatness of the top surfaces of the first fin material layer 210 and the second fin material layer 220, resulting in better height consistency between the first fin material layer 210 and the second fin material layer 220. This, in turn, improves the height consistency of the subsequently formed first device fin and second device fin.

[0101] In this embodiment, a chemical mechanical polishing process is used to planarize the second fin material layer 220.

[0102] Reference Figures 15 to 20 After the second fin material layer 220 is formed, before the subsequent fin patterning process, the method further includes forming a second mask layer 400 on the first fin material layer 210 and the second fin material layer 220.

[0103] The second mask layer 400 is used as a mask layer for subsequent fin formation. In this embodiment, the material of the second mask layer 400 includes one or more of silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the second mask layer 400 is a stack, including a silicon nitride layer 410 and a silicon oxide layer 420 located on the silicon nitride layer 410.

[0104] In this embodiment, the second mask layer 400 is patterned to form the fin mask layer 500. The fin mask layer 500 serves as an etching mask for subsequent fin patterning processing. Patterning the bottom fin material layer 200, the first fin material layer 210, and the second fin material layer 220 using the second mask layer 500 helps improve the accuracy of pattern transfer and forms bottom fins, first device fins, and second device fins with higher dimensional accuracy.

[0105] In this embodiment, the fin mask layer 500 is formed using the self-aligned quadruple patterning (SAQP) process.

[0106] Specifically, refer to Figure 15 A bottom core material layer 430 is formed on the second mask layer 400, and a top core material layer 440 is formed on the bottom core material layer 430; Reference Figure 16 The top core material layer 440 is graphically represented to form a discrete top core layer 450; Reference Figure 17A first sidewall layer 460 is formed on the sidewall of the top core layer 450; after forming the first sidewall layer 460, the top core layer 450 is removed; Reference Figure 18 After removing the top core layer 450, using the first sidewall layer 460 as a mask, the bottom core material layer 430 is patterned to form a bottom core layer 470 protruding from the second mask layer 400; Reference Figure 19 A second sidewall layer 480 is formed on the sidewall of the bottom core layer 470; after forming the second sidewall layer 480, the bottom core layer 470 is removed; (Refer to...) Figure 20 After removing the bottom core layer 470, the second sidewall layer 480 is used as a mask to pattern the second mask layer 400, forming a discrete fin mask layer 500.

[0107] In this embodiment, the fin mask layer 500 is formed using a self-aligned quadruple patterning process, resulting in higher pattern density and more accurate pattern conversion. This not only meets process requirements but also overcomes the limitations of the lithography equipment. In other embodiments, depending on process needs, other patterning methods can be used to form the fin mask layer. For example, a self-aligned double patterning (SADP) process or a single-step lithography-etching process can be employed.

[0108] refer to Figure 21 The fins are patterned by performing fin patterning processing, which patterns the first fin material layer 210, the second fin material layer 220, and the bottom fin material layer 200. The bottom fin material layer 200 is patterned as a bottom fin 600 protruding from the substrate 100 of the first device region 100P and the second device region 100N, respectively. The first fin material layer 210 is patterned as a first device fin 610 protruding from the bottom fin 600 of the first device region 100P, and the second fin material layer 220 is patterned as a second device fin 620 protruding from the bottom fin 600 of the second device region 100N.

[0109] The first device fin 610 and the second device fin 620 are respectively used to provide channels for the first transistor and the second transistor.

[0110] In this embodiment, during the step of patterning the fin, the first fin material layer 210, the second fin material layer 220, and the bottom fin material layer 200 are etched using the fin mask layer 500 as a mask.

[0111] In this embodiment, a dry etching process is used for fin patterning. The dry etching process is an anisotropic etching process, and the etching is directional, which is beneficial for forming bottom fin 600, first device fin 610 and second device fin 620 with better sidewall quality. At the same time, the dry etching process can better control the process parameters and can more accurately control the parameters of fin patterning.

[0112] Specifically, the first fin material layer 210, the second fin material layer 220, and the bottom fin material layer 200 are etched with the top of the etching stop layer 110 as the etching stop position.

[0113] Accordingly, the material of the first device fin 610 is silicon germanide, and the material of the second device fin 620 is silicon.

[0114] It should be noted that an isolation layer will subsequently be formed covering the sidewall of the bottom fin 600. During the formation of the isolation layer, the fin mask layer 500 is removed. For a detailed description of the isolation layer, please refer to the foregoing embodiments, which will not be repeated here.

[0115] It should also be noted that after the isolation layer is formed, a gate structure will be formed that spans the first device fin 610 and the second device fin 620, which will not be discussed in detail here.

[0116] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a base, the base including a first device region for forming a first transistor and a second device region for forming a second transistor; A fin-shaped portion protrudes from the substrate. The fin-shaped portion includes a bottom fin protruding from the substrate and a device fin located on the bottom fin. The device fin includes a first device fin located in the first device region and a second device fin located in the second device region. The contact surfaces of the device fin and the bottom fin are both planar, and the materials of the first device fin and the bottom fin are different. The substrate further includes an etch stop layer located on the substrate, the etch stop layer being formed by ion implantation of the substrate, and the bottom fin protruding from the etch stop layer.

2. The semiconductor structure as described in claim 1, characterized in that, The material of the etching stop layer includes phosphorus-doped silicon, arsenic-doped silicon, carbon-doped silicon, or boron-doped silicon.

3. The semiconductor structure as described in claim 1, characterized in that, The first transistor and the second transistor have different channel conductivity types.

4. The semiconductor structure as described in claim 3, characterized in that, The first transistor is a PMOS transistor; the second transistor is an NMOS transistor.

5. The semiconductor structure as described in claim 1, characterized in that, The material of the first device fin is different from the material of the second device fin.

6. The semiconductor structure as described in claim 1, characterized in that, The material of the bottom fin includes silicon, germanium, silicon germanide, or group III-V semiconductor materials; the material of the first device fin includes silicon, germanium, silicon germanide, or group III-V semiconductor materials; the material of the second device fin includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.

7. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a substrate and a bottom fin material layer on the substrate, the substrate including a first device region for forming a first transistor and a second device region adjacent to the first device region for forming a second transistor; A first fin material layer is formed on the bottom fin material layer, and the material of the first fin material layer is different from the material of the bottom fin material layer; Remove the first fin material layer located in the second device area, and retain the first fin material layer located in the first device area to form an opening that exposes the top of the bottom fin material layer; A second fin material layer is formed in the opening; The fins are patterned by patterning the first fin material layer, the second fin material layer, and the bottom fin material layer. The bottom fin material layer is patterned as a bottom fin protruding from the substrate of the first device region and the second device region, respectively. The first fin material layer is patterned as a first device fin protruding from the bottom fin of the first device region. The second fin material layer is patterned as a second device fin protruding from the bottom fin of the second device region. In the step of providing the substrate, the substrate further includes an etch stop layer located between the substrate and the bottom fin material layer, the etch stop layer being formed by ion implantation of the substrate, and the bottom fin protruding from the etch stop layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The step of providing the substrate includes: providing a substrate; The substrate surface is modified to transform the top portion of the substrate into an etch stop layer; A bottom fin material layer is formed on the etching stop layer.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, The step of removing the first fin material layer located in the second device region includes: forming a first mask layer on the first fin material layer; The first mask layer is patterned to form a mask opening, which exposes the first fin material layer of the second device region; The first fin material layer located in the second device region is removed along the mask opening to form an opening that exposes the top of the bottom fin material layer; After the opening is formed, the first mask layer is removed.

10. The method for forming a semiconductor structure as described in claim 7, characterized in that, After forming the second fin material layer and before performing the fin patterning process, the method further includes: forming a second mask layer on the first fin material layer and the second fin material layer; The second mask layer is patterned to form a fin mask layer; In the step of performing the fin patterning process, the first fin material layer and the second fin material layer are etched using the fin mask layer as a mask.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of modifying the substrate surface, an ion implantation process is used to transform the top portion of the substrate thickness into an etch stop layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The parameters of the ion implantation process include: implanted ions including boron ions, carbon ions, arsenic ions or phosphorus ions, implantation energy of 1 keV to 600 keV, and implantation dose of 1×10¹² ions / cm² to 2×10¹⁸ ions / cm².

13. The method for forming a semiconductor structure as described in claim 7, characterized in that, The step of forming the bottom fin material layer includes: forming the bottom fin material layer on the substrate using an epitaxial growth process.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, After forming the bottom fin material layer on the substrate using an epitaxial growth process, the method further includes: planarizing the top surface of the bottom fin material layer.

15. The method for forming a semiconductor structure as described in claim 7, characterized in that, In the step of forming the first fin material layer on the bottom fin material layer, the first fin material layer is formed by an epitaxial growth process.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, After forming the first fin material layer using an epitaxial growth process, the method further includes: planarizing the top surface of the first fin material layer.

17. The method for forming a semiconductor structure as described in claim 7, characterized in that, In the step of removing the first fin material layer located in the second device region, a dry etching process is used to remove the first fin material layer located in the second device region.

18. The method for forming a semiconductor structure as described in claim 7, characterized in that, The step of forming a second fin material layer in the opening includes: filling the opening with the second fin material layer using an epitaxial growth process, wherein the second fin material layer also covers the top of the first fin material layer located in the first device region; The second fin material layer is planarized, and the second fin material layer located on top of the first fin material layer in the first device region is removed.

19. The method for forming a semiconductor structure as described in claim 7, characterized in that, In the step of providing the substrate, the first transistor and the second transistor have different channel conductivity types.

20. The method for forming a semiconductor structure as described in claim 7, characterized in that, The material of the first fin material layer is different from the material of the second fin material layer.

21. The method for forming a semiconductor structure as described in claim 7, characterized in that, The material of the bottom fin layer includes silicon, germanium, silicon germanide, or group III-V semiconductor materials; the material of the first fin layer includes silicon, germanium, silicon germanide, or group III-V semiconductor materials; the material of the second fin layer includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.

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