IGBT chip with voltage peak suppression cell

Abstract

The present application relates to a kind of IGBT chip with voltage peak suppression cell, the polycrystalline silicon gate surface provided with P-type polycrystalline silicon inversion layer, P-type polycrystalline silicon inversion layer is contacted with N-type surface polycrystalline stock connection layer, to form PN junction diode, the built-in resistance introduced by the polycrystalline silicon gate of this PN junction diode and suppression is connected in series to form suppression circuit, to suppress the speed of gate discharge current when chip is turned off, and then reduce the peak voltage generated thereby.

Description

Technical Field

[0001] The present invention relates to an IGBT chip, in particular to an IGBT chip with a voltage peak suppression cell. Background Art

[0002] Due to the stray inductance L σ The existence of the IGBT will generate a very high voltage overshoot during the IGBT shutdown process. The value of this voltage overshoot is equal to -L σ *di / dt. If the stray inductance and di / dt are large, the voltage peak will be much higher than the bus voltage. Moreover, in the case of inductive loads, the high current can easily trigger dynamic avalanche, causing device failure. This situation is particularly serious when devices are used in parallel.

[0003] The usual solution is to increase the device's Miller capacitance and gate resistance. This way, as the voltage rises, the gate voltage to ground is increased by the displacement current used to charge the Miller voltage and the gate resistance, reopening the channel. The channel current effectively slows the current drop during the turn-off process, preventing the surge peak from reaching a high level. However, the Miller capacitance and gate resistance introduced to effectively suppress the peak voltage inevitably increase turn-on energy consumption. Summary of the Invention

[0004] To solve the device failure problem caused by the above-mentioned voltage overshoot, the purpose of the present invention is to provide an IGBT chip with a voltage peak suppression cell, which introduces a suppression circuit in the cell array to reduce the peak voltage and effectively reduce its impact on the turn-on process.

[0005] The IGBT chip with voltage peak suppression cells of the present invention includes an IGBT chip with voltage peak suppression cells, including a chip body, the chip body including a plurality of normal cells, the chip body also including a plurality of suppression cells, the substrate surface of the suppression cell is provided with a cell gate groove and a suppression gate groove, the cell gate groove is provided with a cell region polysilicon gate, the suppression gate groove is provided with a suppression polysilicon gate, the cell region polysilicon gate and the suppression polysilicon gate are both N-type polysilicon, the surface of the suppression polysilicon gate is provided with a P-type polysilicon inversion layer, and an N-type surface polysilicon connection located on the substrate surface is provided between the suppression polysilicon gate and the cell region polysilicon gate. A connection layer is provided, one end of the N-type surface polysilicon connection layer is connected to the P-type polysilicon inversion layer, and the other end is connected to the polysilicon gate of the cell area. An emitter region located on the surface of the substrate is provided between the cell gate trench and the gate trench of an adjacent normal cell, or between the cell gate trench of an adjacent suppression cell. The surfaces of the P-type polysilicon inversion layer, the N-type surface polysilicon connection layer and the polysilicon gate of the cell area are all provided with an insulating dielectric layer. An emitter metal is provided above the cell gate trench, and the emitter metal is connected to the emitter region through an emitter contact hole. A gate metal is provided above the suppression gate trench, and the gate metal is connected to the suppression polysilicon gate through the gate contact hole.

[0006] The advantage of the IGBT chip with voltage peak suppression cells is that a P-type polysilicon inversion layer is provided on the surface of the suppression polysilicon gate, and the P-type polysilicon inversion layer is in contact with the N-type surface polysilicon connection layer, thereby forming a PN junction diode. The PN junction diode and the built-in resistor introduced by the suppression polysilicon gate are connected in series to form a suppression circuit to suppress the speed of the gate discharge current when the chip is turned off, thereby reducing the peak voltage generated thereby.

[0007] In the IGBT chip with voltage peak suppression cells of the present invention, the width of the suppression polysilicon gate is smaller than the width of the polysilicon gate in the cell region.

[0008] This design increases the resistance of the built-in suppressor gate resistor introduced by the suppressor polysilicon gate. In specific implementation, the operator can adjust the built-in suppressor gate resistor by adjusting the width of the suppressor polysilicon gate.

[0009] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement them in accordance with the contents of the specification, the embodiments of the present invention are described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a planar schematic diagram of an IGBT chip with a voltage peak suppression cell;

[0011] Figure 2 is a planar schematic diagram of the inhibition cell;

[0012] Figure 3 is with Figure 1 The partial cross-sectional view of the IGBT chip corresponding to the dotted line C1;

[0013] Figure 4 is with Figure 1 The partial cross-sectional view of the IGBT chip corresponding to the dotted line C2;

[0014] Figure 5 is with Figure 1 The partial cross-sectional view of the IGBT chip corresponding to the dotted line C3;

[0015] Figure 6 This is a schematic diagram of the circuit connection between normal cells and inhibitory cells;

[0016] In the figure, substrate 1, cellular gate trench 2, suppression gate trench 3, cellular region polysilicon gate 4, suppression polysilicon gate 5, P-type polysilicon inversion layer 6, N-type surface polysilicon connection layer 7, emitter region 8, insulating dielectric layer 9, emitter metal 10, emitter contact hole 11, gate metal 12, gate contact hole 13. DETAILED DESCRIPTION

[0017] The following embodiments of the present invention are described in further detail with reference to the accompanying drawings and examples. The following examples are used to illustrate the present invention but are not intended to limit the scope of the present invention.

[0018] Example 1:

[0019] See also Figures 1 to 6The IGBT chip with voltage peak suppression cells of this embodiment includes a chip body, which includes a plurality of normal cells and a plurality of suppression cells. A cell gate trench 2 and a suppression gate trench 3 are provided on the surface of a substrate 1 of the suppression cell. A cell region polysilicon gate 4 is provided in the cell gate trench, and a suppression polysilicon gate 5 is provided in the suppression gate trench. Both the cell region polysilicon gate and the suppression polysilicon gate are N-type polysilicon. A P-type polysilicon inversion layer 6 is provided on the surface of the suppression polysilicon gate. An N-type surface polysilicon connection layer 7 is provided between the suppression polysilicon gate and the cell region polysilicon gate. One end of the N-type surface polysilicon connection layer is connected to the P-type polysilicon. An inversion layer is provided, and the other end is connected to the polysilicon gate of the cell area. An emitter region 8 located on the surface of the substrate is provided between the cell gate trench and the gate trench of the adjacent normal cell, or between the cell gate trench of the adjacent suppression cell. In this embodiment, the emitter region is located between the cell gate trench and the gate trench of the adjacent normal cell. An insulating dielectric layer 9 is provided on the surface of the P-type polysilicon inversion layer, the N-type surface polysilicon connection layer and the polysilicon gate of the cell area. An emitter metal 10 is provided above the cell gate trench, and the emitter metal is connected to the emitter region through an emitter contact hole 11. A gate metal 12 is provided above the suppression gate trench, and the gate metal is connected to the suppression polysilicon gate through a gate contact hole 13.

[0020] The IGBT chip with a voltage peak suppression cell of the present invention has a P-type polysilicon inversion layer provided on the surface of the suppression polysilicon gate. The P-type polysilicon inversion layer contacts the N-type surface polysilicon connection layer, thereby forming a PN junction diode. The PN junction diode and the built-in resistor introduced by the suppression polysilicon gate are connected in series to form a suppression circuit to suppress the speed of the gate discharge current when the chip is turned off, thereby reducing the peak voltage generated thereby.

[0021] Specifically, during the cell opening process, the polysilicon gate is suppressed from charging to the normal channel area through the built-in resistor and diode, but during the shutdown process, the discharge current of the polysilicon gate is suppressed by the built-in resistor and diode, and the shutdown of the cell is delayed, which also means that the device current drop rate is reduced, and the shutdown peak voltage is also reduced accordingly. However, the charging current will not be suppressed by the diode during the opening process.

[0022] Due to the introduction of built-in resistors and diodes, the ratio of inhibition cells to normal cells can be minimized, which reduces its impact on turn-on. More importantly, when turned on, the inhibition cells can work through the normal cell gate trench, and the length of the inhibition gate trench is almost the same as that of the cell gate trench, so the impact on turn-on can even be ignored.

[0023] Among them, the normal cell is similar to the existing IGBT chip cell, and its specific structure and principle will not be repeated.

[0024] Preferably, in the IGBT chip with the voltage peak suppression cell of this embodiment, the width of the suppression polysilicon gate is smaller than the width of the polysilicon gate in the cell region.

[0025] This design increases the resistance of the built-in suppressor gate resistor introduced by the suppressor polysilicon gate. In specific implementation, the operator can adjust the built-in suppressor gate resistor by adjusting the width of the suppressor polysilicon gate.

[0026] In addition, operators can control the size of the PN junction reverse leakage by controlling the injection concentration of the P-type polysilicon inversion layer and its overlapping width with the N-type surface polysilicon connection layer, thereby adjusting the size of the reverse discharge current of the polysilicon gate through the diode during the device shutdown process.

[0027] The above are only preferred embodiments of the present invention, which are used to assist those skilled in the art to implement the corresponding technical solutions, and are not used to limit the scope of protection of the present invention, which is defined by the appended claims. It should be pointed out that for those skilled in the art, a number of equivalent improvements and variations can be made based on the technical solutions of the present invention, and these improvements and variations should also be regarded as the scope of protection of the present invention. At the same time, it should be understood that although this specification is described in accordance with the above-mentioned embodiments, not every embodiment contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions of each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An IGBT chip with a voltage peak suppression cell, comprising a chip body, the chip body including a plurality of normal cells, characterized in that: The chip body also includes a plurality of suppression cells, and the surface of the substrate (1) of the suppression cell is provided with a cell gate groove (2) and a suppression gate groove (3), a cell region polysilicon gate (4) is provided in the cell gate groove, and a suppression polysilicon gate (5) is provided in the suppression gate groove. Both the cell region polysilicon gate and the suppression polysilicon gate are N-type polysilicon, and a P-type polysilicon inversion layer (6) is provided on the surface of the suppression polysilicon gate. An N-type surface polysilicon connection layer (7) located on the surface of the substrate is also provided between the suppression polysilicon gate and the cell region polysilicon gate, and one end of the N-type surface polysilicon connection layer is connected to the P-type polysilicon inversion layer, and the other end is connected to the N-type surface polysilicon connection layer. The cell region polysilicon gate is connected, an emitter region (8) located on the substrate surface is provided between the cell gate trench and the gate trench of an adjacent normal cell, or between the cell gate trench of an adjacent suppression cell, an insulating dielectric layer (9) is provided on the surface of the P-type polysilicon inversion layer, the N-type surface polysilicon connection layer and the cell region polysilicon gate, an emitter metal (10) is provided above the cell gate trench, and the emitter metal is connected to the emitter region through an emitter contact hole (11), a gate metal (12) is provided above the suppression gate trench, and the gate metal is connected to the suppression polysilicon gate through a gate contact hole (13).

2. The IGBT chip with a voltage peak suppression cell according to claim 1, characterized in that: The width of the suppression polysilicon gate is smaller than the width of the cell region polysilicon gate.

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