A thyristor chip and a manufacturing method thereof

Abstract

This invention relates to a thyristor chip and its fabrication method. The thyristor chip includes: a molybdenum wafer, an insulating film layer, an anode metal, a cathode metal, a gate metal, an anode P-type layer, an N-type base region, a P-type base region, a cathode N-type region, and a conductive film layer. The gate metal includes a central gate metal and an amplifying gate metal. The cathode N-type region includes a cathode emitting N-type region and an amplifying gate N-type region. The P-type base region, N-type base region, and anode P-type layer are sequentially stacked. The anode metal is disposed on the lower surface of the anode P-type layer. The cathode metal, central gate metal, and amplifying gate metal have the same thickness. An insulating film layer is deposited on the lower surface of the molybdenum wafer corresponding to the amplifying gate metal, and a conductive film layer is deposited corresponding to the cathode metal. The advantages of this invention are: it can achieve the purpose of isolating the amplifying gate and the cathode during packaging, reducing the complexity of the process and lowering the process cost.

Description

Technical Field

[0001] This invention relates to a thyristor chip and its manufacturing method. Background Technology

[0002] A silicon controlled rectifier, also known as a thyristor, is a semiconductor device with four interleaved P and N layers.

[0003] A thyristor chip has three electrodes: anode, cathode, and gate. Applying a positive trigger signal between the gate and cathode controls the thyristor's conduction. The gate and cathode are on the same surface, and both surfaces need to be covered with a thin metal film. The metal film leads out electrodes and achieves ohmic contact. The gate metal layer and the cathode metal layer must be isolated. High-power thyristors are typically divided into a center gate stage and an amplifying gate stage. The center gate is connected to the external trigger circuit through a gate assembly, while the amplifying gate can reduce turn-on time, reduce turn-on current, and improve turn-on di / dt, etc.

[0004] There are three common methods for isolating the amplification gate from the cathode: First, reduce the thickness of the amplification gate metal; second, process a molybdenum sheet according to the shape of the amplification gate, reducing the thickness of the molybdenum sheet at the amplification gate metal; third, process a groove on the silicon wafer to reduce the height of the amplification gate metal. Essentially, all three methods create a gap between the amplification gate metal and the molybdenum sheet. However, the processing is relatively complex, and the gate and cathode are prone to short circuits.

[0005] To address this issue, CN202010677130.4 provides a thyristor chip, a thyristor, and its fabrication method, employing PECVD technology to form a first dielectric thin film layer on the amplification gate metal. This first dielectric thin film layer achieves isolation between the amplification gate and the cathode. However, the process of setting the dielectric thin film on the amplification gate metal remains relatively complex. Furthermore, due to the gap between the cathode and the molybdenum sheet, impurities can enter between the cathode and the amplification gate before packaging, posing a risk of short circuits. Relying on lamination to allow the molybdenum sheet to undergo minor deformation to contact the cathode metal also carries the risk of cathode open circuits due to molybdenum sheet deformation, resulting in low conductivity reliability. Summary of the Invention

[0006] The purpose of this invention is to provide a thyristor chip and its manufacturing method to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A thyristor chip includes: a molybdenum sheet, an insulating film layer, an anode metal, a cathode metal, a gate metal, an anode P-type layer, an N-type base region, a P-type base region, a cathode N-type region, and a conductive film layer; the gate metal includes: a central gate metal and an amplifying gate metal; the cathode N-type region includes a cathode emitting N-type region and an amplifying gate N-type region;

[0009] The P-type base region, N-type base region, and anode P-type layer are sequentially stacked; the anode metal is disposed on the lower surface of the anode P-type layer; the cathode N-type region is located within a portion of the P-type base region, and the upper surface of the cathode N-type region is flush with the upper surface of the P-type base region; the cathode metal is located above the cathode emitting N-type region and exposes part of the upper surface of the cathode emitting N-type region; the central gate metal is located above the upper surface of the P-type base region and does not contact the amplifying gate N-type region; the amplifying gate metal is located above the surface of the P-type base region and simultaneously contacts both the P-type base region and the amplifying gate N-type region.

[0010] The cathode metal, the center gate metal, and the amplification gate metal have the same thickness;

[0011] An insulating adhesive film layer is deposited on the lower surface of the molybdenum sheet at the location corresponding to the gate metal, and a conductive adhesive film layer is deposited at the location corresponding to the cathode metal. The molybdenum sheet, the insulating adhesive film layer, and the conductive adhesive film layer are pressed together on top of the gate metal and the cathode metal through a lamination process, so that the lower surface of the insulating adhesive film layer contacts the gate metal and the lower surface of the conductive adhesive film layer contacts the cathode metal.

[0012] The molybdenum sheet, insulating film layer, and conductive film layer together do not cover the central gate metal.

[0013] As a further embodiment of the thyristor chip of the present invention: the cathode metal, the center gate metal, and the amplification gate metal are formed by the same metal film and processed by metal etching.

[0014] As a further embodiment of the thyristor chip of the present invention: the material of the insulating film layer includes 30-50 parts of epoxidized polybutadiene, 30-50 parts of bismaleimide resin, 50-60 parts of polyurethane modified epoxy resin, 50-60 parts of polyether modified epoxy resin, and 15-25 parts of curing agent.

[0015] As a further embodiment of the thyristor chip of the present invention: the insulating film layer and the conductive film layer have the same thickness; the thickness of the insulating film layer is less than half the thickness of the cathode metal.

[0016] As a further embodiment of the thyristor chip of the present invention: the ratio of the thickness of the insulating film layer to the thickness of the cathode metal is greater than or equal to 0.15 and less than or equal to 0.3.

[0017] As a further embodiment of the thyristor chip of the present invention: a rubber insulating layer is filled between the center gate metal and the amplification gate metal.

[0018] As a further embodiment of the thyristor chip of the present invention: the material of the conductive adhesive film layer includes: 50-70 parts of epoxy resin, 30-50 parts of epoxy modifier, 40-60 parts of conductive particles, 0.5-1 part of curing agent, 0.1-0.3 parts of dispersant, and 5-15 parts of diluent.

[0019] A method for manufacturing a thyristor chip includes the following steps:

[0020] Step 1: Form a P-type base region and an anode P-type layer on the upper and lower surfaces of the N-type base region, respectively;

[0021] Step 2: Form a cathode N-type region in a portion of the P-type base region, wherein the upper surface of the cathode N-type region is flush with the upper surface of the P-type base region. The cathode N-type region includes: a cathode emission N-type region and an amplification gate N-type region.

[0022] Step 3: An ohmic contact electrode metal is formed above the P-type base region and below the anode P-type layer, wherein the ohmic contact electrode metal below the anode P-type layer serves as the anode metal.

[0023] Step 4: The ohmic contact electrode metal above the P-type base region is processed by metal etching to form cathode metal, central gate metal, and amplification gate metal. The cathode metal is located above the cathode emitting N-type region and exposes part of the upper surface of the cathode emitting N-type region; the amplification gate metal is located above the surface of the P-type base region and is in contact with both the P-type base region and the amplification gate N-type region; the central gate metal is located above the upper surface of the P-type base region and is not in contact with the amplification gate N-type region.

[0024] Step 5: Deposit an insulating adhesive film layer on the lower surface of the molybdenum sheet corresponding to the gate metal and a conductive adhesive film layer corresponding to the cathode metal. Press the molybdenum sheet, the insulating adhesive film layer, and the conductive adhesive film layer together onto the gate metal and the cathode metal using a lamination process. The lower surface of the insulating adhesive film layer contacts the gate metal, and the lower surface of the conductive adhesive film layer contacts the cathode metal. The molybdenum sheet, the insulating adhesive film layer, and the conductive adhesive film layer together do not cover the central gate metal.

[0025] As a further embodiment of the method for manufacturing a thyristor chip according to the present invention: the material of the insulating film layer includes 30-50 parts of epoxidized polybutadiene, 30-50 parts of bismaleimide resin, 50-60 parts of polyurethane modified epoxy resin, 50-60 parts of polyether modified epoxy resin, and 15-25 parts of curing agent.

[0026] As a further embodiment of the method for manufacturing a thyristor chip according to the present invention: the insulating film layer and the conductive film layer have the same thickness; the thickness of the insulating film layer is less than half the thickness of the cathode metal.

[0027] As a further embodiment of the method for manufacturing a thyristor chip according to the present invention: the ratio of the thickness of the insulating film layer to the thickness of the cathode metal is greater than or equal to 0.15 and less than or equal to 0.3.

[0028] The advantages of this invention are that it can achieve the purpose of isolating the amplification gate and the cathode during packaging, thereby reducing the complexity of the process and the cost of the process.

[0029] Compared to the three traditional methods of isolating the gate and cathode in amplification, this method reduces process complexity and cost. Setting an insulating film layer on a molybdenum sheet is far less difficult than setting a dielectric film on the gate metal, thus reducing process complexity and cost.

[0030] The fabrication difficulty of adding an insulating film layer on a molybdenum wafer is lower than that of adding one on a silicon wafer, resulting in reduced processing costs. The insulating and conductive film layers are respectively bonded to the gate metal and cathode metal, eliminating the need for molybdenum wafer deformation to maintain contact with the cathode metal during lamination. This leads to high structural stability and high conductivity reliability. The conductive film layer further ensures the stability and reliability of conductivity between the cathode metal and the molybdenum wafer after lamination.

[0031] When the molybdenum sheet, insulating film layer, and conductive film layer are applied to the silicon wafer, the silicon wafer surface can be cleaned by air cleaning, followed by lamination. After lamination, the cathode metal and the amplification gate metal are completely sealed under the molybdenum sheet, eliminating the risk of impurities entering from the ends.

[0032] Other features and advantages of the present invention will be disclosed in detail in the following detailed description and accompanying drawings. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of a thyristor chip according to the present invention;

[0034] Figure 2 This is a flowchart of a method for manufacturing a thyristor chip according to the present invention.

[0035] List of icon symbols:

[0036] Thyristor chip 100, molybdenum sheet 1, insulating film layer 2, anode metal 3, cathode metal 4, center gate metal 5, amplifying gate metal 6, anode P-type layer 7, N-type base region 8, P-type base region 9, amplifying gate N-type region 10, cathode emitting N-type region 11, conductive film layer 12. Detailed Implementation

[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] like Figure 1 and Figure 2 As shown in the embodiment of the present invention, a thyristor chip 100 includes: a molybdenum sheet 1, an insulating film layer 2, an anode metal 3, a cathode metal 4, a gate metal, an anode P-type layer 7, an N-type base region 8, a P-type base region 9, a cathode N-type region, and a conductive film layer 12.

[0039] The gate metal includes a central gate metal 5 and an amplifying gate metal 6. The cathode N-type region includes an amplifying gate N-type region 10 and a cathode emitting N-type region 11. A P-type base region 9, an N-type base region 8, and an anode P-type layer 7 are sequentially stacked. The anode metal 3 is disposed on the lower surface of the anode P-type layer 7. The cathode N-type region is located within a portion of the P-type base region 9, and its upper surface is flush with the upper surface of the P-type base region 9. The cathode metal 4 is located above the cathode emitting N-type region 11 and exposes a portion of its upper surface. The central gate metal 5 is located above the upper surface of the P-type base region 9 and does not contact the amplifying gate N-type region 10. The amplifying gate metal 6 is located above the surface of the P-type base region 9 and simultaneously contacts both the P-type base region 9 and the amplifying gate N-type region 10.

[0040] The cathode metal 4, the central gate metal 5, and the amplification gate metal 6 have the same thickness. In one specific embodiment, the cathode metal 4, the central gate metal 5, and the amplification gate metal 6 are formed from the same metal film using a metal etching process.

[0041] An insulating adhesive film layer 2 is deposited on the lower surface of the molybdenum sheet 1 at the location corresponding to the gate metal 6, and a conductive adhesive film layer 12 is deposited at the location corresponding to the cathode metal 4. The molybdenum sheet 1, the insulating adhesive film layer 2, and the conductive adhesive film layer 12 are then laminated together onto the gate metal 6 and the cathode metal 4, with the lower surface of the insulating adhesive film layer 2 contacting the gate metal 6 and the lower surface of the conductive adhesive film layer 12 contacting the cathode metal 4. The entire assembly of the molybdenum sheet 1, the insulating adhesive film layer 2, and the conductive adhesive film layer 12 does not cover the central gate metal 5.

[0042] In a preferred embodiment, the insulating film layer 2 comprises 30-50 parts of epoxidized polybutadiene, 30-50 parts of bismaleimide resin, 50-60 parts of polyurethane-modified epoxy resin, 50-60 parts of polyether-modified epoxy resin, and 15-25 parts of curing agent.

[0043] In a preferred embodiment, the insulating film layer 2 and the conductive film layer 12 have the same thickness.

[0044] In a preferred embodiment, the thickness of the insulating film layer 2 is less than half the thickness of the cathode metal 4. In a specific embodiment, the ratio of the thickness of the insulating film layer 2 to the thickness of the cathode metal 4 is greater than or equal to 0.15 and less than or equal to 0.3. Specifically, the cathode metal 4 is set to 30 μm.

[0045] As an alternative implementation, a rubber insulating layer can also be filled between the central gate metal 5 and the amplifying gate metal 6. The rubber insulating layer can prevent foreign matter from being sealed into the area between the central gate metal 5 and the amplifying gate metal 6 during encapsulation.

[0046] As one specific implementation method, the conductive adhesive film layer comprises: 50-70 parts epoxy resin, 30-50 parts epoxy modifier, 40-60 parts conductive particles, 0.5-1 part curing agent, 0.1-0.3 parts dispersant, and 5-15 parts diluent.

[0047] A method for manufacturing a thyristor chip 100 includes the following steps:

[0048] Step 1: Form a P-type base region 9 and an anode P-type layer 7 on the upper and lower surfaces of the N-type base region 8, respectively.

[0049] Step 2: Form a cathode N-type region in a portion of the P-type base region 9, wherein the upper surface of the cathode N-type region is flush with the upper surface of the P-type base region 9. The cathode N-type region includes: cathode emission N-type region 11 and amplification gate N-type region 10.

[0050] Step 3: An ohmic contact electrode metal is formed above the P-type base region 9 and below the anode P-type layer 7, wherein the ohmic contact electrode metal below the anode P-type layer 7 serves as the anode metal 3.

[0051] Step 4: The ohmic contact electrode metal above the P-type base region 9 is processed using metal etching to form cathode metal 4, center gate metal 5, and amplification gate metal 6. Cathode metal 4 is located above the cathode emitting N-type region 11 and exposes part of the upper surface of the cathode emitting N-type region 11. Amplification gate metal 6 is located above the surface of the P-type base region 9 and is in contact with both the P-type base region 9 and the amplification gate N-type region 10. Center gate metal 5 is located above the upper surface of the P-type base region 9 and is not in contact with the amplification gate N-type region 10.

[0052] Step 5: An insulating adhesive film layer 2 is deposited on the lower surface of the molybdenum sheet 1 at the location corresponding to the gate metal 6, and a conductive adhesive film layer 12 is deposited at the location corresponding to the cathode metal 4. The molybdenum sheet 1, the insulating adhesive film layer 2, and the conductive adhesive film layer 12 are then laminated onto the gate metal 6 and the cathode metal 4 using a lamination process. The lower surface of the insulating adhesive film layer 2 is aligned with the gate metal 6. The lower surface of the conductive adhesive film layer 12 contacts the cathode metal 4. The entire assembly of the molybdenum sheet 1, the insulating adhesive film layer 2, and the conductive adhesive film layer 12 does not cover the central gate metal 5.

[0053] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0054] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A thyristor chip, characterized by Comprise: Molybdenum sheet, insulating adhesive film layer, anode metal, cathode metal, gate metal, anode P-type layer, N-type base area, P-type base area, cathode N-type area and conductive adhesive film layer; the gate metal comprises: center gate metal and amplification gate metal; the cathode N-type area: including cathode emission N-type area and amplification gate N-type area; The P-type base area, the N-type base area and the anode P-type layer are sequentially stacked and arranged; the anode metal is arranged on the lower surface of the anode P-type layer; the cathode N-type area is located in part of the P-type base area, and the upper surface of the cathode N-type area is flush with the upper surface of the P-type base area; the cathode metal is located on the cathode emission N-type area and exposes part of the upper surface of the cathode emission N-type area; the center gate metal is located on the upper surface of the P-type base area and does not contact the amplification gate N-type area; the amplification gate metal is located on the surface of the P-type base area and simultaneously contacts the P-type base area and the amplification gate N-type area; The thicknesses of the cathode metal, the center gate metal and the amplification gate metal are the same; The insulating adhesive film layer is deposited on the lower surface of the molybdenum sheet corresponding to the amplification gate metal, and the conductive adhesive film layer is deposited on the lower surface of the molybdenum sheet corresponding to the cathode metal; the whole composed of the molybdenum sheet, the insulating adhesive film layer and the conductive adhesive film layer is pressed to the upper side of the amplification gate metal and the cathode metal to make the lower surface of the insulating adhesive film layer contact the amplification gate metal, and the lower surface of the conductive adhesive film layer contact the cathode metal; The whole composed of the molybdenum sheet, the insulating adhesive film layer and the conductive adhesive film layer does not cover the center gate metal.

2. The thyristor chip according to claim 1, wherein the cathode metal, the center gate metal and the amplification gate metal are the same metal film processed by metal etching.

3. The thyristor chip according to claim 1, wherein the material of the insulating adhesive film layer comprises 30-50 parts of epoxidized polybutadiene, 30-50 parts of bismaleimide resin, 50-60 parts of polyurethane modified epoxy resin, 50-60 parts of polyether modified epoxy resin and 15-25 parts of curing agent.

4. The thyristor chip according to claim 1, wherein the thicknesses of the insulating adhesive film layer and the conductive adhesive film layer are the same, and the thickness of the insulating adhesive film layer is less than half of the thickness of the cathode metal.

5. The thyristor chip according to claim 4, wherein the ratio of the thickness of the insulating adhesive film layer to the thickness of the cathode metal is greater than or equal to 0.15 and less than or equal to 0.

3.

6. The thyristor chip according to claim 1, wherein a rubber isolation layer is filled between the center gate metal and the amplification gate metal. Comprise the following steps: Step 1, forming P-type base area and anode P-type layer on the upper surface and lower surface of N-type base area respectively; ​ ​ ​ 7. A method of fabricating a thyristor chip, characterized by: ​ ​ Step 2, forming a cathode N-type region in a partial region of the P-type base region, wherein the upper surface of the cathode N-type region is flush with the upper surface of the P-type base region, and the cathode N-type region comprises a cathode emission N-type region and an amplification gate N-type region; Step 3, forming an ohmic contact electrode metal above the P-type base region and below the anode P-type layer, wherein the ohmic contact electrode metal below the anode P-type layer serves as an anode metal; Step 4, processing the ohmic contact electrode metal above the P-type base region by metal etching to form a cathode metal, a center gate metal, and an amplification gate metal, wherein the cathode metal is located above the cathode emission N-type region and exposes part of the upper surface of the cathode emission N-type region; the amplification gate metal is located above the surface of the P-type base region and simultaneously contacts the P-type base region and the amplification gate N-type region; and the center gate metal is located above the upper surface of the P-type base region and does not contact the amplification gate N-type region; Step 5, depositing an insulating adhesive film layer at the position corresponding to the amplification gate metal on the lower surface of a molybdenum sheet and depositing a conductive adhesive film layer at the position corresponding to the cathode metal; and pressing the whole of the molybdenum sheet, the insulating adhesive film layer, and the conductive adhesive film layer to the upper side of the amplification gate metal and the cathode metal by a pressing process, wherein the lower surface of the insulating adhesive film layer contacts the amplification gate metal, the lower surface of the conductive adhesive film layer contacts the cathode metal, and the whole of the molybdenum sheet, the insulating adhesive film layer, and the conductive adhesive film layer does not cover the center gate metal.

8. The method according to claim 7, wherein the material of the insulating adhesive film layer comprises 30-50 parts of epoxidized polybutadiene, 30-50 parts of bismaleimide resin, 50-60 parts of polyurethane-modified epoxy resin, 50-60 parts of polyether-modified epoxy resin, and 15-25 parts of curing agent.

9. The method according to claim 7, wherein the thickness of the insulating adhesive film layer is the same as that of the conductive adhesive film layer, and the thickness of the insulating adhesive film layer is less than half of the thickness of the cathode metal.

10. The method according to claim 9, wherein the ratio of the thickness of the insulating adhesive film layer to the thickness of the cathode metal is greater than or equal to 0.15 and less than or equal to 0.

3. ​ ​ ​

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