A fully gallium nitride integrated power conversion module

Abstract

The present invention relates to a fully gallium nitride integrated power conversion module, which includes a low-side drive circuit, a high-side drive circuit, and a half-bridge module. The half-bridge module includes a first gallium nitride power device and a second gallium nitride power device. The drain of the first gallium nitride power device is connected to a high voltage HV, the source is connected to the drain of the second gallium nitride power device, and the gate is connected to the output end of the high-side drive circuit; the source of the second gallium nitride power device is grounded, and the gate is connected to the output end of the low-side drive circuit; the high-side drive circuit includes a first input end and a second input end. The first input end is connected to a first high-side drive signal source, and the second input end is connected to a second high-side drive signal source; the input end of the low-side drive circuit is connected to a low-side drive signal source. The present invention can reduce the usage threshold of gallium nitride power devices.

Description

Technical Field

[0001] The present invention relates to the technical field of all-gallium nitride power integration, and particularly to an all-gallium nitride integrated power conversion module. Background Art

[0002] With the rapid development of power electronics technology, power converters are evolving towards higher power density. For power converters, passive energy storage components (inductors, capacitors, etc.) occupy a relatively large volume, restricting further improvement of power density.

[0003] Common silicon-based devices generally operate in the range of dozens of kHz to hundreds of kHz, while gallium nitride devices have a small on-resistance and extremely small parasitic capacitance, and there is no reverse recovery time of silicon-based devices. Therefore, they can operate at higher frequencies, with the operating frequency reaching several MHz. A higher operating frequency means that subsequent power converters can greatly reduce the volume and weight of inductors and capacitors, and thus reduce the volume and weight of the entire power converter, achieving the effect of improving power density.

[0004] However, for gallium nitride power devices, an operating frequency of several MHz poses higher requirements for the driving of gallium nitride power transistors and also brings multiple restrictions in terms of use. First, common gallium nitride power devices have a smaller gate voltage tolerance. For common enhancement-mode gallium nitride devices, the gate safety voltage is from -5V to 8V, while the gate operating voltage of general commercial enhancement-mode gallium nitride devices is 5V. This makes it easy to exceed the gate safety voltage of gallium nitride devices, thereby causing device damage. Second, the threshold of enhancement-mode gallium nitride devices is relatively small, generally about 1V. And gallium nitride devices have a fast switching speed and are commonly used in high-frequency situations. In this way, a large dv / dt noise will be coupled to the drive circuit through the gate parasitic inductance, resulting in mis-triggering. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an all-gallium nitride integrated power conversion module to lower the usage threshold of gallium nitride power devices.

[0006] The technical solution adopted by the present invention to solve its technical problems is: to provide a fully gallium nitride integrated power conversion module, including a low-side drive circuit, a high-side drive circuit and a half-bridge module. The half-bridge module includes a first gallium nitride power device and a second gallium nitride power device. The drain of the first gallium nitride power device is connected to a high voltage HV, the source is connected to the drain of the second gallium nitride power device, and the gate is connected to the output end of the high-side drive circuit; the source of the second gallium nitride power device is grounded, and the gate is connected to the output end of the low-side drive circuit; the high-side drive circuit includes a first input end and a second input end. The first input end is connected to a first high-side drive signal source, and the second input end is connected to a second high-side drive signal source; the input end of the low-side drive circuit is connected to a low-side drive signal source;

[0007] Within a complete half-bridge drive cycle, at time t0, the first high-side drive signal source, the second high-side drive signal source and the low-side drive signal source are all at low level, and both the first gallium nitride power device and the second gallium nitride power device are in the off state; at time t1, the low-side drive signal source turns to high level, and the second gallium nitride power device turns to the on state; from time t2 to t3, the low-side drive signal source, the first high-side drive signal source and the second high-side drive signal source are all at low level, and both the first gallium nitride power device and the second gallium nitride power device are in the off state; from time t3 to t4, the first high-side drive signal source converts to high level, and the first gallium nitride power device turns on, so that the midpoint output of the first gallium nitride power device and the second gallium nitride power device rises to the high voltage HV, and the gate voltage of the first gallium nitride power device rises to the sum of the high voltage HV and the threshold voltage VTH; from time t4 to t5, the first high-side drive signal source and the second high-side drive signal source are at low level, the gate voltage of the first gallium nitride power device, and the midpoint output of the first gallium nitride power device and the second gallium nitride power device remain in the previous state; from time t5 to t6, the first high-side drive signal source is at low level, the second high-side drive signal source is at high level, the gate voltage of the first gallium nitride power device turns to high voltage HV, the midpoint output of the first gallium nitride power device and the second gallium nitride power device remains at high voltage HV, the drive voltage Vgs of the first gallium nitride power device is less than the threshold voltage VTH, and the first gallium nitride power device turns off.

[0008] The high-side drive circuit includes a first high-side N-type enhancement-mode gallium nitride (GaN) HEMT device, a second high-side N-type enhancement-mode GaN HEMT device, a third high-side N-type enhancement-mode GaN HEMT device, a fourth high-side N-type enhancement-mode GaN HEMT device, a fifth high-side N-type enhancement-mode GaN HEMT device, a sixth high-side N-type enhancement-mode GaN HEMT device, a seventh high-side N-type enhancement-mode GaN HEMT device, and an eighth high-side N-type enhancement-mode GaN HEMT device. The gate of the first high-side N-type enhancement-mode GaN HEMT device serves as the first input terminal of the high-side drive circuit, connecting to the first high-side drive signal source. The source is connected to one end of a fifth two-dimensional electron gas resistor, and the drain is connected to one end of a first two-dimensional electron gas resistor. The other end of the first two-dimensional electron gas resistor is connected to the high-end power supply, and the other end of the fifth two-dimensional electron gas resistor is grounded. The gate of the sixth high-side N-type enhancement-mode GaN HEMT device serves as the second input terminal of the high-side drive circuit, connecting to the second high-side drive signal source. The source is connected to one end of a sixth two-dimensional electron gas resistor, and the drain is connected to one end of a fourth two-dimensional electron gas resistor. The other end of the fourth two-dimensional electron gas resistor is connected to the high-end power supply, and the other end of the sixth two-dimensional electron gas resistor is grounded. The gate of the second high-side N-type enhancement-mode GaN HEMT device is connected to the drain of the fourth high-side N-type enhancement-mode GaN HEMT device, the drain is connected to one end of a second two-dimensional electron gas resistor, and the source is connected to the drain of the third high-side N-type enhancement-mode GaN HEMT device. The other end of the second two-dimensional electron gas resistor is connected to the high-end power supply. The gate of the third high-side N-type enhancement-mode GaN HEMT device is connected to the drain of the first high-side N-type enhancement-mode GaN HEMT device, and the source is grounded. The gate of the fourth high-side N-type enhancement-mode GaN HEMT device is connected to the drain of the second high-side N-type enhancement-mode GaN HEMT device, the drain is connected to one end of a third two-dimensional electron gas resistor, and the source is connected to the drain of the fifth high-side N-type enhancement-mode GaN HEMT device. The other end of the third two-dimensional electron gas resistor is connected to the high-end power supply. The gate of the fifth high-side N-type enhancement-mode GaN HEMT device is connected to the drain of the sixth high-side N-type enhancement-mode GaN HEMT device, and the source is grounded. The gate of the seventh high-side N-type enhancement-mode GaN HEMT device is connected to the drain of the second high-side N-type enhancement-mode GaN HEMT device, the drain is connected to the high-end power supply, and the source serves as the output terminal of the high-side drive circuit, connecting to the drain of the eighth high-side N-type enhancement-mode GaN HEMT device. The gate of the eighth high-side N-type enhancement-mode GaN HEMT device is connected to the drain of the fourth high-side N-type enhancement-mode GaN HEMT device, and the source is grounded.

[0009] A first diode is connected in parallel across the two ends of the first two-dimensional electron gas resistor; a second diode is connected in parallel across the two ends of the fourth two-dimensional electron gas resistor.

[0010] The low-side drive circuit includes a first low-side N-type enhancement-mode gallium nitride HEMT device, a second low-side N-type enhancement-mode gallium nitride HEMT device, a third low-side N-type enhancement-mode gallium nitride HEMT device, and a fourth low-side N-type enhancement-mode gallium nitride HEMT device. The gate of the first low-side N-type enhancement-mode gallium nitride HEMT device serves as the input terminal of the low-side drive circuit and is connected to a low-side drive signal source, the source is grounded, and the drain is connected to one end of a seventh two-dimensional electron gas resistor. The other end of the seventh two-dimensional electron gas resistor is connected to a low-end power supply; the gate of the second low-side N-type enhancement-mode gallium nitride HEMT device is connected to the drain of the first low-side N-type enhancement-mode gallium nitride HEMT device, the source is grounded, and the drain is connected to one end of an eighth two-dimensional electron gas resistor. The other end of the eighth two-dimensional electron gas resistor is connected to the low-end power supply; the gate of the third low-side N-type enhancement-mode gallium nitride HEMT device is connected to the drain of the second low-side N-type enhancement-mode gallium nitride HEMT device, the source serves as the output terminal of the low-side drive circuit and is connected to the drain of the fourth low-side N-type enhancement-mode gallium nitride HEMT device, and the drain is connected to the low-end power supply; the gate of the fourth low-side N-type enhancement-mode gallium nitride HEMT device is connected to the drain of the first low-side N-type enhancement-mode gallium nitride HEMT device, and the source is grounded.

[0011] Beneficial effects

[0012] Due to the adoption of the above technical solution, compared with the prior art, the present invention has the following advantages and positive effects: The present invention can operate at a frequency of 1 MHz or even higher, and has the advantages of small parasitic inductance and small gate oscillation, simplifies the difficulties in the application of gallium nitride devices, and greatly reduces the usage threshold of gallium nitride power devices. Description of the drawings

[0013] Figure 1 is the circuit topology diagram of the embodiment of the present invention;

[0014] Figure 2 is the integrated drive input timing diagram of the embodiment of the present invention;

[0015] Figure 3 is the schematic diagram of the midpoint Vsw voltage of the integrated drive output of the embodiment of the present invention;

[0016] Figure 4 is the schematic diagram of the midpoint Vsw1 and Vsw2 voltages of the full-bridge power conversion module. Specific embodiments

[0017] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of this application.

[0018] An embodiment of the present invention relates to a fully gallium nitride integrated power conversion module, as Figure 1 shown, which includes a low-side drive circuit 1, a high-side drive circuit 2, and a half-bridge module 3.

[0019] Among them, the low-side drive circuit 1 includes: an N-type enhancement-mode GaN HEMT L1, an N-type enhancement-mode GaN HEMT L2, an N-type enhancement-mode GaN HEMT L3, and an N-type enhancement-mode GaN HEMT L4, as well as two-dimensional electron gas resistors R7 and R8. The gate of the N-type enhancement-mode GaN HEMT L1 serves as the input end of the low-side drive circuit, connects to the low-end drive signal source INL, the source terminal is grounded, and the drain terminal connects to one end of the two-dimensional electron gas resistor R7; the other end of the two-dimensional electron gas resistor R7 connects to the low-end power supply VDD1; the gate of the N-type enhancement-mode GaN HEMT L2 connects to the drain terminal of the N-type enhancement-mode GaN HEMT L1, the drain terminal connects to one end of the two-dimensional electron gas resistor R8, and the source terminal is grounded; the other end of the two-dimensional electron gas resistor R8 connects to the low-end power supply VDD1; the gate of the N-type enhancement-mode GaN HEMT L3 connects to the drain terminal of the N-type enhancement-mode GaN HEMT L2, the drain terminal connects to the low-end power supply VDD1, and the source terminal serves as the output end of the low-side drive circuit and connects to the drain terminal of the N-type enhancement-mode GaN HEMT L4; the gate of the N-type enhancement-mode GaN HEMT L4 connects to the drain terminal of the N-type enhancement-mode GaN HEMTL1, the drain terminal connects to the source terminal of the N-type enhancement-mode GaN HEMT L3, and the source terminal is grounded.

[0020] The high-side drive circuit 2 includes: N-type enhancement-mode GaN HEMT H1, N-type enhancement-mode GaN HEMT H2, N-type enhancement-mode GaN HEMT H3, N-type enhancement-mode GaN HEMT H4, N-type enhancement-mode GaN HEMT H5, N-type enhancement-mode GaN HEMT H6, N-type enhancement-mode GaN HEMT H7, and N-type enhancement-mode GaN HEMT H8, as well as two-dimensional electron gas resistors R1, two-dimensional electron gas resistors R2, two-dimensional electron gas resistors R3, two-dimensional electron gas resistors R4, two-dimensional electron gas resistors R5, two-dimensional electron gas resistors R6, diode D1, and diode D2.N-type enhancement-mode GaN HEMT H1, with its gate as the first input terminal of the high-side drive circuit, connected to the high-side drive signal source INHUP, its source terminal connected to one end of the two-dimensional electron gas resistor R5, and its drain terminal connected to one end of the two-dimensional electron gas resistor R1; the other end of the two-dimensional electron gas resistor R1 is connected to the high-end power supply VDD2; the other end of the two-dimensional electron gas resistor R5 is grounded; the anode of the diode D1 is connected to the high-end power supply VDD2, and the cathode is connected to the drain terminal of the N-type enhancement-mode GaN HEMT H1; the gate of the N-type enhancement-mode GaN HEMT H6 is the second input terminal of the high-side drive circuit, connected to the high-side drive signal source INHDOWN, its source terminal connected to one end of the two-dimensional electron gas resistor R6, and its drain terminal connected to one end of the two-dimensional electron gas resistor R4; the other end of the two-dimensional electron gas resistor R4 is connected to the high-end power supply VDD2; the other end of the two-dimensional electron gas resistor R6 is grounded; the anode of the diode D2 is connected to the high-end power supply VDD2, and the cathode is connected to the drain terminal of the N-type enhancement-mode GaN HEMT H6; the gate of the N-type enhancement-mode GaN HEMT H2 is connected to the drain terminal of the N-type enhancement-mode GaN HEMT H4, its drain terminal connected to one end of the two-dimensional electron gas resistor R2, and its source terminal connected to the drain terminal of the N-type enhancement-mode GaN HEMT H3; one end of the two-dimensional electron gas resistor R2 is connected to the drain terminal of the N-type enhancement-mode GaN HEMT H2, and the other end is connected to the high-end power supply VDD2; the gate of the N-type enhancement-mode GaN HEMT H3 is connected to the drain terminal of the N-type enhancement-mode GaN HEMT H1, its drain terminal connected to the source terminal of the N-type enhancement-mode GaN HEMT H2, and its source terminal is grounded; the gate of the N-type enhancement-mode GaN HEMT H4 is connected to the drain terminal of the N-type enhancement-mode GaN HEMT H2, its drain terminal connected to one end of the two-dimensional electron gas resistor R3, and its source terminal connected to the drain terminal of the N-type enhancement-mode GaN HEMT H5; one end of the two-dimensional electron gas resistor R3 is connected to the drain terminal of the N-type enhancement-mode GaN HEMT H4, and the other end is connected to the high-end power supply VDD2; the gate of the N-type enhancement-mode GaN HEMT H5 is connected to the drain terminal of the N-type enhancement-mode GaN HEMT H6, its drain terminal connected to the source terminal of the N-type enhancement-mode GaN HEMT H4, and its source terminal is grounded; the gate of the N-type enhancement-mode GaN HEMT H7 is connected to the drain terminal of the N-type enhancement-mode GaN HEMT H2, its drain terminal connected to the high-end power supply VDD2, and its source terminal is the output terminal of the high-side drive circuit, connected to the drain terminal of the N-type enhancement-mode GaN HEMT H8; the gate of the N-type enhancement-mode GaN HEMT H8 is connected to the drain terminal of the N-type enhancement-mode GaN HEMT H4, its drain terminal connected to the source terminal of the N-type enhancement-mode GaN HEMT H7, and its source terminal is grounded.

[0021] The half-bridge module 3 is composed of a gallium nitride power device P1 and a gallium nitride power device P2. The drain of the gallium nitride power device P1 is connected to a high voltage HV, the source is connected to the drain of the gallium nitride power device P2, and the gate is connected to the output of the high-side drive circuit to control the opening and closing of the gallium nitride power device P1; the source of the gallium nitride power device P2 is grounded, and the gate is connected to the output of the low-side drive circuit to control the opening and closing of the gallium nitride power device P2.

[0022] A complete half-bridge drive cycle includes the following steps: At t0, the high-side pulse inputs INHUP and INHDOWM are low, the low-side input INL is also low, the gate signals of the GaN power devices P1 and P2 are low, and the GaN power devices P1 and P2 are both in the off state. At t1, the low-side input INL turns high, the gate signal of the GaN power device P2 turns high, and the GaN power device P2 turns on. From t2 to t3, the low-side input INL and the high-side pulse inputs INHUP and INHDOWM are all low, at which time the gate signals of the GaN power devices P1 and P2 are low, and the GaN power devices P1 and P2 are both in the off state. This period of time is in the dead time. From t3 to t4, the high-side pulse input INHUP is converted to a high level. After passing through the latch, the gate signal of the gallium nitride power device P1 is converted to a high level, the gallium nitride power device P1 is turned on, and the midpoint output Vsw gradually increases to HV. The gate voltage of the gallium nitride power device P1 is raised to HV+VTH due to the bootstrap capacitor. From t4 to t5, the high-side pulse input INHUP and INHDOWM are low levels. After passing through the latch, the gate voltage and output midpoint voltage Vsw of the gallium nitride power device P1 remain in the previous state. From t5 to t6, the high-side pulse input INHUP is low, and the high-side pulse input INHDOWM is high. After passing through the latch, the gate signal of the gallium nitride power device P1 is converted to HV. At this time, the midpoint output Vsw voltage is still maintained at HV, the Vgs of the gallium nitride power device P1 is less than VTH, and the gallium nitride power device P1 is turned off. At this point, one cycle is completed, and the relevant input timing is as follows: Figure 2 As shown, in the figure, A represents INHUP, B represents INHDOWM, and C represents INL.

[0023] The commercial GaN spice model was used for modeling and simulation using LTspice circuit simulation software. The simulation was performed at a switching frequency of 1MHz. The simulation results are shown in the figure. Figure 3 As shown, it can work normally under the condition of 100V external voltage. Two sets of this integrated power module can form a full-bridge power conversion module. The full-bridge midpoint voltage is as follows Figure 4As shown, it can be seen from the simulation results that the full-bridge power conversion module can also work properly.

[0024] The simulation results confirm the superiority of this embodiment in the direction of gallium nitride drive. The all-gallium-nitride integrated power conversion module of this embodiment can work at a frequency of 1 MHz or even higher, and has the advantages of small parasitic inductance and small gate oscillation, simplifies the difficulties in the application of gallium nitride devices, and greatly reduces the usage threshold of gallium nitride power devices.

Claims

1. A fully gallium nitride integrated power conversion module, characterized in that, It includes a low-side drive circuit, a high-side drive circuit, and a half-bridge module. The half-bridge module includes a first gallium nitride power device and a second gallium nitride power device. The drain of the first gallium nitride power device is connected to a high voltage HV, the source is connected to the drain of the second gallium nitride power device, and the gate is connected to the output terminal of the high-side drive circuit; the source of the second gallium nitride power device is grounded, and the gate is connected to the output terminal of the low-side drive circuit; The high-side drive circuit includes a first input terminal and a second input terminal. The first input terminal is connected to a first high-side drive signal source, and the second input terminal is connected to a second high-side drive signal source; The input terminal of the low-side drive circuit is connected to a low-side drive signal source; Within a complete half-bridge drive cycle, at time t0, the first high-side drive signal source, the second high-side drive signal source, and the low-side drive signal source are all at low level, and the first gallium nitride power device and the second gallium nitride power device are both in the off state; at time t1, the low-side drive signal source turns to high level, and the second gallium nitride power device turns to the on state; From time t2 to t3, the low-side drive signal source, the first high-side drive signal source, and the second high-side drive signal source are all at low level, and the first gallium nitride power device and the second gallium nitride power device are both in the off state; from time t3 to t4, the first high-side drive signal source converts to high level, the first gallium nitride power device turns on, so that the midpoint output of the first gallium nitride power device and the second gallium nitride power device rises to the high voltage HV, and the gate voltage of the first gallium nitride power device rises to the sum of the high voltage HV and the threshold voltage VTH; from time t4 to t5, the first high-side drive signal source and the second high-side drive signal source are at low level, the gate voltage of the first gallium nitride power device, and the midpoint output of the first gallium nitride power device and the second gallium nitride power device maintain the previous state; from time t5 to t6, the first high-side drive signal source is at low level, the second high-side drive signal source is at high level, the gate voltage of the first gallium nitride power device turns to the high voltage HV, the midpoint output of the first gallium nitride power device and the second gallium nitride power device remains at the high voltage HV, the drive voltage Vgs of the first gallium nitride power device is less than the threshold voltage VTH, and the first gallium nitride power device turns off.

2. The fully gallium nitride integrated power conversion module according to claim 1, wherein The high-side drive circuit includes a first high-side N-type enhancement-mode gallium nitride (GaN) HEMT device, a second high-side N-type enhancement-mode GaN HEMT device, a third high-side N-type enhancement-mode GaN HEMT device, a fourth high-side N-type enhancement-mode GaN HEMT device, a fifth high-side N-type enhancement-mode GaN HEMT device, a sixth high-side N-type enhancement-mode GaN HEMT device, a seventh high-side N-type enhancement-mode GaN HEMT device, and an eighth high-side N-type enhancement-mode GaN HEMT device. The gate of the first high-side N-type enhancement-mode GaN HEMT device serves as the first input terminal of the high-side drive circuit and is connected to the first high-side drive signal source. The source is connected to one end of a fifth two-dimensional electron gas resistor, and the drain is connected to one end of a first two-dimensional electron gas resistor. The other end of the first two-dimensional electron gas resistor is connected to the high-end power supply, and the other end of the fifth two-dimensional electron gas resistor is grounded. The gate of the sixth high-side N-type enhancement-mode GaN HEMT device serves as the second input terminal of the high-side drive circuit and is connected to the second high-side drive signal source. The source is connected to one end of a sixth two-dimensional electron gas resistor, and the drain is connected to one end of a fourth two-dimensional electron gas resistor. The other end of the fourth two-dimensional electron gas resistor is connected to the high-end power supply, and the other end of the sixth two-dimensional electron gas resistor is grounded. The gate of the second high-side N-type enhancement-mode GaN HEMT device is connected to the drain of the fourth high-side N-type enhancement-mode GaN HEMT device. The drain is connected to one end of a second two-dimensional electron gas resistor, and the source is connected to the drain of the third high-side N-type enhancement-mode GaN HEMT device. The other end of the second two-dimensional electron gas resistor is connected to the high-end power supply. The gate of the third high-side N-type enhancement-mode GaN HEMT device is connected to the drain of the first high-side N-type enhancement-mode GaN HEMT device, and the source is grounded. The gate of the fourth high-side N-type enhancement-mode GaN HEMT device is connected to the drain of the second high-side N-type enhancement-mode GaN HEMT device. The drain is connected to one end of a third two-dimensional electron gas resistor, and the source is connected to the drain of the fifth high-side N-type enhancement-mode GaN HEMT device. The other end of the third two-dimensional electron gas resistor is connected to the high-end power supply. The gate of the fifth high-side N-type enhancement-mode GaN HEMT device is connected to the drain of the sixth high-side N-type enhancement-mode GaN HEMT device, and the source is grounded. The gate of the seventh high-side N-type enhancement-mode GaN HEMT device is connected to the drain of the second high-side N-type enhancement-mode GaN HEMT device. The drain is connected to the high-end power supply, and the source serves as the output terminal of the high-side drive circuit and is connected to the drain of the eighth high-side N-type enhancement-mode GaN HEMT device. The gate of the eighth high-side N-type enhancement-mode GaN HEMT device is connected to the drain of the fourth high-side N-type enhancement-mode GaN HEMT device, and the source is grounded.

3. The all-gallium nitride integrated power conversion module according to claim 2, wherein A first diode is connected in parallel across the two ends of the first two-dimensional electron gas resistor; a second diode is connected in parallel across the two ends of the fourth two-dimensional electron gas resistor.

4. The all-GaN integrated power conversion module according to claim 1, wherein The low-side drive circuit includes a first low-side N-type enhancement-mode gallium nitride HEMT device, a second low-side N-type enhancement-mode gallium nitride HEMT device, a third low-side N-type enhancement-mode gallium nitride HEMT device, and a fourth low-side N-type enhancement-mode gallium nitride HEMT device. The gate of the first low-side N-type enhancement-mode gallium nitride HEMT device is connected to a low-side drive signal source as the input end of the low-side drive circuit, the source is grounded, and the drain is connected to one end of a seventh two-dimensional electron gas resistor. The other end of the seventh two-dimensional electron gas resistor is connected to a low-end power supply; the gate of the second low-side N-type enhancement-mode gallium nitride HEMT device is connected to the drain of the first low-side N-type enhancement-mode gallium nitride HEMT device, the source is grounded, and the drain is connected to one end of an eighth two-dimensional electron gas resistor. The other end of the eighth two-dimensional electron gas resistor is connected to the low-end power supply; the gate of the third low-side N-type enhancement-mode gallium nitride HEMT device is connected to the drain of the second low-side N-type enhancement-mode gallium nitride HEMT device, the source is used as the output end of the low-side drive circuit and is connected to the drain of the fourth low-side N-type enhancement-mode gallium nitride HEMT device, and the drain is connected to the low-end power supply; the gate of the fourth low-side N-type enhancement-mode gallium nitride HEMT device is connected to the drain of the first low-side N-type enhancement-mode gallium nitride HEMT device, and the source is grounded.

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