LED chip structure and preparation method thereof
By fabricating N-GaN and P-GaN electrodes on the sidewalls of the epitaxial wafer, the loss of the light-emitting area is avoided. Combined with the use of ITO and silicon dioxide layers, the light extraction efficiency and brightness of the LED chip are improved, solving the problem of light-emitting area loss in traditional processes.
Patent Information
- Application Number
- CN202211468152.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-22
- Publication Date
- 2026-01-20
- Estimated Expiration
- 2042-11-22
AI Technical Summary
Traditional LED chip manufacturing processes result in a loss of light-emitting area, leading to low light extraction efficiency and brightness.
N-electrodes are fabricated on the sidewalls of the N-GaN layer and P-electrodes are fabricated on the sidewalls of the P-GaN layer on the diced epitaxial wafer, so that the electrodes do not occupy the area of the light-emitting region. At the same time, ITO layers are deposited on the sidewalls to achieve heat dissipation, and silicon dioxide layers are set on the chip surface to prevent leakage.
It effectively improves light extraction efficiency and brightness, and enhances the stability and reliability of the chip.
Smart Images
Figure CN115939279B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and in particular to an LED chip structure and its fabrication method. Background Technology
[0002] With increasing awareness of energy conservation and environmental protection, GaN (gallium nitride)-based light-emitting diodes (LEDs) have become widely used as a high-efficiency, environmentally friendly, and green new solid-state lighting source due to their long lifespan and environmental benefits. However, the luminous efficacy, brightness, and reliability of GaN LEDs are among the main issues restricting the development of LEDs.
[0003] Traditional LED chip manufacturing processes have become increasingly mature, and the light extraction efficiency of LED chips is mainly affected by the area of the light-emitting region. Since P and N electrodes need to be made on the light-emitting region and the electrodes need to be covered with metal, the area of the light-emitting region is lost.
[0004] Figure 1 This diagram illustrates a conventional LED chip structure, which includes a sapphire substrate 13 and sequentially formed N-GaN layers 11, quantum well layers 14, and P-GaN layers 12, as well as an ITO layer 4 and a silicon dioxide layer 5. Typically, an LED chip has a P-electrode 3 formed on the P-GaN layer 12, followed by an N-electrode 2 formed through etching. This conventional fabrication process results in a loss of light-emitting area, and absorption of reflected and lateral light within the LED chip, leading to low light extraction efficiency and brightness. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide an LED chip structure and its preparation method, which can effectively improve the light extraction efficiency.
[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:
[0007] A method for fabricating an LED chip structure includes the following steps:
[0008] An epitaxial wafer is formed by sequentially forming an N-GaN layer, a quantum well layer, and a P-GaN layer on a sapphire substrate.
[0009] The epitaxial wafer is cut to obtain a cut epitaxial wafer;
[0010] An N-electrode is fabricated on the sidewall of the N-GaN layer on the diced epitaxial wafer, and a P-electrode is fabricated on the sidewall of the P-GaN layer to obtain a completed LED chip.
[0011] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is as follows:
[0012] An LED chip structure, including an epitaxial wafer;
[0013] The epitaxial wafer includes an N-GaN layer and a P-GaN layer disposed on one side of the N-GaN layer;
[0014] The N-GaN layer has an N electrode on one side wall, and the P-GaN layer has a P electrode on one side wall, and the side walls of the N-GaN layer and the P-GaN layer are not on the same plane.
[0015] The beneficial effects of this invention are as follows: an N electrode is prepared on the sidewall of the N-GaN layer on the diced epitaxial wafer, and a P electrode is prepared on the sidewall of the P-GaN layer, so that the electrode no longer occupies the area of the light-emitting region, thereby avoiding the loss of the area of the light-emitting region, maximizing the utilization of the light-emitting area, thereby effectively improving the light extraction efficiency, and thus improving the brightness of the LED chip. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of an existing LED chip structure;
[0017] Figure 2 This is a flowchart illustrating the steps of an LED chip structure fabrication method according to an embodiment of the present invention;
[0018] Figure 3 This is a schematic diagram of an LED chip structure according to an embodiment of the present invention;
[0019] Figure 4 A comparison of the brightness of an LED chip fabricated by an LED chip structure fabrication method according to an embodiment of the present invention and a traditional LED chip under a constant current of 20mA.
[0020] Figure 5 The LED chip fabricated by the LED chip structure fabrication method of this invention, compared with a traditional LED chip under a constant current of 50mA, shows that the optical power of the LED chip increases with aging time t. a A diagram showing the relationship between changes;
[0021] Label Explanation:
[0022] 1. Epitaxial wafer; 11. N-GaN layer; 12. P-GaN layer; 13. Sapphire substrate; 14. Quantum well layer; 2. N electrode; 3. P electrode; 4. ITO layer; 5. Silicon dioxide layer. Detailed Implementation
[0023] To explain in detail the technical content, objectives, and effects of the present invention, the following description is provided in conjunction with the embodiments and accompanying drawings.
[0024] Please refer to Figure 2This invention provides a method for fabricating an LED chip structure, comprising the following steps:
[0025] An epitaxial wafer is formed by sequentially forming an N-GaN layer, a quantum well layer, and a P-GaN layer on a sapphire substrate.
[0026] The epitaxial wafer is cut to obtain a cut epitaxial wafer;
[0027] An N-electrode is fabricated on the sidewall of the N-GaN layer on the diced epitaxial wafer, and a P-electrode is fabricated on the sidewall of the P-GaN layer to obtain a completed LED chip.
[0028] As can be seen from the above description, the beneficial effects of the present invention are as follows: an N electrode is prepared on the sidewall of the N-GaN layer on the diced epitaxial wafer, and a P electrode is prepared on the sidewall of the P-GaN layer, so that the electrode no longer occupies the area of the light-emitting region, thereby avoiding the loss of the area of the light-emitting region, maximizing the utilization of the light-emitting area, thereby effectively improving the light extraction efficiency, and thus improving the brightness of the LED chip.
[0029] Further, the step of fabricating an N-electrode on the sidewall of the N-GaN layer on the diced epitaxial wafer and a P-electrode on the sidewall of the P-GaN layer to obtain the fabricated LED chip includes:
[0030] An N-electrode pattern is prepared on the sidewall of the N-GaN layer on the diced epitaxial wafer using a photoresist mask, and a P-electrode pattern is prepared on the sidewall of the P-GaN layer to obtain an epitaxial wafer with electrode pattern preparation.
[0031] The sidewalls of the N-GaN layer and the sidewalls of the P-GaN layer on the epitaxial wafer after the electrode pattern is prepared are roughened using a photoresist mask and a roughening solution to obtain a roughened epitaxial wafer.
[0032] The photoresist mask on the roughened epitaxial wafer is removed using a wet etching method to obtain the removed epitaxial wafer. N-electrodes and P-electrodes are then fabricated based on the removed epitaxial wafer to obtain the fabricated LED chip.
[0033] As described above, first using a photoresist mask to fabricate electrode patterns on the sidewalls of the N-GaN and P-GaN layers on the diced epitaxial wafer, and then fabricating the N and P electrodes, can more accurately locate the fabrication positions of the N and P electrodes, ensuring that the electrodes do not occupy the area of the light-emitting region.
[0034] Further, the roughening of the sidewalls of the N-GaN layer and the P-GaN layer on the epitaxial wafer after the electrode pattern is prepared using a photoresist mask and a roughening solution to obtain a roughened epitaxial wafer includes:
[0035] The sidewalls of the N-GaN layer and the P-GaN layer on the epitaxial wafer after the electrode pattern is prepared are roughened for 15 to 45 seconds using a photoresist mask and a roughening solution to obtain a roughened epitaxial wafer.
[0036] As described above, roughening the sidewalls of the N-GaN layer and the P-GaN layer for 15–45 seconds increases the friction between the epitaxial wafer and the electrode, thereby ensuring that the electrode can adhere firmly to the sidewall and improving the stability of the chip.
[0037] Further, the step of roughening the sidewalls of the N-GaN layer and the P-GaN layer on the epitaxial wafer after the electrode pattern is prepared using photoresist and roughening solution to obtain the roughened epitaxial wafer includes:
[0038] An ITO layer is deposited on the sidewall of the epitaxial wafer after the electrode pattern is prepared (without the N-electrode pattern and P-electrode pattern), to obtain an epitaxial wafer with an ITO layer.
[0039] The step of removing the photoresist on the roughened epitaxial wafer using a wet etching method to obtain the epitaxial wafer after removal includes:
[0040] The photoresist on the epitaxial wafer with the ITO layer is removed using a wet etching method to obtain the epitaxial wafer after removal.
[0041] As described above, an ITO layer is deposited on the sidewall of the epitaxial wafer after the electrode patterning (without N-electrode and P-electrode patterns) is prepared, and the ITO layer is used to achieve effective heat dissipation.
[0042] Further, the step of depositing an ITO layer on the sidewall of the epitaxial wafer after the electrode patterning (without the N-electrode pattern and P-electrode pattern) to obtain an epitaxial wafer with an ITO layer includes:
[0043] Electron cyclotron resonant sputtering was used to deposit a thickness of [thickness value missing] on the sidewalls of the epitaxial wafer after electrode patterning (without the N-electrode pattern and P-electrode pattern) at a sputtering temperature of 300–400°C. The ITO layer is added to obtain an epitaxial wafer with an ITO layer.
[0044] As described above, it can effectively activate the activity of doped impurities in the P and N electrodes, increase the carrier concentration, and improve the heat dissipation capacity of the chip.
[0045] Further, the step of fabricating N-electrodes and P-electrodes based on the removed epitaxial wafer to obtain the fabricated LED chip includes:
[0046] The ITO layer is annealed on the removed epitaxial wafer to form an epitaxial wafer with an ohmic contact layer.
[0047] An N-electrode is deposited on the sidewall of the N-GaN layer of the epitaxial wafer with the ohmic contact layer, and a P-electrode is deposited on the sidewall of the P-GaN layer.
[0048] A silicon dioxide layer is deposited on the ITO layer of the epitaxial wafer with an ohmic contact layer using a photoresist mask. After deposition, the photoresist mask is removed using a wet etching method to expose the N electrode and the P electrode, thereby obtaining the fabricated LED chip.
[0049] As described above, the use of a silicon dioxide layer can protect the sidewalls, prevent leakage, and thus greatly improve the reliability of the chip.
[0050] Please refer to Figure 3 An LED chip structure, including an epitaxial wafer;
[0051] The epitaxial wafer includes an N-GaN layer and a P-GaN layer disposed on one side of the N-GaN layer;
[0052] The N-GaN layer has an N electrode on one side wall, and the P-GaN layer has a P electrode on one side wall, and the side walls of the N-GaN layer and the P-GaN layer are not on the same plane.
[0053] As can be seen from the above description, the beneficial effects of the present invention are as follows: an N electrode is prepared on the sidewall of the N-GaN layer and a P electrode is prepared on the sidewall of the P-GaN layer, so that the electrode no longer occupies the area of the light-emitting region, thereby avoiding the loss of the area of the light-emitting region, maximizing the utilization of the light-emitting area, thereby effectively improving the light extraction efficiency, and thus improving the brightness of the LED chip.
[0054] Furthermore, the epitaxial wafer also includes a sapphire substrate and a quantum well layer;
[0055] The sapphire substrate is disposed on the other side of the N-GaN layer, and the quantum well layer is disposed between the N-GaN layer and the P-GaN layer.
[0056] As can be seen from the above description, this ensures the basic working performance of the LED chip.
[0057] Furthermore, it also includes the ITO layer;
[0058] The ITO layer is located on the sidewall of the epitaxial layer at a position where the N electrode and the P electrode are not located.
[0059] As described above, an ITO layer is set up to achieve effective heat dissipation.
[0060] Furthermore, it also includes a silicon dioxide layer;
[0061] The silicon dioxide layer is disposed on the side of the ITO layer away from the epitaxial layer.
[0062] As described above, the use of a silicon dioxide layer can protect the sidewalls, prevent leakage, and thus greatly improve the reliability of the chip.
[0063] The LED chip structure and its fabrication method described above are applicable to applications requiring high brightness of LED chips. The following detailed embodiments illustrate these applications:
[0064] Example 1
[0065] Please refer to Figures 2-5 This embodiment of an LED chip structure fabrication method includes the following steps:
[0066] S1. An epitaxial wafer is formed by sequentially forming an N-GaN layer, a quantum well layer, and a P-GaN layer on a sapphire substrate, specifically including:
[0067] S11. An N-GaN layer of 1.5–3.2 μm is grown on a sapphire substrate at a temperature of 1050–1150 °C;
[0068] In one alternative embodiment, a 3.2 μm N-GaN layer is grown on a sapphire substrate at a temperature of 1150 °C.
[0069] In another alternative embodiment, a 1.5 μm N-GaN layer is grown on a sapphire substrate at a temperature of 1050 °C.
[0070] In another alternative implementation, a 2 μm N-GaN layer is grown on a sapphire substrate at a temperature of 1100 °C.
[0071] S12. Reduce the temperature to 820-880°C, and grow 4-10 pairs of 3-6nm GaN layers and 1-3nm InGaN layers on the N-GaN layer to form a 20-100nm quantum well layer.
[0072] In one alternative embodiment, the temperature is lowered to 880°C, and four pairs of 6nm GaN layers and 3nm InGaN layers are grown on the N-GaN layer to form a 100nm quantum well layer.
[0073] In another alternative embodiment, the temperature is reduced to 850°C, and six pairs of 5nm GaN layers and 2nm InGaN layers are grown on the N-GaN layer to form a 50nm quantum well layer.
[0074] In another alternative embodiment, the temperature is reduced to 820°C, and 10 pairs of 3nm GaN layers and 1nm InGaN layers are grown on the N-GaN layer to form a 20nm quantum well layer.
[0075] S13. An initial P-GaN layer of 0.2 to 0.6 μm is grown on the quantum well layer at a temperature of 900 to 1190 °C, and the initial P-GaN layer is annealed in a nitrogen atmosphere at a temperature of 450 to 650 °C to obtain a P-GaN layer, which can effectively activate the activity of doped impurities in the P-GaN layer and increase the carrier concentration of P-GaN.
[0076] In one optional embodiment, an initial P-GaN layer of 0.2 μm is grown on the quantum well layer at a temperature of 900°C, and the initial P-GaN layer is annealed at a temperature of 450°C in a nitrogen atmosphere to obtain a P-GaN layer. This effectively activates the activity of doped impurities in the P-GaN layer and increases the carrier concentration of P-GaN.
[0077] In another alternative embodiment, an initial P-GaN layer of 0.4 μm is grown on the quantum well layer at a temperature of 1000 °C, and the initial P-GaN layer is annealed at a temperature of 500 °C in a nitrogen atmosphere to obtain a P-GaN layer. This effectively activates the activity of doped impurities in the P-GaN layer and increases the carrier concentration of P-GaN.
[0078] In another optional embodiment, an initial P-GaN layer of 0.6 μm is grown on the quantum well layer at a temperature of 1190 °C, and the initial P-GaN layer is annealed at a temperature of 650 °C in a nitrogen atmosphere to obtain a P-GaN layer. This effectively activates the activity of doped impurities in the P-GaN layer and increases the carrier concentration of P-GaN. S2, The epitaxial wafer is diced to obtain a diced epitaxial wafer;
[0079] Specifically, the epitaxial wafer is cut into individual chip sizes using a laser scribing device to obtain the cut epitaxial wafer.
[0080] S3. An N-electrode is fabricated on the sidewall of the N-GaN layer on the diced epitaxial wafer, and a P-electrode is fabricated on the sidewall of the P-GaN layer to obtain the completed LED chip, specifically including:
[0081] S31. Using a photoresist mask, an N-electrode pattern is prepared on the sidewall of the N-GaN layer on the diced epitaxial wafer, and a P-electrode pattern is prepared on the sidewall of the P-GaN layer to obtain an epitaxial wafer with electrode pattern prepared.
[0082] Specifically, using a photoresist positive mask, spin coating, exposure, and development are sequentially performed on the sidewalls of the N-GaN layer on the diced epitaxial wafer to prepare N-electrode patterns, and spin coating, exposure, and development are sequentially performed on the sidewalls of the P-GaN layer to prepare P-electrode patterns, resulting in an epitaxial wafer with electrode patterns prepared.
[0083] S32. Use a photoresist mask and a roughening solution to roughen the sidewalls of the N-GaN layer and the P-GaN layer on the epitaxial wafer after the electrode pattern is prepared, to obtain a roughened epitaxial wafer.
[0084] Specifically, a photoresist mask and a roughening solution are used to roughen the sidewalls of the N-GaN layer corresponding to the N-electrode pattern and the sidewalls of the P-GaN layer corresponding to the P-electrode pattern on the epitaxial wafer after the electrode pattern is fabricated, for 15–45 seconds, resulting in a roughened epitaxial wafer with a serrated surface. Figure 3 As shown.
[0085] In one optional embodiment, a photoresist mask and a roughening solution are used to roughen the sidewalls of the N-GaN layer corresponding to the N-electrode pattern and the sidewalls of the P-GaN layer corresponding to the P-electrode pattern on the epitaxial wafer after the electrode pattern is prepared for 30 seconds to obtain a roughened epitaxial wafer.
[0086] In another optional embodiment, a photoresist mask and a roughening solution are used to roughen the sidewalls of the N-GaN layer corresponding to the N electrode pattern and the sidewalls of the P-GaN layer corresponding to the P electrode pattern on the epitaxial wafer after the electrode pattern is prepared for 15 seconds to obtain a roughened epitaxial wafer.
[0087] In another optional embodiment, a photoresist mask and a roughening solution are used to roughen the sidewalls of the N-GaN layer corresponding to the N electrode pattern and the sidewalls of the P-GaN layer corresponding to the P electrode pattern on the epitaxial wafer after the electrode pattern is prepared for 45 seconds to obtain a roughened epitaxial wafer.
[0088] S33. An ITO layer is deposited on the sidewall of the epitaxial wafer after the electrode pattern is prepared (without the N-electrode pattern and P-electrode pattern), to obtain an epitaxial wafer with an ITO layer.
[0089] Specifically, using electron cyclotron resonance sputtering at a sputtering temperature of 300–400°C, a thickness of [thickness missing] is deposited on the sidewalls of the epitaxial wafer after the electrode patterns have been prepared (before the N and P electrode patterns are prepared). The ITO layer is added to obtain an epitaxial wafer with an ITO layer.
[0090] In one alternative embodiment, electron cyclotron resonant sputtering is used to deposit a thickness of [thickness missing] on the sidewalls of the epitaxial wafer after electrode patterning (before the N-electrode and P-electrode patterns are prepared) at a sputtering temperature of 330°C. The ITO layer is added to obtain an epitaxial wafer with an ITO layer.
[0091] In another alternative embodiment, electron cyclotron resonant sputtering is used to deposit a thickness of [thickness missing] on the sidewalls of the epitaxial wafer after electrode patterning (before the N-electrode and P-electrode patterns are prepared) at a sputtering temperature of 300°C. The ITO layer is added to obtain an epitaxial wafer with an ITO layer.
[0092] In another alternative embodiment, electron cyclotron resonant sputtering is used to deposit a thickness of [thickness missing] on the sidewalls of the epitaxial wafer after electrode patterning (without the N-electrode pattern and P-electrode pattern) at a sputtering temperature of 400°C. The ITO layer is added to obtain an epitaxial wafer with an ITO layer.
[0093] S34. The photoresist mask on the roughened epitaxial wafer is removed using a wet etching method to obtain the removed epitaxial wafer. N-electrodes and P-electrodes are then fabricated based on the removed epitaxial wafer to obtain the completed LED chip. Specifically, this includes:
[0094] S341. The photoresist on the epitaxial wafer with the ITO layer is removed by a wet etching method to obtain the epitaxial wafer after removal;
[0095] S342. Anneal the ITO layer on the removed epitaxial wafer to form an epitaxial wafer with an ohmic contact layer.
[0096] Specifically, the ITO layer is annealed on the removed epitaxial wafer at a temperature of 550–650°C to form an epitaxial wafer with an ohmic contact layer.
[0097] In one alternative embodiment, the ITO layer is annealed on the removed epitaxial wafer at a temperature of 600°C to form an epitaxial wafer with an ohmic contact layer.
[0098] In another alternative embodiment, the ITO layer is annealed at a temperature of 550°C on the removed epitaxial wafer to form an epitaxial wafer with an ohmic contact layer.
[0099] In another alternative embodiment, the ITO layer is annealed at a temperature of 650°C on the removed epitaxial wafer to form an epitaxial wafer with an ohmic contact layer.
[0100] S343. An N electrode is deposited on the sidewall of the N-GaN layer of the epitaxial wafer with the ohmic contact layer, and a P electrode is deposited on the sidewall of the P-GaN layer.
[0101] The electrode is an Au / Cr / Ni metal electrode.
[0102] S344. A silicon dioxide layer is deposited on the ITO layer of the epitaxial wafer with the ohmic contact layer using a photoresist mask, and the photoresist mask is removed by a wet etching method after deposition to expose the N electrode and the P electrode, thereby obtaining the fabricated LED chip.
[0103] Specifically, a silicon dioxide layer is deposited on the ITO layer of the epitaxial wafer with an ohmic contact layer using chemical vapor deposition with a photoresist mask, and the photoresist mask is removed using a wet etching method after deposition to expose the N electrode and the P electrode, thereby obtaining the fabricated LED chip.
[0104] The same epitaxial wafer was cut into two groups of chips, and LED chips were fabricated using both conventional processes and the LED chip structure fabrication method described above. A comparison of brightness changes under a constant current of 20mA was made. Figure 4 As shown. From Figure 4 As can be seen, the brightness of the LED chip prepared by the method of this invention is 1.8 times that of the traditional process; using the current accelerated aging method, two types of LED chips were selected and subjected to a constant current of 50mA at room temperature for 100 hours, and the optical power increased with aging time t a The relationship of change is as follows Figure 5 As shown, from Figure 5 As can be seen, the power decay rate of the sidewall electrode LED chip prepared by the method of the present invention is significantly lower than that of the traditional LED chip structure.
[0105] Example 2
[0106] Please refer to Figure 3 An LED chip structure according to this embodiment includes an epitaxial wafer 1;
[0107] The epitaxial wafer 1 includes an N-GaN layer 11 and a P-GaN layer 12 disposed on one side of the N-GaN layer 11;
[0108] The N-GaN layer 11 has an N electrode 2 on one side wall, and the P-GaN layer 12 has a P electrode 3 on one side wall. The side walls of the N-GaN layer 11 and the P-GaN layer 12 are not on the same plane.
[0109] That is, Figure 3As shown, the surface of the N-GaN layer without other epitaxial structures is the sidewall of the N-GaN layer;
[0110] Specifically, the epitaxial wafer 1 further includes a sapphire substrate 13 and a quantum well layer 14; the sapphire substrate 13 is disposed on the other side of the N-GaN layer 11, and the quantum well layer 14 is disposed between the N-GaN layer 11 and the P-GaN layer 12.
[0111] like Figure 3 As shown, it also includes an ITO layer 4; the ITO layer 4 is disposed on the sidewall of the epitaxial layer 1 at a position where the N electrode 2 and the P electrode 3 are not located.
[0112] Specifically, such as Figure 3 As shown, it also includes a silicon dioxide layer 5; the silicon dioxide layer 5 is disposed on the side of the ITO layer 4 away from the epitaxial layer 1.
[0113] In summary, the present invention provides a method for fabricating an LED chip structure by sequentially forming an N-GaN layer, a quantum well layer, and a P-GaN layer on a sapphire substrate to form an epitaxial wafer; cutting the epitaxial wafer to obtain a cut epitaxial wafer; fabricating an N-electrode on the sidewall of the N-GaN layer and a P-electrode on the sidewall of the P-GaN layer on the cut epitaxial wafer to obtain a fabricated LED chip; an LED chip structure includes an epitaxial wafer; the epitaxial wafer includes an N-GaN layer and a P-GaN layer disposed on one side of the N-GaN layer; an N-electrode is disposed on one sidewall of the N-GaN layer, and a P-electrode is disposed on one sidewall of the P-GaN layer, and the sidewalls of the N-GaN layer and the P-GaN layer are not on the same plane; this allows the electrodes to no longer occupy the light-emitting area, thereby avoiding the loss of the light-emitting area, maximizing the utilization of the light-emitting area, effectively improving the light extraction efficiency, and thus improving the brightness of the LED chip.
[0114] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A method for fabricating an LED chip structure, characterized in that, Including the following steps: An epitaxial wafer is formed by sequentially forming an N-GaN layer, a quantum well layer, and a P-GaN layer on a sapphire substrate. The epitaxial wafer is cut to obtain a cut epitaxial wafer; An N-electrode is fabricated on the sidewall of the N-GaN layer on the diced epitaxial wafer, and a P-electrode is fabricated on the sidewall of the P-GaN layer to obtain a completed LED chip. The process involves fabricating an N-electrode on the sidewall of the N-GaN layer on the diced epitaxial wafer and a P-electrode on the sidewall of the P-GaN layer to obtain a completed LED chip. An N-electrode pattern is prepared on the sidewall of the N-GaN layer on the diced epitaxial wafer using a photoresist mask, and a P-electrode pattern is prepared on the sidewall of the P-GaN layer to obtain an epitaxial wafer with electrode pattern preparation. The sidewalls of the N-GaN layer and the sidewalls of the P-GaN layer on the epitaxial wafer after the electrode pattern is prepared are roughened using a photoresist mask and a roughening solution to obtain a roughened epitaxial wafer. The photoresist mask on the roughened epitaxial wafer is removed using a wet etching method to obtain the removed epitaxial wafer. N-electrodes and P-electrodes are then fabricated based on the removed epitaxial wafer to obtain the fabricated LED chip.
2. The method for fabricating an LED chip structure according to claim 1, characterized in that, The process of roughening the sidewalls of the N-GaN layer and the P-GaN layer on the epitaxial wafer after the electrode pattern is prepared using a photoresist mask and a roughening solution to obtain a roughened epitaxial wafer includes: The sidewalls of the N-GaN layer and the P-GaN layer on the epitaxial wafer after the electrode pattern is prepared are roughened for 15~45s using a photoresist mask and a roughening solution to obtain a roughened epitaxial wafer.
3. The method for fabricating an LED chip structure according to claim 1, characterized in that, The process of roughening the sidewalls of the N-GaN layer and the P-GaN layer on the epitaxial wafer after the electrode pattern is prepared using photoresist and a roughening solution to obtain the roughened epitaxial wafer includes: An ITO layer is deposited on the sidewall of the epitaxial wafer after the electrode pattern is prepared (without the N-electrode pattern and P-electrode pattern), to obtain an epitaxial wafer with an ITO layer. The step of removing the photoresist on the roughened epitaxial wafer using a wet etching method to obtain the epitaxial wafer after removal includes: The photoresist on the epitaxial wafer with the ITO layer is removed using a wet etching method to obtain the epitaxial wafer after removal.
4. The method for fabricating an LED chip structure according to claim 3, characterized in that, The step of depositing an ITO layer on the sidewall of the epitaxial wafer after the electrode patterns (without the N-electrode pattern and P-electrode pattern) to obtain an epitaxial wafer with an ITO layer includes: An ITO layer with a thickness of 1500-2000 Å is deposited on the sidewall of the epitaxial wafer after the electrode patterns have been prepared (without the N-electrode pattern and P-electrode pattern) using electron cyclotron resonant sputtering at a sputtering temperature of 300-400°C, resulting in an epitaxial wafer with an ITO layer.
5. The method for fabricating an LED chip structure according to claim 3, characterized in that, The process of fabricating N-electrodes and P-electrodes based on the removed epitaxial wafer to obtain a completed LED chip includes: The ITO layer is annealed on the removed epitaxial wafer to form an epitaxial wafer with an ohmic contact layer. An N-electrode is deposited on the sidewall of the N-GaN layer of the epitaxial wafer with the ohmic contact layer, and a P-electrode is deposited on the sidewall of the P-GaN layer. A silicon dioxide layer is deposited on the ITO layer of the epitaxial wafer with an ohmic contact layer using a photoresist mask. After deposition, the photoresist mask is removed using a wet etching method to expose the N electrode and the P electrode, thereby obtaining the fabricated LED chip.
6. An LED chip structure, prepared by the LED chip structure preparation method according to any one of claims 1 to 5, characterized in that, Including epitaxial wafers; The epitaxial wafer includes an N-GaN layer and a P-GaN layer disposed on one side of the N-GaN layer; The N-GaN layer has an N electrode on one side wall, and the P-GaN layer has a P electrode on one side wall, and the side walls of the N-GaN layer and the P-GaN layer are not on the same plane.
7. An LED chip structure according to claim 6, characterized in that, The epitaxial wafer also includes a sapphire substrate and a quantum well layer; The sapphire substrate is disposed on the other side of the N-GaN layer, and the quantum well layer is disposed between the N-GaN layer and the P-GaN layer.
8. An LED chip structure according to claim 6, characterized in that, It also includes the ITO layer; The ITO layer is located on the sidewall of the epitaxial wafer at a position where the N electrode and the P electrode are not located.
9. An LED chip structure according to claim 8, characterized in that, It also includes a silicon dioxide layer; The silicon dioxide layer is disposed on the side of the ITO layer away from the epitaxial wafer.