Bus buffer circuit

Abstract

A bus buffer circuit is provided which can prevent a state fixation in the bus buffer circuit to reduce power consumption and temporarily output a potential different from an actual bus signal at a state transition. The bus buffer circuit includes an input buffer circuit which operates with a first power supply to output a non-inverted input signal and an inverted input signal; a voltage conversion circuit which operates with a second power supply to output a voltage-converted non-inverted output signal and a voltage-converted inverted output signal; an output maintenance section which maintains the voltage-converted non-inverted output signal and the voltage-converted inverted output signal at the same potential level when an output enable signal is in an inhibit state; a determination section which determines whether the same potential level is present; a tri-state output buffer circuit which outputs the voltage-converted non-inverted output signal or the voltage-converted inverted output signal; and an output control section which sets the tri-state output buffer circuit to an output inhibit state when the same potential level is present based on a result of the determination section.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-154882 (filed on September 22, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a bus buffer circuit. Background Technology

[0004] Previously, bus buffer circuits were used as the circuits connected to the data bus.

[0005] When multiple nodes are connected on the bus, the bus buffer circuit can set the output to a high impedance state so that nodes that are not in operation will not affect the bus.

[0006] In addition, bus buffer circuits with voltage conversion functions are known as such bus buffer circuits.

[0007] The bus buffer circuit with voltage conversion function includes a voltage conversion circuit and a tri-state output buffer circuit. The voltage conversion circuit has positive input, negative input, positive output and negative output.

[0008] Furthermore, when the internal circuit state is fixed in order to reduce current consumption during operation, the potentials of the positive and negative outputs are kept in opposite phase.

[0009] Furthermore, since the bus buffer circuit does not change state according to the bus signal after its state is fixed, there is no current consumption.

[0010] However, the internal signals, once their states are fixed, can sometimes change to states different from the actual bus input signals. There is concern that when output state transitions are based on output control signals, the output may temporarily output a potential different from the actual bus signal. This is particularly noticeable when the circuit's operating speed decreases significantly at low voltages.

[0011] Even when the internal signal state is fixed, the positive and negative outputs of the voltage conversion circuit can be made to have the same potential. However, if there is a difference between the voltage level of the internal fixed state and the voltage level of the bus input, there is also a concern about the occurrence of temporary erroneous outputs. Summary of the Invention

[0012] This invention provides a bus buffer circuit that can prevent the output from temporarily outputting a potential different from the actual bus signal when the output state changes during a state transition in a bus buffer circuit where the state is fixed to reduce power consumption.

[0013] The bus buffer circuit of the embodiment includes: an input buffer circuit that operates with a first power supply, receives an input signal, and outputs a non-inverting input signal and an inverting input signal; a voltage conversion circuit that operates with a second power supply, converts the voltages of the input non-inverting input signal and the inverting input signal, and outputs them as a voltage-converted non-inverting output signal and a voltage-converted inverting output signal; an output holding unit that maintains the voltage-converted non-inverting output signal and the voltage-converted inverting output signal at the same potential level when the output enable signal is disabled; a determination unit that determines whether the voltage-converted non-inverting output signal and the voltage-converted inverting output signal are at the same potential level; a three-state output buffer circuit that outputs a voltage-converted non-inverting output signal or a voltage-converted inverting output signal from an output terminal; and an output control unit that, based on the result of the determination unit, sets the three-state output buffer circuit to an output disable state when the voltage-converted non-inverting output signal and the voltage-converted inverting output signal are at the same potential level. Attached Figure Description

[0014] Figure 1 This is a schematic block diagram of the bus buffer circuit in the first embodiment.

[0015] Figure 2 This is an explanatory diagram of an example of a voltage conversion circuit structure.

[0016] Figure 3 This is a timing diagram of the first implementation method.

[0017] Figure 4 This is a schematic block diagram of the bus buffer circuit in the second embodiment.

[0018] Figure 5 This is a schematic block diagram of the bus buffer circuit in the third embodiment.

[0019] Figure 6 This is a timing diagram of the third implementation method.

[0020] Figure 7 This is a schematic block diagram of the bus buffer circuit in the fourth embodiment. Detailed Implementation

[0021] The embodiments will now be described with reference to the accompanying drawings.

[0022] [1] First implementation method

[0023] Figure 1 This is a schematic block diagram of the bus buffer circuit in the first embodiment.

[0024] The bus buffer circuit 10 of the embodiment includes: an input buffer circuit 11, which operates with a first power supply, receives an input signal IN, and outputs a non-inverting input signal IN and an inverting input signal / IN; and an output buffer circuit 12, which receives the non-inverting input signal IN and the inverting input signal / IN, operates with a second power supply, performs voltage conversion of the input signal IN, and outputs it as an output signal OUT.

[0025] The input buffer circuit 11 includes: a first inverter 21 that receives an input signal IN at its input terminal, flips the input signal IN, and outputs an inverted input signal / IN from its output terminal; and a second inverter 22 that receives an inverted input signal / IN at its input terminal, flips the inverted input signal / IN, and outputs a non-inverted input signal IN from its output terminal.

[0026] The output buffer circuit 12 has the following structure: a voltage conversion circuit 31, including a non-inverting input terminal A, an inverting input terminal / A, a non-inverting output terminal Y, and an inverting output terminal / Y, which performs voltage conversion on the non-inverting input signal IN input to the non-inverting input terminal A and the inverting input signal / IN input to the inverting input terminal / A, outputs a voltage-converted non-inverting output signal VOUT from the non-inverting output terminal Y, and outputs a voltage-converted inverting output signal / VOUT from the inverting output terminal / Y; and an output sustaining circuit 32, which functions as an output sustaining unit, maintaining the output of the voltage conversion circuit 31 at the same level when the output enable signal OE is in the output inhibited state. Figure 1 In the example, the level is "H" (high); NAND (NAND gate) circuit 33 acts as a judgment unit, determining whether the non-inverting output and inverting output of voltage conversion circuit 31 are at the same potential level; AND (AND gate) circuit 34 acts as an output control unit, and based on the output of NAND circuit 33, when the non-inverting output and inverting output of voltage conversion circuit 31 are at the same potential level, sets the control signal OE' to the disabled state and sets the tri-state output buffer circuit 35 to the output disabled state; the tri-state output buffer circuit 35 has its input terminal connected to the non-inverting output terminal Y, and when the control signal OE' is enabled, outputs the voltage conversion non-inverting signal VOUT as the output signal OUT; and the operating switch (N-channel MOS transistor) 36.

[0027] Here, the structure of the voltage conversion circuit will be explained.

[0028] Figure 2 This is an explanatory diagram of an example of a voltage conversion circuit structure.

[0029] The voltage conversion circuit 31 includes: an N-channel MOS transistor 41, with its gate terminal connected to the non-inverting input terminal A, its drain terminal connected to the inverting output terminal, and its source terminal connected to the low-potential side of the second power supply (in... Figure 2 In the example, the connection is grounded; N-channel MOS transistor 42, the gate terminal is connected to the inverting input terminal / A, the drain terminal is connected to the non-inverting output terminal, and the source terminal is connected to the low-potential side of the second power supply (in... Figure 2 In the example, the connection is grounded; P-channel MOS transistor 43, the gate terminal is connected to the non-inverting output terminal Y, the source terminal is connected to the high-potential side of the second power supply, and the drain terminal is connected to the inverting output terminal / Y; and P-channel MOS transistor 44, the gate terminal is connected to the inverting output terminal / Y, the source terminal is connected to the high-potential side of the second power supply, and the drain terminal is connected to the non-inverting output terminal Y.

[0030] In the above structure, when the input signal IN is at the "H" level, the N-channel MOS transistor 41 is in the on state (closed state). On the other hand, the N-channel MOS transistor 42 is in the off state (open state).

[0031] As a result, the gate terminal of the P-channel MOS transistor 44 becomes "L" level, and the P-channel MOS transistor 44 becomes the on state (closed state).

[0032] As a result, the non-inverting output terminal switches to the "H" level.

[0033] Subsequently, the gate terminal of the P-channel MOS transistor 43 becomes "H" level, and the P-channel MOS transistor 43 becomes the off state (on state).

[0034] Therefore, since N-channel MOS transistor 41 is in the ON state, N-channel MOS transistor 42 is in the OFF state, P-channel MOS transistor 43 is in the OFF state, and P-channel MOS transistor 44 is in the ON state, the non-inverting output terminal Y is at the "H" level, and the inverting output terminal / Y is at the "L" (low) level. Under the logic states of the non-inverting input signal IN and the inverting input signal / IN, the voltage converted from the non-inverting output terminal Y to the "H" level is converted into the non-inverting output signal VOUT, and the voltage converted from the inverting output terminal / Y to the "L" level is converted into the inverting output signal / VOUT.

[0035] Furthermore, when the input signal IN is at the "L" level, the N-channel MOS transistor 41 is in the off state (on state). On the other hand, the N-channel MOS transistor 42 is in the on state (closed state).

[0036] As a result, the gate terminal of the P-channel MOS transistor 44 becomes "H" level, and the P-channel MOS transistor 44 becomes the off state (on state).

[0037] As a result, the non-inverting output terminal switches to the "L" level.

[0038] Subsequently, the gate terminal of the P-channel MOS transistor 43 becomes "L" level, and the P-channel MOS transistor 43 becomes the on state (closed state).

[0039] Therefore, since N-channel MOS transistor 41 is in the off state, N-channel MOS transistor 42 is in the on state, P-channel MOS transistor 43 is in the on state, and P-channel MOS transistor 44 is in the off state, the non-inverting output terminal Y is at the "L" level, and the inverting output terminal / Y is at the "H" level. Under the logic states of the non-inverting input signal IN and the inverting input signal / IN, the voltage converted from the "L" level output from the non-inverting output terminal Y is converted into the non-inverting output signal VOUT, and the voltage converted from the "H" level output from the inverting output terminal / Y is converted into the inverting output signal / VOUT.

[0040] The following describes an example of the structure of the output sustaining circuit 32.

[0041] like Figure 1 As shown, the output sustaining circuit 32 includes a pair of P-channel MOS transistors 51 and 52, whose gate terminals are connected in a common manner, and an output enable signal OE is input to the gate terminals.

[0042] In addition, the source terminal of the P-channel MOS transistor 51 is connected to the high-potential side of the second power supply, and the drain terminal is connected to the inverting output terminal / Y of the voltage conversion circuit 31.

[0043] On the other hand, the source terminal of the P-channel MOS transistor 52 is connected to the high-potential side of the second power supply, and the drain terminal is connected to the non-inverting output terminal Y of the voltage conversion circuit 31.

[0044] As a result of the above structure, when the output enable signal OE is disabled, i.e., when the output enable signal OE = "L" level, the P-channel MOS transistors 51 and 52 become on (closed), and the non-inverting output terminal Y and the inverting output terminal / Y of the voltage conversion circuit 31 are set to the same level (in this case, "H" level).

[0045] Next, the operation of the first embodiment will be explained.

[0046] Figure 3 This is a timing diagram related to the first implementation method.

[0047] At time t0, assume that the output enable signal OE is in the enabled state, that is, the output enable signal OE = "H" level, and the input signal IN is "L" level.

[0048] Since the input signal IN is at the "L" level, from time t0 until time t1 when the output enable signal OE becomes disabled (i.e., the output enable signal OE is at the "L" level), the non-inverting input terminal A of the voltage conversion circuit is at the "L" level, the inverting input terminal / A is at the "H" level, the non-inverting output terminal Y is at the "L" level, and the inverting output terminal / Y is at the "H" level.

[0049] As a result, since one of the inputs of NAND circuit 33 is at the "H" level and the other is at the "L" level, the output signal of NAND circuit 33 is the judgment signal a = "H" level.

[0050] In addition, since one input of the AND circuit 34 is the judgment signal a = "H" level and the other input is the output enable signal OE = "H" level, the output signal of the AND circuit 34, i.e. the control signal OE′ of the tri-state output buffer circuit 35, is in the "H" level enabled state.

[0051] Therefore, the three-state output buffer circuit 35 outputs the input non-inverting output terminal Y as is, outputting an "L" level.

[0052] Subsequently, when the output enable signal OE changes to the disable state at time t1, that is, when the output enable signal OE = "L" level, the P-channel MOS transistors 51 and 52 of the output sustaining circuit 32 become on (closed state), and the non-inverting output terminal Y and the inverting output terminal / Y of the voltage conversion circuit 31 become the same level (in this case, "H" level).

[0053] As a result, since both inputs to NAND circuit 33 become "H" level, the output signal of NAND circuit 33, i.e. the judgment signal a, becomes "L" level.

[0054] In addition, since one input of the AND circuit 34 is the judgment signal a = "L" level and the other input is the output enable signal OE = "L" level, the output signal of the AND circuit 34, i.e. the control signal OE′ of the tri-state output buffer circuit 35, becomes the "L" level disabled state.

[0055] Additionally, at time t2, the output enable signal OE becomes enabled again, i.e., the output enable signal OE = "H" level, and new data is taken into the non-inverting input terminal A and the inverting input terminal / A.

[0056] However, during the period before the signal input to the non-inverting input terminal A is transmitted to the non-inverting output terminal Y, that is, before the change in signal level of the non-inverting input terminal A manifests as a change in signal level of the non-inverting output terminal Y, the non-inverting output terminal Y and the inverting output terminal Y maintain the same level (in Figure 1 In the example, it is the "H" level.

[0057] As a result, since both inputs to NAND circuit 33 become "H" level, the output signal of NAND circuit 33, i.e. the judgment signal a = "L" level, the output signal of AND circuit 34, i.e. the control signal OE′ of tri-state output buffer circuit 35, remains in the "L" level disabled state, and the output terminal OUT remains in a high impedance state.

[0058] Then, at time t3, when the signal input to the non-inverting input terminal A is transmitted to the non-inverting output terminal Y, the non-inverting output terminal Y becomes "L" level.

[0059] As a result, since one of the inputs of NAND circuit 33 becomes "L" level and the other becomes "H" level, the output signal of NAND circuit, i.e. the judgment signal a = "H" level, the output signal of AND circuit 34, i.e. the control signal OE′ of tri-state output buffer circuit 35, becomes the "H" level enabled state, and outputs an "L" level signal from the output terminal OUT.

[0060] As explained above, according to this first embodiment, even if it is desired to release the high-impedance output state by means of the output enable signal OE, which is the output control signal, the high-impedance state of the tri-state output buffer 35 will be maintained during the period when the inverting output terminal Y and the inverting output terminal / Y are at the same level due to the transmission delay, thus reliably preventing erroneous output.

[0061] [2] Second implementation method

[0062] Figure 4 This is a schematic block diagram of the bus buffer circuit in the second embodiment.

[0063] The difference between this second embodiment and the first embodiment is that, in the first embodiment, a NAND circuit 33 is provided, which functions as a determination unit to determine whether the non-inverting output and the inverting output are at the same potential level. However, in this second embodiment, an output buffer circuit 12A is provided instead, which has an EXOR circuit 61 that functions as a determination unit to determine whether the non-inverting output and the inverting output are at the same potential level.

[0064] Regarding other structures, they are the same as in the first embodiment; therefore, while referring to the description of the first embodiment, the operation of the output buffer circuit 12A will be explained.

[0065] The operation of the second embodiment will now be described.

[0066] The timing diagram of the second embodiment is the same as that of the first embodiment, therefore, refer again to... Figure 3 Please provide an explanation.

[0067] At time t0, assume that the output enable signal OE is in the enabled state, that is, the output enable signal OE = "H" level, and the input signal IN is "L" level.

[0068] Since the input signal IN is at the "L" level, from time t0 until time t1 when the output enable signal OE becomes disabled (i.e., the output enable signal OE is at the "L" level), the non-inverting input terminal A of the voltage conversion circuit is at the "L" level, the inverting input terminal / A is at the "H" level, the non-inverting output terminal Y is at the "L" level, and the inverting output terminal / Y is at the "H" level.

[0069] As a result, since one of the inputs to the EXOR circuit 61 is at the "H" level and the other is at the "L" level, the output signal of the EXOR circuit 61 is the judgment signal a = "H" level.

[0070] In addition, since one input of the AND circuit 34 is the judgment signal a = "H" level and the other input is the output enable signal OE = "H" level, the output signal of the AND circuit 34, i.e. the control signal OE′ of the tri-state output buffer circuit 35, is in the "H" level enabled state.

[0071] Therefore, the three-state output buffer circuit 35 outputs the input non-inverting output terminal Y as is, outputting an "L" level.

[0072] Subsequently, when the output enable signal OE changes to the disable state at time t1, that is, when the output enable signal OE = "L" level, the P-channel MOS transistors 51 and 52 of the output sustaining circuit 32 become on (closed state), and the non-inverting output terminal Y and the inverting output terminal / Y of the voltage conversion circuit 31 become the same level (in this case, "H" level).

[0073] As a result, since both inputs to the EXOR circuit 61 become "H" level, the output signal of the EXOR circuit 61, i.e. the judgment signal a, becomes "L" level.

[0074] In addition, since one input of the AND circuit is the judgment signal a = "L" level and the other input is the output enable signal OE = "L" level, the output signal of the AND circuit 34, i.e. the control signal OE′ of the tri-state output buffer circuit 35, becomes the "L" level disabled state.

[0075] Additionally, at time t2, the output enable signal OE becomes enabled again, i.e., the output enable signal OE = "H" level, and new data is taken into the non-inverting input terminal A and the inverting input terminal / A.

[0076] However, during the period before the signal input to the non-inverting input terminal A is transmitted to the non-inverting output terminal Y, the non-inverting output terminal Y and the inverting output terminal / Y maintain the same level (in Figure 4 In the example, it is the "H" level.

[0077] As a result, since both inputs to EXOR circuit 61 become "H" level, the output signal of EXOR circuit 61, i.e. the judgment signal a = "L" level, the output signal of AND circuit 34, i.e. the control signal OE′ of tri-state output buffer circuit 35, remains in the "L" level disabled state, and the output terminal OUT remains in a high impedance state.

[0078] Then, at time t3, when the signal input to the non-inverting input terminal A is transmitted to the non-inverting output terminal Y, the non-inverting output terminal Y becomes "L" level.

[0079] As a result, since one of the inputs to the EXOR circuit 61 becomes "L" level and the other becomes "H" level, the output signal of the EXOR circuit 61, i.e. the judgment signal a = "H" level, the output signal of the AND circuit 34, i.e. the control signal OE′ of the tri-state output buffer circuit 35, becomes the "H" level enabled state, and the "L" level signal is output from the output terminal OUT.

[0080] As explained above, according to this second embodiment, even if it is desired to release the high-impedance output state by means of the output enable signal OE, which is the output control signal, the high-impedance state of the tri-state output buffer will be maintained during the period when the inverting output terminal Y and the inverting output terminal / Y are at the same level due to the transmission delay, thus reliably preventing erroneous output.

[0081] [3] Third implementation method

[0082] In the first and second embodiments described above, when the output enable signal OE changes to the disable state, that is, when the output enable signal OE = "L" level, the P-channel MOS 51 and 52 of the output sustaining circuit 32 become on (closed), thereby setting both the non-inverting output terminal Y and the inverting output terminal / Y of the voltage conversion circuit 31 to the "H" level. However, the third embodiment is an embodiment in which both the non-inverting output terminal Y and the inverting output terminal / Y of the voltage conversion circuit 31 are set to the "L" level.

[0083] Figure 5 This is a schematic block diagram of the bus buffer circuit in the third embodiment.

[0084] In this case, the structure of the input buffer circuit 11, voltage conversion circuit 31, AND circuit 34 and tri-state output buffer circuit 35 is the same as in the first embodiment, and therefore a detailed description thereof is provided.

[0085] The output buffer circuit 12B includes: a voltage conversion circuit 31; and an output sustaining circuit 32A, which functions as an output sustaining unit, maintaining the output of the voltage conversion circuit 31 at the same level when the output enable signal OE is in an output-inhibited state. Figure 5 In the example, the level is "H"; OR (or gate) circuit 65, which acts as a judgment unit to determine whether the non-inverting output and inverting output of voltage conversion circuit 31 are at the same potential level; AND circuit 34; and tri-state output buffer circuit 35.

[0086] First, an example of the structure of the output sustaining circuit 32A will be explained.

[0087] like Figure 5 As shown, the output sustaining circuit 32A includes a pair of N-channel MOS transistors 71 and 72, the gate terminals of the N-channel MOS transistors 71 and 72 are connected in common, and an inverted output enable signal / OE, which is an inverted signal of the output enable signal OE, is input to the gate terminal.

[0088] In addition, the source terminal of the N-channel MOS transistor 71 is connected to the low-potential side power supply (ground) of the second power supply, and the drain terminal is connected to the inverting output terminal / Y of the voltage conversion circuit 31.

[0089] On the other hand, the source terminal of the N-channel MOS transistor 72 is connected to the low-potential side power supply (ground) of the second power supply, and the drain terminal is connected to the non-inverting output terminal Y of the voltage conversion circuit 31.

[0090] As a result of the above structure, when the output enable signal OE is disabled, that is, when the output enable signal OE = "L" level, that is, when the inverting output enable signal / OE = "H" level, the N-channel MOS transistors 71 and 72 become on (closed), and the non-inverting output terminal Y and the inverting output terminal / Y of the voltage conversion circuit 31 are set to the same level (in this case, "L" level).

[0091] Next, the operation of the third embodiment will be explained.

[0092] Figure 6 This is a timing diagram of the third implementation method.

[0093] At time t0, assume that the output enable signal OE is in the enabled state, that is, the output enable signal OE = "H" level, and the input signal IN is "H" level.

[0094] Since the input signal IN is at level "H", from time t0 until time t1 when the output enable signal OE becomes disabled (i.e., the output enable signal OE is at level "L"), the non-inverting input terminal A of the voltage conversion circuit is at level "H", the inverting input terminal / A is at level "L", the non-inverting output terminal Y is at level "H", and the inverting output terminal / Y is at level "L".

[0095] As a result, since one of the inputs to the OR circuit 65 is at the "H" level and the other is at the "L" level, the output signal of the OR circuit 65, i.e. the judgment signal a, is at the "H" level.

[0096] In addition, since one input of the AND circuit 34 is the judgment signal a = "H" level and the other input is the output enable signal OE = "H" level, the output signal of the AND circuit 34, that is, the enable signal OE′ of the output buffer circuit, is in the "H" level enabled state.

[0097] Therefore, the output buffer circuit outputs the input non-inverting output terminal Y as is, outputting the "H" level.

[0098] Subsequently, when the output enable signal OE changes to the disable state at time t1, i.e., when the output enable signal OE = "L" level, it changes to the inverted output enable signal / OE = "H" level. Therefore, the N-channel MOS transistors 71 and 72 of the output sustaining circuit 32A become on (closed state), and the non-inverting output terminal Y and the inverting output terminal / Y of the voltage conversion circuit 31 become the same level (in this case, "L" level).

[0099] As a result, since both inputs to OR circuit 65 become "L" level, the output signal of OR circuit 65, i.e. the judgment signal a, is "L" level.

[0100] In addition, since one input of the AND circuit 34 is the judgment signal a = "L" level and the other input is the output enable signal OE = "L" level, the output signal of the AND circuit 34, i.e. the enable signal OE' of the output buffer circuit, becomes the "L" level disabled state.

[0101] Additionally, at time t2, the output enable signal OE becomes enabled again, i.e., the output enable signal OE = "H" level, and new data is taken into the non-inverting input terminal A and the inverting input terminal / A.

[0102] However, during the period before the signal input to the non-inverting input terminal A is transmitted to the non-inverting output terminal Y, the non-inverting output terminal Y and the inverting output terminal / Y maintain the same level (in Figure 5 In the example, it is the "L" level.

[0103] As a result, since both inputs to OR circuit 65 become "L" level, the output signal of OR circuit 65, i.e. the judgment signal a, is at "L" level. The output signal of AND circuit 34, i.e. the enable signal OE' of the output buffer circuit, remains in the "L" level disabled state, and the output terminal OUT remains in a high impedance state.

[0104] Then, at time t3, when the signal input to the non-inverting input terminal A is transmitted to the non-inverting output terminal Y, the non-inverting output terminal Y becomes "H" level.

[0105] As a result, since one of the inputs of OR circuit 65 becomes "L" level and the other becomes "H" level, the output signal of OR circuit 65, i.e. the judgment signal a = "H" level, the output signal of AND circuit 34, i.e. the enable signal OE′ of the output buffer circuit, becomes the "H" level enabled state, and the "H" level signal is output from the output terminal OUT.

[0106] As explained above, according to this third embodiment, even if it is desired to release the high-impedance output state by means of the output enable signal OE, which is the output control signal, the high-impedance state of the tri-state output buffer will be maintained during the period when the inverting output terminal Y and the inverting output terminal / Y are at the same level due to the transmission delay, thus reliably preventing erroneous output.

[0107] [4] Fourth implementation method

[0108] Figure 7 This is a schematic block diagram of the bus buffer circuit in the fourth embodiment.

[0109] The difference between this fourth embodiment and the third embodiment is that, in the third embodiment, an OR circuit 65 is provided, which functions as a determination unit to determine whether the non-inverting output and the inverting output are at the same potential level. However, in this fourth embodiment, an output buffer circuit 12C is provided instead, which has an EXOR (exclusive OR gate) circuit 75 that functions as a determination unit to determine whether the non-inverting output and the inverting output are at the same potential level.

[0110] Regarding other structures, they are the same as in the third embodiment; therefore, while referring to the description of the third embodiment, the operation of the output buffer circuit 12C will be explained.

[0111] The operation of the fourth embodiment will now be described.

[0112] The timing diagram of the fourth embodiment is the same as that of the third embodiment, therefore, please refer to it again. Figure 6 Please provide an explanation.

[0113] At time t0, assume that the output enable signal OE is in the enabled state, that is, the output enable signal OE = "H" level, and the input signal IN is "H" level.

[0114] Since the input signal IN is at level "H", from time t0 until time t1 when the output enable signal OE becomes disabled (i.e., the output enable signal OE is at level "L"), the non-inverting input terminal A of the voltage conversion circuit is at level "H", the inverting input terminal / A is at level "L", the non-inverting output terminal Y is at level "H", and the inverting output terminal / Y is at level "L".

[0115] As a result, since one of the inputs to the EXOR circuit 75 is at the "H" level and the other is at the "L" level, the output signal of the EXOR circuit 75 is the judgment signal a = "H" level.

[0116] In addition, since one input of the AND circuit 34 is the judgment signal a = "H" level and the other input is the output enable signal OE = "H" level, the output signal of the AND circuit 34, i.e. the control signal OE′ of the tri-state output buffer circuit 35, is in the "H" level enabled state.

[0117] Therefore, the output buffer circuit outputs the input non-inverting output terminal Y as is, outputting the "H" level.

[0118] Subsequently, when the output enable signal OE changes to the disable state at time t1, i.e., the output enable signal OE = "L" level, it changes to the inverted output enable signal OE = "H" level. Therefore, the N-channel MOS transistors 71 and 72 of the output sustaining circuit 32 become on (closed state), and the non-inverting output terminal Y and the inverting output terminal / Y of the voltage conversion circuit 31 become the same level (in this case, "L" level).

[0119] As a result, since both inputs to the EXOR circuit 75 become "L" level, the output signal of the EXOR circuit 75, i.e. the judgment signal a, is "L" level.

[0120] In addition, since one input of the AND circuit 34 is the judgment signal a = "L" level and the other input is the output enable signal OE = "L" level, the output signal of the AND circuit 34, i.e. the control signal OE′ of the tri-state output buffer circuit 35, becomes the "L" level disabled state.

[0121] Additionally, at time t2, the output enable signal OE becomes enabled again, i.e., the output enable signal OE = "H" level, and new data is taken into the non-inverting input terminal A and the inverting input terminal / A.

[0122] However, during the period before the signal input to the non-inverting input terminal A is transmitted to the non-inverting output terminal Y, the non-inverting output terminal Y and the inverting output terminal / Y maintain the same level (in Figure 7 In the example, it is the "L" level.

[0123] As a result, since both inputs to the EXOR circuit 75 become "L" level, the output signal of the EXOR circuit 75, i.e. the judgment signal a, is at the "L" level. The output signal of the AND circuit 34, i.e. the control signal OE′ of the tri-state output buffer circuit 35, remains in the "L" level disabled state, and the output terminal OUT remains in a high impedance state.

[0124] Then, at time t3, when the signal input to the non-inverting input terminal A is transmitted to the non-inverting output terminal Y, the non-inverting output terminal Y becomes "H" level.

[0125] As a result, since one of the inputs to the EXOR circuit 75 becomes "L" level and the other becomes "H" level, the output signal of the EXOR circuit 75, i.e. the judgment signal a = "H" level, the output signal of the AND circuit 34, i.e. the control signal OE′ of the tri-state output buffer circuit 35, becomes the "H" level enabled state, and the "H" level signal is output from the output terminal OUT.

[0126] As explained above, according to this fourth embodiment, even if it is desired to release the high-impedance output state by means of the output enable signal OE, which is the output control signal, the high-impedance state of the tri-state output buffer will be maintained during the period when the inverting output terminal Y and the inverting output terminal / Y are at the same level due to the transmission delay, thus reliably preventing erroneous output.

[0127] While several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and also within the scope of the invention as described in the claims and its equivalents.

[0128] For example, in the above embodiments, the case in which the three-state output buffer circuit 35 outputs the output signal of the non-inverting output terminal Y from the output terminal OUT, i.e., the voltage-converted non-inverting output signal, is described as an example. However, it is also possible to configure the three-state output buffer circuit 35 to connect the inverting output terminal / Y to the input terminal and output the output signal of the inverting output terminal / Y, i.e., the voltage-converted inverting output signal, from the output terminal OUT.

Claims

1. A bus buffer circuit, comprising: Possessing: an input buffer circuit that operates with a first power supply, inputs an input signal, and outputs a non-inverted input signal and an inverted input signal; a voltage conversion circuit that operates with a second power supply, converts the voltage of the input non-inverted input signal and the inverted input signal, and outputs the voltage-converted non-inverted output signal and the voltage-converted inverted output signal; an output maintenance section that maintains the voltage-converted non-inverted output signal and the voltage-converted inverted output signal at the same potential level in the case where an output enable signal is in an inactive state; a determination section that determines whether the voltage-converted non-inverted output signal and the voltage-converted inverted output signal are at the same potential level; a tri-state output buffer circuit that outputs the voltage-converted non-inverted output signal or the voltage-converted inverted output signal from an output terminal; and an output control section that, based on the result of the determination section, sets the tri-state output buffer circuit to an output inactive state in the case where the voltage-converted non-inverted output signal and the voltage-converted inverted output signal are at the same potential level.

2. The bus buffer circuit according to claim 1, wherein the same potential level is either one of an "H" high level or an "L" low level.

3. The bus buffer circuit according to claim 1 or claim 2, wherein the output maintenance section sets the same potential level of the voltage-converted non-inverted output signal and the voltage-converted inverted output signal to an "H" high level, the determination section is configured as a NAND gate circuit.

4. The bus buffer circuit according to claim 1 or claim 2, wherein the output maintenance section sets the same potential level of the voltage-converted non-inverted output signal and the voltage-converted inverted output signal to an "H" high level, the determination section is configured as an EXOR gate circuit.

5. The bus buffer circuit according to claim 1 or claim 2, wherein the output maintenance section sets the same potential level of the voltage-converted non-inverted output signal and the voltage-converted inverted output signal to an "L" low level, the determination section is configured as an OR gate circuit.

6. The bus buffer circuit according to claim 1 or claim 2, wherein the output maintenance section sets the same potential level of the voltage-converted non-inverted output signal and the voltage-converted inverted output signal to an "L" low level, the determination section is configured as an EXOR gate circuit.

7. The bus buffer circuit according to claim 3, wherein the output control section is configured as an AND gate circuit, an output signal of the determination section is input to one input terminal of the AND gate circuit, and the output enable signal is input to the other input terminal of the AND gate circuit.

8. The bus buffer circuit according to claim 4, wherein the output control section is configured as an AND gate circuit, an output signal of the determination section is input to one input terminal of the AND gate circuit, and the output enable signal is input to the other input terminal of the AND gate circuit.

9. The bus buffer circuit according to claim 5, wherein ​ The output control section is configured as an AND gate circuit, and the output signal of the judging section is input to one input terminal of the AND gate circuit, and the output enable signal is input to the other input terminal of the AND gate circuit.

10. The bus buffer circuit of claim 6, wherein, The output control section is configured as an AND gate circuit, and the output signal of the judging section is input to one input terminal of the AND gate circuit, and the output enable signal is input to the other input terminal of the AND gate circuit.

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