An elevator brake unit circuit realizing complex logic control function

Abstract

The elevator brake unit circuit realizing the complex logic control function provided by the present invention is a pure hardware circuit, including a host synchronization signal input module, an overcurrent and overtemperature detection module, a bus voltage detection module, an IGBT short-circuit fault detection module, a main and auxiliary machine indication module, and an IGBT drive signal output module. The host synchronization signal input module is electrically connected to the overcurrent and overtemperature detection module, the bus voltage detection module, and the IGBT short-circuit fault detection module; the overcurrent and overtemperature detection module and the main and auxiliary machine indication module are electrically connected to the IGBT short-circuit fault detection module; the main and auxiliary machine indication module is electrically connected to the bus voltage detection module and the IGBT drive signal output module. The elevator brake unit circuit realizing the complex logic control function provided by the present invention adopts a full electronic hardware design, eliminates the conventional electronic software design, saves manpower, and simplifies the circuit.

Description

Technical Field

[0001] The invention relates to the technical field of elevator braking, and in particular to an elevator braking unit circuit realizing a complex logic control function. Background Art

[0002] Elevators play an increasingly important role in people's daily lives and are used in more and more occasions.

[0003] The safety issue in the use of elevators is an issue that people are more concerned about.

[0004] At present, the brake unit of the elevator system is usually realized by combining the design of electronic hardware and electronic software. However, the design of electronic hardware and electronic software involves a lot of work, and product development requires a lot of manpower.

[0005] Therefore, it is necessary to provide an elevator braking unit circuit that realizes complex logic control functions to solve the above technical problems. Summary of the invention

[0006] The main technical problem solved by the present invention is to provide an elevator brake unit circuit that realizes complex logic control functions, adopts a full electronic hardware design, omits conventional electronic software design, saves manpower, and simplifies the circuit.

[0007] In order to solve the above technical problems, the first technical solution adopted by the present invention is to provide an elevator braking unit circuit that realizes complex logic control functions. The elevator braking unit circuit that realizes complex logic control functions is a pure hardware circuit, including a host synchronization signal input module 10, an overcurrent and overtemperature detection module 20, a bus voltage detection module 30, an IGBT short-circuit fault detection module 40, a main and auxiliary machine indication module 50, and an IGBT drive signal output module 60. The host synchronization signal input module 10 is electrically connected to the overcurrent and overtemperature detection module 20, the bus voltage detection module 30 and the IGBT short-circuit fault detection module 40; the overcurrent and overtemperature detection module 20 and the main and auxiliary machine indication module 50 are electrically connected to the IGBT short-circuit fault detection module 40; the main and auxiliary machine indication module 50 is electrically connected to the bus voltage detection module 30 and the IGBT drive signal output module 60.

[0008] In one embodiment, the host synchronization signal input module 10 includes a parallel input signal terminal PI; the IGBT driving signal output module 60 includes a parallel output signal terminal PO and a parallel common signal terminal COM.

[0009] In one embodiment, the host synchronization signal input module 10 includes a host synchronization signal input unit, a U3A NAND gate, a U3B NAND gate, and a U3C NAND gate; the output signal of the host synchronization signal input unit is connected to the second input pin of the U3A NAND gate, the first input pin of the U3A NAND gate is connected to the master-slave indication module 50, the third output pin of the U3A NAND gate is connected to the fifth input pin of the U3B NAND gate, the fourth input pin of the U3B NAND gate is connected to the bus voltage detection module 30, the sixth output pin of the U3B NAND gate is connected to the ninth input pin of the U3C NAND gate, the tenth input pin of the U3C NAND gate is connected to the overcurrent and overtemperature detection module 20, and the eighth output pin of the U3C NAND gate is connected to the IGBT short circuit fault detection module 40 and the master-slave indication module 50.

[0010] In one embodiment, the bus voltage detection module 30 includes a master / slave setting switch SW1 and a U2D NAND gate. The master / slave setting switch SW1 is connected in series between the ground line and the twelfth input pin of the U2D NAND gate. The thirteenth input pin of the U2D NAND gate is connected to the bus voltage detection terminal. The eleventh output pin of the U2D NAND gate is connected to the fourth input pin of the U3B NAND gate. The twelfth input pin of the U2D NAND gate is connected to the master / slave indication module 50.

[0011] In one embodiment, the main and auxiliary machine indication module 50 includes a U1B NOT gate, a U2B NAND gate, a U2A NAND gate, a main machine indicator LED1, and an auxiliary machine indicator LED2;

[0012] The twelfth input pin of the U2D NAND gate is connected to the third input pin of the U1B NAND gate, the first input pin of the U2A NAND gate, and the VCC input pin of the U2A NAND gate through the third resistor R3, and the VCC input pin of the U2A NAND gate is connected to +5V DC; the fourth output pin of the U1B NAND gate is connected to the fifth input pin of the U2B NAND gate and the first input pin of the U3A NAND gate;

[0013] The GND pin of the U2A NAND gate is grounded; the host indicator LED1 and the first resistor R1 are connected in series, one end is connected to +5V DC, and the other end is connected to the third output pin of the U2A NAND gate; the slave indicator LED2 and the second resistor R2 are connected in series, one end is connected to +5V DC, and the other end is connected to the sixth output pin of the U2B NAND gate;

[0014] The fourth input pin of the U2B NAND gate is connected to the second input pin of the U2A NAND gate, the input end of the IGBT short-circuit fault detection module 40 , and the input end of the IGBT drive signal output module 60 .

[0015] In one embodiment, the IGBT short circuit fault detection module 40 includes a U2C NAND gate, a U1E NAND gate, and a U1D NAND gate; the ninth input pin of the U1D NAND gate is connected to the IGBT short circuit detection terminal, the eighth output pin is connected to the ninth input pin of the U2C NAND gate, and the tenth input pin of the U2C NAND gate is connected to the fourth input pin of the U2B NAND gate; the eighth output pin of the U2C NAND gate is connected to the eleventh input pin of the U1E NAND gate through the fourth resistor R4, and the eleventh input pin of the U1E NAND gate is grounded through the first capacitor C1, the tenth output pin of the U1E NAND gate is connected to the IGBT short circuit fault terminal, the IGBT short circuit fault terminal is connected to the anode of the fourth semiconductor diode D4, the cathode of the fourth semiconductor diode D4 is connected to one end of the twelfth resistor R12, the other end of the twelfth resistor R12 is connected to the anode of the red light emitting diode LED3, and the cathode of the red light emitting diode LED3 is grounded.

[0016] In one embodiment, the over-current and over-temperature detection module 20 includes a U4C NAND gate, a U4D NAND gate, a U5B NAND gate, a U4A NAND gate, a U4B NAND gate, a U3D NAND gate, a U5D NAND gate, a U5C NAND gate, a fifth semiconductor diode D5, and a third semiconductor diode D3;

[0017] +5V DC is connected to one end of the eleventh resistor R11 and the cathode of the third semiconductor diode D3; the anode of the third semiconductor diode D3 is connected to the other end of the eleventh resistor R11 and is grounded through the fourth capacitor C4; the anode of the third semiconductor diode D3 is connected to the twelfth input pin of the U3D NAND gate, the fourth input pin of the U4B NAND gate, and the tenth input pin of the U4C NAND gate;

[0018] The ninth input pin of the U4C NAND gate is connected to the eleventh output pin of the U4D NAND gate, and is also connected to the third input pin of the U5B NAND gate. The eighth output pin of the U4C NAND gate is connected to the twelfth input pin of the U4D NAND gate. The thirteenth input pin of the U4D NAND gate is connected to the IGBT overcurrent detection terminal. The eleventh output pin of the U4D NAND gate is connected to the third input pin of the U5B NAND gate. The fourth output pin of the U5B NAND gate is connected to the first input pin of the U4A NAND gate.

[0019] The second input pin of the U4A NAND gate is connected to the temperature detection terminal, the VCC input pin of the U4A NAND gate is connected to +5V DC, the GND pin is grounded, the third output pin is connected to the fifth input pin of the U4B NAND gate, the sixth output pin of the U4B NAND gate is connected to the thirteenth input pin of the U3D NAND gate, the eleventh output pin of the U3D NAND gate is connected to the ninth input pin of the U5D NAND gate, and the eighth output pin of the U5D NAND gate is connected to the tenth input pin of the U3C NAND gate; the sixth output pin of the U4B NAND gate is connected to the fifth input pin of the U5C NAND gate, the sixth output pin of the U5C NAND gate is connected to the overheating / IGBT overcurrent fault terminal and the anode of the fifth semiconductor diode D5, and the cathode of the fifth semiconductor diode D5 is connected to the cathode of the fourth semiconductor diode D4.

[0020] In one embodiment, the host synchronization signal input unit includes an eighth resistor R8, a ninth resistor R9, a fifth capacitor C5, a first voltage zener diode ZD1, a seventh photocoupler U7, and a tenth resistor R10;

[0021] After the ninth resistor R9 and the fifth capacitor C5 are connected in parallel, one end is connected to the VCC voltage input terminal through the eighth resistor R8, and the other end is connected to the parallel input signal terminal PI and the cathode of the seventh photocoupler U7. The one end of the ninth resistor R9 is connected to the cathode of the first voltage zener diode ZD1, the anode of the first voltage zener diode ZD1 is connected to the anode of the seventh photocoupler U7, the collector of the seventh photocoupler U7 is connected to +5V DC, the emitter of the seventh photocoupler U7 is grounded through the tenth resistor R10, and the emitter of the seventh photocoupler U7 is connected to the second input pin of the U3A NAND gate.

[0022] In one embodiment, the IGBT drive signal output module 60 includes a second semiconductor diode D2, an NPN transistor Q1, a third capacitor C3, a seventh resistor R7, a first semiconductor diode D1, a fifth resistor R5, a sixth photocoupler U6, a second capacitor C2, a sixth resistor R6, and a U1C NOT gate;

[0023] The parallel output signal terminal PO is connected to the cathode of the second semiconductor diode D2, the anode of the first semiconductor diode D1, and the collector of the NPN transistor Q1;

[0024] The anode of the second semiconductor diode D2 is grounded, connected in parallel to the common signal terminal COM and the emitter of the NPN transistor Q1, one end of the third capacitor C3, and one end of the seventh resistor R7; the base of the NPN transistor Q1 is connected to the other end of the third capacitor C3 and the seventh resistor R7, and the emitter of the sixth photocoupler U6; the collector of the sixth photocoupler U6 is connected to the VCC voltage input terminal and the cathode of the first semiconductor diode D1 through the fifth resistor R5;

[0025] A second capacitor C2 is connected between the anode and cathode of the sixth photocoupler U6, and the anode of the sixth photocoupler U6 is connected to the sixth output pin of the U1C NOT gate through the sixth resistor R6, the fifth input pin of the U1C NOT gate is connected to the second input pin of the U2A NAND gate, and the sixth output pin of the U1C NOT gate is connected to the IGBT drive signal terminal.

[0026] The beneficial effects of the present invention are:

[0027] (1) The all-electronic hardware design eliminates the need for conventional electronic software design, saves manpower, and simplifies the circuit;

[0028] (2) Furthermore, through the design of logic circuits, it can process 6 input signals and 8 output signals at the same time, with complete functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the circuit connection structure of the elevator brake unit circuit realizing the complex logic control function of the present invention;

[0030] Figure 2 There are two Figure 1 The schematic diagram of the parallel circuit shown. DETAILED DESCRIPTION

[0031] The technical solution of the present invention is described in detail below with reference to the accompanying drawings.

[0032] like Figure 1 The elevator braking unit circuit 100 for realizing complex logic control function is shown. The elevator braking unit circuit for realizing complex logic control function is a pure hardware circuit, including a host synchronization signal input module 10, an overcurrent and overtemperature detection module 20, a bus voltage detection module 30, an IGBT short-circuit fault detection module 40, a main and auxiliary machine indication module 50, and an IGBT drive signal output module 60. The host synchronization signal input module 10 is electrically connected to the overcurrent and overtemperature detection module 20, the bus voltage detection module 30 and the IGBT short-circuit fault detection module 40; the overcurrent and overtemperature detection module 20 and the main and auxiliary machine indication module 50 are electrically connected to the IGBT short-circuit fault detection module 40; the main and auxiliary machine indication module 50 is electrically connected to the bus voltage detection module 30 and the IGBT drive signal output module 60.

[0033] like Figure 1 As shown, the host synchronization signal input module 10 includes a parallel input signal terminal PI; the IGBT drive signal output module 60 includes a parallel output signal terminal PO and a parallel common signal terminal COM.

[0034] like Figure 1 As shown, the host synchronization signal input module 10 includes a host synchronization signal input unit, a U3A NAND gate, a U3B NAND gate, and a U3C NAND gate; the output signal of the host synchronization signal input unit is connected to the second input pin of the U3A NAND gate, the first input pin of the U3A NAND gate is connected to the master-slave indication module 50, the third output pin of the U3A NAND gate is connected to the fifth input pin of the U3B NAND gate, the fourth input pin of the U3B NAND gate is connected to the bus voltage detection module 30, the sixth output pin of the U3B NAND gate is connected to the ninth input pin of the U3C NAND gate, the tenth input pin of the U3C NAND gate is connected to the overcurrent and overtemperature detection module 20, and the eighth output pin of the U3C NAND gate is connected to the IGBT short circuit fault detection module 40 and the master-slave indication module 50.

[0035] like Figure 1As shown, the bus voltage detection module 30 includes a master / slave setting switch SW1 and a U2D NAND gate. The master / slave setting switch SW1 is connected in series between the ground line and the twelfth input pin of the U2D NAND gate. The thirteenth input pin of the U2D NAND gate is connected to the bus voltage detection terminal. The eleventh output pin of the U2D NAND gate is connected to the fourth input pin of the U3B NAND gate. The twelfth input pin of the U2D NAND gate is connected to the master / slave indication module 50.

[0036] like Figure 1 As shown, the main and auxiliary machine indication module 50 includes a U1B NOT gate, a U2B NAND gate, a U2A NAND gate, a main machine indicator LED1, and an auxiliary machine indicator LED2;

[0037] The twelfth input pin of the U2D NAND gate is connected to the third input pin of the U1B NAND gate, the first input pin of the U2A NAND gate, and the VCC input pin of the U2A NAND gate through the third resistor R3, and the VCC input pin of the U2A NAND gate is connected to +5V DC; the fourth output pin of the U1B NAND gate is connected to the fifth input pin of the U2B NAND gate and the first input pin of the U3A NAND gate;

[0038] The GND pin of the U2A NAND gate is grounded; the host indicator LED1 and the first resistor R1 are connected in series, one end is connected to +5V DC, and the other end is connected to the third output pin of the U2A NAND gate; the slave indicator LED2 and the second resistor R2 are connected in series, one end is connected to +5V DC, and the other end is connected to the sixth output pin of the U2B NAND gate;

[0039] The fourth input pin of the U2B NAND gate is connected to the second input pin of the U2A NAND gate, the input end of the IGBT short-circuit fault detection module 40 , and the input end of the IGBT drive signal output module 60 .

[0040] like Figure 1 As shown, the IGBT short-circuit fault detection module 40 includes a U2C NAND gate, a U1E NAND gate, and a U1D NAND gate; the ninth input pin of the U1D NAND gate is connected to the IGBT short-circuit detection terminal, the eighth output pin is connected to the ninth input pin of the U2C NAND gate, and the tenth input pin of the U2C NAND gate is connected to the fourth input pin of the U2B NAND gate; the eighth output pin of the U2C NAND gate is connected to the eleventh input pin of the U1E NAND gate through the fourth resistor R4, and the eleventh input pin of the U1E NAND gate is grounded through the first capacitor C1, the tenth output pin of the U1E NAND gate is connected to the IGBT short-circuit fault terminal, the IGBT short-circuit fault terminal is connected to the anode of the fourth semiconductor diode D4, the cathode of the fourth semiconductor diode D4 is connected to one end of the twelfth resistor R12, the other end of the twelfth resistor R12 is connected to the anode of the red light emitting diode LED3, and the cathode of the red light emitting diode LED3 is grounded.

[0041] like Figure 1As shown, the over-current and over-temperature detection module 20 includes U4C NAND gate, U4D NAND gate, U5B NAND gate, U4A NAND gate, U4B NAND gate, U3D NAND gate, U5D NAND gate, U5C NAND gate, a fifth semiconductor diode D5, and a third semiconductor diode D3;

[0042] +5V DC is connected to one end of the eleventh resistor R11 and the cathode of the third semiconductor diode D3; the anode of the third semiconductor diode D3 is connected to the other end of the eleventh resistor R11 and is grounded through the fourth capacitor C4; the anode of the third semiconductor diode D3 is connected to the twelfth input pin of the U3D NAND gate, the fourth input pin of the U4B NAND gate, and the tenth input pin of the U4C NAND gate;

[0043] The ninth input pin of the U4C NAND gate is connected to the eleventh output pin of the U4D NAND gate, and is also connected to the third input pin of the U5B NAND gate. The eighth output pin of the U4C NAND gate is connected to the twelfth input pin of the U4D NAND gate. The thirteenth input pin of the U4D NAND gate is connected to the IGBT overcurrent detection terminal. The eleventh output pin of the U4D NAND gate is connected to the third input pin of the U5B NAND gate. The fourth output pin of the U5B NAND gate is connected to the first input pin of the U4A NAND gate.

[0044] The second input pin of the U4A NAND gate is connected to the temperature detection terminal, the VCC input pin of the U4A NAND gate is connected to +5V DC, the GND pin is grounded, the third output pin is connected to the fifth input pin of the U4B NAND gate, the sixth output pin of the U4B NAND gate is connected to the thirteenth input pin of the U3D NAND gate, the eleventh output pin of the U3D NAND gate is connected to the ninth input pin of the U5D NAND gate, and the eighth output pin of the U5D NAND gate is connected to the tenth input pin of the U3C NAND gate; the sixth output pin of the U4B NAND gate is connected to the fifth input pin of the U5C NAND gate, the sixth output pin of the U5C NAND gate is connected to the overheating / IGBT overcurrent fault terminal and the anode of the fifth semiconductor diode D5, and the cathode of the fifth semiconductor diode D5 is connected to the cathode of the fourth semiconductor diode D4.

[0045] like Figure 1 As shown, the host synchronization signal input unit includes an eighth resistor R8, a ninth resistor R9, a fifth capacitor C5, a first voltage zener diode ZD1, a seventh photocoupler U7, and a tenth resistor R10;

[0046] After the ninth resistor R9 and the fifth capacitor C5 are connected in parallel, one end is connected to the VCC voltage input terminal through the eighth resistor R8, and the other end is connected to the parallel input signal terminal PI and the cathode of the seventh photocoupler U7. The one end of the ninth resistor R9 is connected to the cathode of the first voltage zener diode ZD1, the anode of the first voltage zener diode ZD1 is connected to the anode of the seventh photocoupler U7, the collector of the seventh photocoupler U7 is connected to +5V DC, the emitter of the seventh photocoupler U7 is grounded through the tenth resistor R10, and the emitter of the seventh photocoupler U7 is connected to the second input pin of the U3A NAND gate.

[0047] In one embodiment, the IGBT drive signal output module 60 includes a second semiconductor diode D2, an NPN transistor Q1, a third capacitor C3, a seventh resistor R7, a first semiconductor diode D1, a fifth resistor R5, a sixth photocoupler U6, a second capacitor C2, a sixth resistor R6, and a U1C NOT gate;

[0048] The parallel output signal terminal PO is connected to the cathode of the second semiconductor diode D2, the anode of the first semiconductor diode D1, and the collector of the NPN transistor Q1;

[0049] The anode of the second semiconductor diode D2 is grounded, connected in parallel to the common signal terminal COM and the emitter of the NPN transistor Q1, one end of the third capacitor C3, and one end of the seventh resistor R7; the base of the NPN transistor Q1 is connected to the other end of the third capacitor C3 and the seventh resistor R7, and the emitter of the sixth photocoupler U6; the collector of the sixth photocoupler U6 is connected to the VCC voltage input terminal and the cathode of the first semiconductor diode D1 through the fifth resistor R5;

[0050] A second capacitor C2 is connected between the anode and cathode of the sixth photocoupler U6, and the anode of the sixth photocoupler U6 is connected to the sixth output pin of the U1C NOT gate through the sixth resistor R6, the fifth input pin of the U1C NOT gate is connected to the second input pin of the U2A NAND gate, and the sixth output pin of the U1C NOT gate is connected to the IGBT drive signal terminal.

[0051] like Figure 1 and Figure 2 As shown, the first preferred embodiment of the present invention is mainly designed with NOT gate and NAND gate chips, which can realize 8 kinds of logic functions, as shown in Table 1, namely, normal operation of the host, host overheating fault, host overcurrent fault, host short circuit fault, normal operation of the auxiliary machine, auxiliary machine overheating fault, auxiliary machine overcurrent fault, and auxiliary machine short circuit fault. These 8 kinds of logic functions will have different output signals under different input signals, thereby realizing corresponding functions. As can be seen from Table 1, this design can set the host and auxiliary machine. The working principle is as follows Figure 1 As shown, when Figure 1When the circuit shown is set as the host, the host / slave setting switch SW1 is disconnected, the slave indicator LED2 is off, the host indicator LED1 and the IGBT drive signal terminal are affected by the bus voltage detection signal, the overheating / IGBT overcurrent fault signal 17 is affected by the temperature detection signal 13 or the IGBT overcurrent detection signal 12, and the temperature detection signal 13 or the IGBT overcurrent detection signal 12 also affects the fault indicator LED3, the IGBT short circuit fault signal 18 is affected by the IGBT short circuit detection signal 14 and the bus voltage detection signal 10, but the host synchronization signal 11 has no effect on the output signal of the host. When the brake unit is set as the slave, the SW1 switch is closed, the host indicator LED1 is off, the slave indicator LED1 and the IGBT drive signal 16 are affected by the host synchronization signal 11, the bus voltage detection signal 10 has no effect on the IGBT drive signal 16, the signal of the overheating / IGBT overcurrent fault terminal is affected by the temperature detection signal terminal or the IGBT overcurrent detection signal terminal, and the temperature detection signal terminal or the IGBT overcurrent detection signal terminal also affects the fault indicator LED3, and the IGBT short-circuit fault signal terminal is affected by the IGBT short-circuit detection signal terminal and the host synchronization signal terminal. Please refer to Table 1 for detailed logic functions.

[0052] The circuit of this design adds a soft start circuit (including an eleventh resistor R11, a fourth capacitor C4 and a third semiconductor diode D3) to the twelfth input pin of the NAND gate U3D, the fourth input pin of the NAND gate U4B and the tenth input pin of the NAND gate U4C, which can effectively prevent false triggering of overheating / IGBT overcurrent faults.

[0053] Figure 1 The design of the circuit shown allows two or more main units and slave units to be connected in parallel. The power of the circuit can be increased by connecting multiple units in parallel. Figure 1 As shown, the parallel connection of the host and slave requires three signals, namely the parallel output signal PO, the parallel input signal PI and the parallel common signal COM. The electrical connection method is as follows Figure 2 shown.

[0054] Table 1 below shows Figure 1 Logic function table of the circuit shown

[0055]

[0056] Note: H is high level, L is low level, and X is high level or low level.

[0057] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure made using the contents of the present invention's specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An elevator brake unit circuit realizing complex logic control function, characterized in that: The elevator braking unit circuit realizing the complex logic control function is a pure hardware circuit, comprising a host synchronous signal input module (10), an overcurrent and overtemperature detection module (20), a bus voltage detection module (30), an IGBT short-circuit fault detection module (40), a main and auxiliary machine indication module (50), and an IGBT drive signal output module (60); the host synchronous signal input module (10) is electrically connected to the overcurrent and overtemperature detection module (20), the bus voltage detection module (30), and the IGBT short-circuit fault detection module (40); the overcurrent and overtemperature detection module (20) and the main and auxiliary machine indication module (50) are electrically connected to the IGBT short-circuit fault detection module (40); and the main and auxiliary machine indication module (50) is electrically connected to the bus voltage detection module (30) and the IGBT drive signal output module (60); The host synchronous signal input module (10) comprises a parallel input signal terminal (PI); the IGBT drive signal output module (60) comprises a parallel output signal terminal (PO) and a parallel common signal terminal (COM); The host synchronization signal input module (10) comprises a host synchronization signal input unit, a U3A NAND gate, a U3B NAND gate, and a U3C NAND gate; the output signal of the host synchronization signal input unit is connected to the second input pin of the U3A NAND gate, the first input pin of the U3A NAND gate is connected to the host and auxiliary machine indication module (50), the third output pin of the U3A NAND gate is connected to the fifth input pin of the U3B NAND gate, the fourth input pin of the U3B NAND gate is connected to the bus voltage detection module (30), the sixth output pin of the U3B NAND gate is connected to the ninth input pin of the U3C NAND gate, the tenth input pin of the U3C NAND gate is connected to the overcurrent and overtemperature detection module (20), and the eighth output pin of the U3C NAND gate is connected to the IGBT short circuit fault detection module (40) and the host and auxiliary machine indication module (50); The bus voltage detection module (30) comprises a master / slave setting switch (SW1) and a U2D NAND gate, the master / slave setting switch (SW1) is connected in series between a ground line and the twelfth input pin of the U2D NAND gate, the thirteenth input pin of the U2D NAND gate is connected to the bus voltage detection terminal, the eleventh output pin of the U2D NAND gate is connected to the fourth input pin of the U3B NAND gate, and the twelfth input pin of the U2D NAND gate is connected to the master / slave indication module (50); The main and auxiliary machine indication module (50) comprises a U1B NOT gate, a U2B NAND gate, a U2A NAND gate, a main machine indicator light (LED1), and an auxiliary machine indicator light (LED2); The twelfth input pin of the U2D NAND gate is connected to the third input pin of the U1B NAND gate, the first input pin of the U2A NAND gate, and the VCC input pin of the U2A NAND gate through the third resistor (R3), and the VCC input pin of the U2A NAND gate is connected to +5V DC; the fourth output pin of the U1B NAND gate is connected to the fifth input pin of the U2B NAND gate and the first input pin of the U3A NAND gate; The GND pin of the U2A NAND gate is grounded; the host indicator light (LED1) and the first resistor (R1) are connected in series, one end of which is connected to +5V DC and the other end is connected to the third output pin of the U2A NAND gate; the slave indicator light (LED2) and the second resistor (R2) are connected in series, one end of which is connected to +5V DC and the other end is connected to the sixth output pin of the U2B NAND gate; The fourth input pin of the U2B NAND gate is connected to the second input pin of the U2A NAND gate, the input end of the IGBT short-circuit fault detection module (40), and the input end of the IGBT drive signal output module (60).

2. According to the elevator braking unit circuit realizing complex logic control function according to claim 1, it is characterized in that: The IGBT short circuit fault detection module (40) comprises a U2C NAND gate, a U1E NAND gate and a U1D NAND gate; the ninth input pin of the U1D NAND gate is connected to the IGBT short circuit detection terminal, the eighth output pin is connected to the ninth input pin of the U2C NAND gate, and the tenth input pin of the U2C NAND gate is connected to the fourth input pin of the U2B NAND gate; the eighth output pin of the U2C NAND gate is connected to the eleventh input pin of the U1E NAND gate through a fourth resistor (R4), and the eleventh input pin of the U1E NAND gate is grounded through a first capacitor (C1), the tenth output pin of the U1E NAND gate is connected to the IGBT short circuit fault terminal, the IGBT short circuit fault terminal is connected to the anode of the fourth semiconductor diode (D4), the cathode of the fourth semiconductor diode (D4) is connected to one end of the twelfth resistor (R12), the other end of the twelfth resistor (R12) is connected to the anode of a red light emitting diode (LED3), and the cathode of the red light emitting diode (LED3) is grounded.

3. According to the elevator braking unit circuit realizing complex logic control function according to claim 2, it is characterized in that: The over-current and over-temperature detection module (20) comprises a U4C NAND gate, a U4D NAND gate, a U5B NAND gate, a U4A NAND gate, a U4B NAND gate, a U3D NAND gate, a U5D NAND gate, a U5C NAND gate, a fifth semiconductor diode (D5), and a third semiconductor diode (D3); A +5V DC is connected to one end of the eleventh resistor (R11) and the cathode of the third semiconductor diode (D3); an anode of the third semiconductor diode (D3) is connected to the other end of the eleventh resistor (R11) and is grounded through a fourth capacitor (C4); an anode of the third semiconductor diode (D3) is connected to the twelfth input pin of the U3D NAND gate, the fourth input pin of the U4B NAND gate, and the tenth input pin of the U4C NAND gate; The ninth input pin of the U4C NAND gate is connected to the eleventh output pin of the U4D NAND gate, and is also connected to the third input pin of the U5B NAND gate. The eighth output pin of the U4C NAND gate is connected to the twelfth input pin of the U4D NAND gate. The thirteenth input pin of the U4D NAND gate is connected to the IGBT overcurrent detection terminal. The eleventh output pin of the U4D NAND gate is connected to the third input pin of the U5B NAND gate. The fourth output pin of the U5B NAND gate is connected to the first input pin of the U4A NAND gate. The second input pin of the U4A NAND gate is connected to the temperature detection terminal, the VCC input pin of the U4A NAND gate is connected to +5V DC, the GND pin is grounded, the third output pin is connected to the fifth input pin of the U4B NAND gate, the sixth output pin of the U4B NAND gate is connected to the thirteenth input pin of the U3D NAND gate, the eleventh output pin of the U3D NAND gate is connected to the ninth input pin of the U5D NAND gate, and the eighth output pin of the U5D NAND gate is connected to the tenth input pin of the U3C NAND gate; the sixth output pin of the U4B NAND gate is connected to the fifth input pin of the U5C NAND gate, the sixth output pin of the U5C NAND gate is connected to the overheating / IGBT overcurrent fault terminal and the anode of the fifth semiconductor diode (D5), and the cathode of the fifth semiconductor diode (D5) is connected to the cathode of the fourth semiconductor diode (D4).

4. According to the elevator braking unit circuit realizing complex logic control function according to claim 3, it is characterized in that: The host synchronization signal input unit includes an eighth resistor (R8), a ninth resistor (R9), a fifth capacitor (C5), a first voltage stabilizing diode (ZD1), a seventh photocoupler (U7), and a tenth resistor (R10); After the ninth resistor (R9) and the fifth capacitor (C5) are connected in parallel, one end is connected to the VCC voltage input terminal through the eighth resistor (R8), and the other end is connected to the parallel input signal terminal (PI) and the cathode of the seventh photoelectric coupler (U7), the one end of the ninth resistor (R9) is connected to the cathode of the first voltage zener diode (ZD1), the anode of the first voltage zener diode (ZD1) is connected to the anode of the seventh photoelectric coupler (U7), the collector of the seventh photoelectric coupler (U7) is connected to +5V direct current, the emitter of the seventh photoelectric coupler (U7) is grounded through the tenth resistor (R10), and the emitter of the seventh photoelectric coupler (U7) is connected to the second input pin of the U3A NAND gate.

5. According to the elevator braking unit circuit realizing complex logic control function according to claim 4, it is characterized in that: The IGBT drive signal output module (60) comprises a second semiconductor diode (D2), an NPN transistor (Q1), a third capacitor (C3), a seventh resistor (R7), A first semiconductor diode (D1), a fifth resistor (R5), a sixth photocoupler (U6), a second capacitor (C2), a sixth resistor (R6), and a U1C NOT gate; The parallel output signal terminal (PO) is connected to the cathode of the second semiconductor diode (D2), the anode of the first semiconductor diode (D1), and the collector of the NPN transistor (Q1); The anode of the second semiconductor diode (D2) is grounded, connected in parallel to a common signal terminal (COM) and an emitter of an NPN transistor (Q1), one end of a third capacitor (C3), and one end of a seventh resistor (R7); the base of the NPN transistor (Q1) is connected to the other ends of the third capacitor (C3) and the seventh resistor (R7), and an emitter of a sixth photoelectric coupler (U6); and the collector of the sixth photoelectric coupler (U6) is connected to a VCC voltage input terminal and a cathode of the first semiconductor diode (D1) through a fifth resistor (R5); A second capacitor (C2) is connected between the anode and cathode of the sixth photocoupler (U6), and the anode of the sixth photocoupler (U6) is connected to the sixth output pin of the U1C NOT gate through a sixth resistor (R6), the fifth input pin of the U1C NOT gate is connected to the second input pin of the U2A NAND gate, and the sixth output pin of the U1C NOT gate is connected to the IGBT drive signal terminal.

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