Storage device and data protection processing performance optimization method thereof

Abstract

The application discloses a storage device and a data protection processing performance optimization method thereof. The storage device comprises a memory and a controller. The controller comprises a first detection module, a second detection module, a command generation module and an error correction code circuit. The first detection module performs data error correction on error data read from the memory and judges whether the data error correction fails. The second detection module judges whether there is a valid index in a preferred detection table when the data error correction fails and judges whether there is a valid index in a regular detection table when there is no valid index in the preferred detection table. The command generation module generates a setting feature command according to the valid index when there is a valid index in the preferred detection table or the regular detection table, controls the retry number to increase by one, and performs effective configuration on the error data in the memory through the error correction code circuit according to the valid index. When there is no valid index in the preferred detection table and the regular detection table, the error data is identified as an uncorrectable error correction code.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a storage device and a method for optimizing the data protection and processing performance of the same. Background Technology

[0002] During data reading, memory may generate error checking codes (ECCs). In this case, a retry table provided by the manufacturer is typically used to correct the ECC. Because memory performs data correction by querying the retry table line by line, the more times the retry is performed, the longer the latency for write commands becomes, resulting in abnormally slow data processing speed. Summary of the Invention

[0003] In view of the above situation, the present invention provides a storage device and a method for optimizing the data protection processing performance of the same, aiming to solve the problem of slow data processing speed of memory when correcting erroneous data in the prior art.

[0004] This invention provides a storage device, including a memory and a controller; the controller can read data stored in the memory based on a request from an external device, and the controller is used to detect and correct erroneous data read from the memory; the controller includes:

[0005] The first detection module is used to perform data error correction on the erroneous data read from the memory and determine whether the data error correction has failed.

[0006] The second detection module is used to determine whether a valid index exists in the preferred detection table when the data correction fails; and to determine whether the valid index exists in the regular detection table when no valid index exists in the preferred detection table; wherein the number of detection parameters in the preferred detection table is less than the number of detection parameters in the regular detection table; the detection parameters stored in the preferred detection table are those that have been indexed multiple times within a predetermined period, and are arranged in chronological order of indexing time; and

[0007] The command generation module is used to generate a setting feature command based on the valid index when the valid index exists in the preferred detection table or the regular detection table, control the retry count to increase by one, and effectively configure the erroneous data in the memory through the error correction code circuit based on the valid index;

[0008] When no valid index exists in either the preferred detection table or the conventional detection table, the second detection module identifies the erroneous data as an uncorrectable error correction code.

[0009] This invention also proposes a method for optimizing the data protection processing performance of a storage device, the storage device including a memory and a controller; the controller can read data stored in the memory based on a request from an external device; the controller is used to detect and correct erroneous data read from the memory; the controller includes a first detection module, a second detection module, a command generation module, and an error correction code circuit; the data protection processing performance optimization method includes:

[0010] The first detection module performs data error correction on the erroneous data read from the memory;

[0011] The first detection module determines whether the data correction has failed;

[0012] When the data correction fails, the second detection module determines whether a valid index exists in the preferred detection table;

[0013] When no valid index exists in the preferred detection table, the second detection module determines whether the valid index exists in the regular detection table; wherein, the number of detection parameters in the preferred detection table is less than the number of detection parameters in the regular detection table; the detection parameters stored in the preferred detection table are the detection parameters that have been indexed multiple times within a predetermined period, and are arranged in order of indexing time;

[0014] When a valid index exists in the preferred detection table or the regular detection table, the command generation module generates a setting feature command based on the valid index.

[0015] The command generation module controls the retry count to increase by one, and effectively configures the data in the memory through the error correction code circuit according to the valid index;

[0016] When the valid index is not found in either the preferred detection table or the regular detection table, the second detection module identifies the erroneous data as an uncorrectable error correction code.

[0017] The aforementioned storage device and its data protection processing performance optimization method include setting a preferred detection table. When performing data error correction on data read from the storage device, the system prioritizes checking whether a valid index exists in the preferred detection table, which can reduce the error correction time of the controller. In addition, if no valid index exists in the preferred detection table, the system checks whether a valid index exists in the regular detection table, which can ensure the comprehensiveness of the trial and error parameters of the controller during the error correction process. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a storage device according to a preferred embodiment of the present invention.

[0020] Figure 2 for Figure 1 A schematic diagram of the controller module described herein.

[0021] Figure 3 This is a flowchart of a data protection processing performance optimization method according to a preferred embodiment of the present invention.

[0022] Explanation of main component symbols

[0023] Storage device 1

[0024] Memory 10

[0025] Controller 30

[0026] Communication bus 50

[0027] First detection module 31

[0028] Second detection module 32

[0029] Command generation module 33

[0030] ECC circuit 34

[0031] Third detection module 35

[0032] Adjustment module 36

[0033] Steps S10-S19

[0034] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component or may also have a component that is centrally located. When a component is considered to be "set" on another component, it can be directly set on the other component or may also have a component that is centrally located.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0038] The specific embodiments of the storage device and its data protection processing performance optimization method of the present invention will be described below with reference to the accompanying drawings.

[0039] Please see Figure 1 This is a schematic diagram of the storage device 1. The storage device 1 includes a memory 10, a controller 30, and a communication bus 50.

[0040] The memory 10 is used to store data. The memory 10 is a non-volatile memory, such as at least one of embedded multimedia cards (EMMC), storage cards (SD), USB flash drives, read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory, but is not limited thereto.

[0041] The controller 30 can control the memory 10 based on requests from external devices (e.g., a host, CPU, or AP). For example, the controller 30 can send data to the memory 10 for storage or read data stored in the memory 10 based on requests from external devices. The controller 30 can also exchange data with the memory 10 based on requests from external devices. In at least one embodiment of the invention, both the controller 30 and the memory 10 can be implemented using a single chip, a package, or a module. The controller 30 is further configured to detect and correct erroneous data read from the memory 10.

[0042] The communication bus 50 is used to establish data communication between the memory 10 and the controller 30.

[0043] Please refer to the following: Figure 2This is a schematic diagram of the controller 30. The controller 30 includes a first detection module 31, a second detection module 32, a command generation module 33, an error correction code (ECC) circuit 34, a third detection module 35, and an adjustment module 36.

[0044] The first detection module 31 is used to perform data error correction on the erroneous data read from the memory 10 and determine whether the data error correction has failed.

[0045] The second detection module 32 includes a preferred detection table and a regular detection table. The preferred detection table and the regular detection table each include multiple index areas, each index area corresponding to at least one detection parameter. Each detection parameter has a mapping relationship with a data address. The preferred detection table contains fewer detection parameters than the regular detection table. In at least one embodiment of the present invention, the regular detection table includes the preferred detection table and multiple detection parameters not included in the preferred detection table. In other embodiments, the regular detection table can exclude the detection parameters in the preferred detection table to optimize the detection time of the second detection module 32 in determining the valid index in the regular detection table. The detection parameters stored in the preferred detection table are those that have been indexed multiple times within a predetermined period and are arranged in order of indexing time. The valid index is when the data address corresponding to the detection parameter is consistent with the data address corresponding to the erroneous data.

[0046] The second detection module 32 is used to determine whether there is a valid index in the preferred judgment table when the data correction fails.

[0047] In at least one embodiment of the present invention, the second detection module 32 sequentially obtains the detection parameters in the index area through a pointer, and controls the pointer to shift to the next detection parameter after the judgment is completed.

[0048] The second detection module 32 further determines whether the valid index exists in the regular detection table when the valid index does not exist in the preferred detection table.

[0049] The command generation module 33 is used to generate a setting feature command based on the valid index when a valid index exists in the preferred detection table or the regular detection table, control the number of retries to increase by one, and effectively configure the erroneous data in the memory 10 through the ECC circuit 34 based on the valid index.

[0050] In at least one embodiment of the present invention, the initial value of the number of retries is 0.

[0051] The third detection module 35 is used to determine whether the number of retries is greater than zero when the data error correction is successful.

[0052] The adjustment module 36 is used to update the preferred detection table according to the setting feature command when the number of retries is greater than zero.

[0053] In at least one embodiment of the present invention, the adjustment module 36 adjusts the currently valid index to a specified position within the preferred detection table. In at least one embodiment of the present invention, the specified position may be the header position of the preferred detection table. In at least one embodiment of the present invention, the specified position may also be a position within the table or at the foot of the preferred detection table.

[0054] The adjustment module 36 further resets the number of retries to zero.

[0055] When the valid index is not found in either the preferred detection table or the regular detection table, the second detection module 32 identifies the data error as an Uncorrectable error correcting code (UECC).

[0056] The storage device 1 described above is equipped with a preferred detection table. When reading data as an error correction code from the memory 10, it first checks whether a valid index exists in the preferred detection table, which can reduce the error correction time of the controller 30. In addition, when no valid index exists in the preferred detection table, it checks whether a valid index exists in the regular detection table, which can ensure the comprehensiveness of the trial and error parameters of the controller 30 during the error correction process.

[0057] Please refer to the following: Figure 3 This is a flowchart of a data protection processing performance optimization method for storage device 1. In at least one embodiment of the present invention, the storage device 1 may include... Figure 1 or Figure 2 More or fewer other hardware or software, or different component configurations. The data protection processing performance optimization method includes the following steps:

[0058] S10, the first detection module 31 performs data error correction on the erroneous data read from the memory 10.

[0059] In at least one embodiment of the present invention, when the read data is an error correction code (ECC), the first detection module 31 identifies that the read data contains an error.

[0060] S11, the first detection module 31 determines whether the data correction has failed.

[0061] S12. When the data correction fails, the second detection module 32 determines whether there is a valid index in the preferred detection table.

[0062] The preferred detection table includes multiple index areas, each corresponding to at least one detection parameter. Each detection parameter is mapped to a data address. The detection parameters stored in the preferred detection table are those indexed multiple times within a predetermined period, arranged in chronological order of indexing. A valid index is defined as the data address corresponding to the detection parameter matching the data address corresponding to the erroneous data.

[0063] In at least one embodiment of the present invention, the second detection module 32 sequentially obtains the detection parameters in the index area through a pointer, and controls the pointer to shift to the next detection parameter after the judgment is completed.

[0064] S13. When there is no valid index in the preferred detection table, the second detection module 32 determines whether the valid index exists in the regular detection table.

[0065] In at least one embodiment of the present invention, the conventional detection table includes the preferred detection table and a plurality of detection parameters not included in the preferred detection table. In other embodiments, the conventional detection table may exclude the detection parameters in the preferred detection table to optimize the detection time of the second detection module 32 in determining whether a valid index exists in the conventional detection table.

[0066] S14. When a valid index exists in the preferred detection table or the regular detection table, the command generation module 33 generates a setting feature command based on the valid index.

[0067] S15. The command generation module 33 controls the retry count to increase by one, and according to the valid index, it performs effective configuration of the erroneous data in the memory 10 through the ECC circuit, and returns to step S10.

[0068] S16. When the data error correction is successful, the third detection module 35 determines whether the number of retries is greater than zero.

[0069] S17. When the number of retries is greater than zero, the adjustment module 36 updates the preferred detection table according to the setting feature command.

[0070] In at least one embodiment of the present invention, the adjustment module 36 adjusts the currently valid index to a specified position within the preferred detection table. In at least one embodiment of the present invention, the specified position may be the header position of the preferred detection table. In at least one embodiment of the present invention, the specified position may also be a position within the table or at the foot of the preferred detection table.

[0071] S18, The adjustment module 36 resets the number of retry attempts to zero.

[0072] The process ends when the number of retries is zero.

[0073] S19. If no valid index exists in either the preferred detection table or the conventional detection table, the second detection module 32 identifies the erroneous data as an Uncorrectable Error Correcting Code (UECC).

[0074] The data protection processing performance optimization method of the storage device 1 described above sets up a preferred detection table. When performing data error correction on data read from the memory 10, the method prioritizes determining whether there is a valid index in the preferred detection table, which can reduce the error correction time of the controller 30. In addition, when there is no valid index in the preferred detection table, the method checks whether there is a valid index in the regular detection table, which can ensure the comprehensiveness of the trial and error parameters of the controller 30 during the error correction process.

[0075] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A storage device, comprising a memory and a controller; the controller is capable of reading data stored in the memory based on a request from an external device, the controller being configured to detect and correct erroneous data read from the memory; characterized in that, The controller includes: The detection module is used to determine whether data correction has failed. A reread module is used to perform a reread operation on the memory using parameters from a dynamically adjustable preferred detection table; The adjustment module is used to dynamically adjust the parameters in the preferred detection table based on the number of rereads; The detection module detects whether data correction fails after performing the reread operation using parameters from the preferred detection table. If the reread operation is successful and data correction is successful, the reread operation ends. If the reread operation fails, the reread module performs the reread operation on the memory using parameters from the conventional detection table. The detection module also detects whether data correction fails after performing the reread operation using parameters from the conventional detection table. If the reread operation succeeds and data correction is successful, the reread operation ends. If the reread operation fails, the detection module identifies an uncorrectable error in the memory.

2. The storage device as claimed in claim 1, characterized in that, The controller also includes: The third detection module is used to determine whether the number of rereads is greater than zero when the data correction is successful; and An adjustment module is used to update the preferred detection table according to a setting feature command when the number of rereads is greater than zero, and to clear the number of retryes to zero.

3. The storage device as claimed in claim 2, characterized in that, The adjustment module adjusts the currently valid index to a specified position within the preferred detection table.

4. The storage device as claimed in claim 1, characterized in that, The standard test table includes the preferred test table and several test parameters not included in the preferred test table.

5. The storage device as claimed in claim 3, characterized in that, The valid index is the data address corresponding to the detection parameter that is consistent with the data address corresponding to the erroneous data.

6. A method for optimizing the data protection processing performance of a storage device, the storage device comprising a memory and a controller; The controller can read data stored in the memory based on a request from an external device; The controller is used to detect and correct erroneous data read from the memory; The controller includes a first detection module, a second detection module, a command generation module, and an error correction code circuit; characterized in that: the data protection processing performance optimization method includes: The first detection module performs data error correction on the erroneous data read from the memory; The first detection module determines whether the data correction has failed; When the data correction fails, the second detection module determines whether there is a valid index in the preferred detection table; When no valid index exists in the preferred detection table, the second detection module determines whether the valid index exists in the regular detection table; wherein, the number of detection parameters in the preferred detection table is less than the number of detection parameters in the regular detection table; the detection parameters stored in the preferred detection table are the detection parameters that have been indexed multiple times within a predetermined period, and are arranged in order of indexing time; When a valid index exists in the preferred detection table or the regular detection table, the command generation module generates a setting feature command based on the valid index. The command generation module controls the retry count to increase by one, and effectively configures the data in the memory through the error correction code circuit according to the valid index; When the valid index is not found in either the preferred detection table or the regular detection table, the second detection module identifies the erroneous data as an uncorrectable error correction code.

7. The data protection processing performance optimization method as described in claim 6, characterized in that, The controller also includes a third detection module and an adjustment module; The data protection processing performance optimization method further includes: When the data correction is successful, the third detection module determines whether the number of retries is greater than zero; When the number of retries is greater than zero, the adjustment module updates the preferred detection table according to the setting feature command; The adjustment module resets the number of retries to zero.

8. The data protection processing performance optimization method as described in claim 7, characterized in that, The adjustment module adjusts the currently valid index to a specified position within the preferred detection table.

9. The data protection processing performance optimization method as described in claim 6, characterized in that, The standard test table includes the preferred test table and several test parameters not included in the preferred test table.

10. The data protection processing performance optimization method as described in claim 6, characterized in that, The valid index is the data address corresponding to the detection parameter that is consistent with the data address corresponding to the erroneous data.

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