A hybrid mode power factor corrector and method of operation thereof

Abstract

A mixed-mode power factor corrector and its operating method, the corrector includes a power factor correction circuit, a zero-crossing detection circuit and a controller. The power factor correction circuit includes a power inductor and a power switch, and the zero-crossing detection circuit detects the resonance phenomenon generated by the switching voltage across the power switch when the inductor current drops to zero. The controller controls the power factor correction circuit to convert the input voltage to the output voltage by controlling the switching of the power switch through the zero-crossing detection circuit and the operating frequency, and controls the input current drawn by the power factor correction circuit to follow the input voltage. The controller controls the power switch to be turned on based on the inductor current dropping to zero, the resonance generated by the switching voltage being close to the threshold of the zero-crossing detection circuit, and the switching time of the power switch reaching the operating frequency.

Description

TECHNICAL FIELD

[0001] The present application is a power factor corrector and its operating method, in particular, a mixed-mode power factor corrector and its mixed-mode operating method. BACKGROUND

[0002] PFC, which stands for Power Factor Correction, is to improve the ratio of apparent power to real power, that is, the ratio of effective power to total power consumption (apparent power). The power factor can measure the degree of effective use of electricity, and the larger the power factor value, the higher the power utilization rate. The regulations for mains electricity use are different in different countries, but basically PFC is required when the power input is more than 75W.

[0003] The implementation and application of traditional active power factor correctors are generally based on boost converters. According to the operation of inductor current, it can be divided into three types: discontinuous conduction mode (DCM), boundary conduction mode (BCM) and continuous conduction mode (CCM). As shown in Figure 1 In the boundary conduction mode (BCM), the peak value of inductor current Il is larger than that in the continuous conduction mode, so that the power element needs to withstand higher current stress and conduction loss. However, the boundary conduction mode does not have the problem of diode reverse recovery time, and the switching voltage of the main power switch can be switched at a lower voltage (valley), so it has the advantage of smaller switching loss. However, when the inductor current is small, operating in the boundary conduction mode will have a higher switching frequency, causing additional switching loss and thus reducing efficiency.

[0004] Therefore, how to design a mixed-mode power factor corrector and its mixed-mode operating method to make a single power factor corrector operate in continuous conduction mode, boundary conduction mode and discontinuous conduction mode, and avoid the problem of too high switching frequency when the inductor current is small, is a major research topic for the present inventors. SUMMARY

[0005] To solve the above problems, the present application provides a mixed-mode power factor corrector to overcome the problems of the prior art. Therefore, the mixed-mode power factor corrector of the present application comprises a power factor correction circuit, a zero-crossing detection circuit and a controller. The power factor correction circuit receives an input voltage and comprises a power inductor and a power switch. The zero-crossing detection circuit is coupled to the power inductor to detect the resonance of a switching voltage across the power switch. The controller is coupled to the power switch and the zero-crossing detection circuit and controls the switching of the power switch by an operating frequency to control the power factor correction circuit to convert the input voltage to an output voltage and to control the input current drawn by the power factor correction circuit to follow the input voltage. Wherein, the controller controls the power switch to turn on based on the resonance of the switching voltage being close to a threshold of the zero-crossing detection circuit when the inductor current is low to zero and the time point of the switching of the power switch reaching the operating frequency.

[0006] The mixed-mode operation method of the power factor corrector of the present application comprises the following steps: (a) controlling the switching of the power switch of the power factor correction circuit by an operating frequency to control the power factor correction circuit to convert the input voltage to an output voltage and to control the input current drawn by the power factor correction circuit to follow the input voltage. (b) detecting the resonance of a switching voltage across the power switch of the power factor correction circuit. (c) controlling the power switch to turn on based on the resonance of the switching voltage being close to a threshold of the zero-crossing detection circuit when the inductor current is low to zero and the time point of the switching of the power switch reaching the operating frequency.

[0007] The mixed-mode power factor corrector of the present application can operate the power factor correction circuit in continuous conduction mode, critical conduction mode and discontinuous conduction mode based on the magnitude of the inductor current and limit the frequency of the switching of the power switch to be substantially equal to a fixed frequency to avoid the increase of the frequency of the switching of the power switch to reduce the switching loss and thus improve the efficiency of the power factor corrector. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 Waveform schematic diagram of the critical conduction mode of the prior art;

[0009] Figure 2 Circuit block diagram of the mixed-mode power factor corrector of the present application;

[0010] Figure 3 Waveform schematic diagram of the mixed-mode power factor corrector of the present application;

[0011] Figure 4 Internal circuit block diagram of the controller of the present application;

[0012] Figure 5 Method flowchart of the mixed-mode operation method of the power factor corrector of the present application.

[0013] 100 power factor corrector, 1 power factor correction circuit, L power inductor, Q power switch, 2 zero cross detection circuit, 3 controller, MULT multiplier, 32 comparison module, 34 trigger module, RS1 first flip-flop, OR1 first OR module, RS2 second flip-flop, AND module, OR2 second OR module, RS3 third flip-flop, 200 load, Vin input voltage, Vo output voltage, Vdc direct current voltage, Vds switch voltage, Vref1, Vref2 reference voltage, Il inductor current, Iin input current, Sv voltage signal, Sc control signal, Vo_fb, Vin_fb / Vin_rms feedback signal, Iref half-sine wave signal, Ipfc error signal, RAMP triangular wave signal, Szcd comparison signal, Sp pulse signal, S1, S2, S3 output signal, Slg logic signal, Sck clock signal, CCM continuous conduction mode, BCM boundary conduction mode, DCM discontinuous conduction mode, P zero cross point, Fsw operating frequency, ZCD threshold, t0~t1 time, (S100)~(S400) steps. DETAILED DESCRIPTION

[0014] The technical content and detailed description of the present application are described as follows in combination with the drawings:

[0015] Please refer to Figure 2 , the AC input voltage Vin is received by the mixed mode power factor corrector 100, and the input voltage Vin is converted into a DC output voltage Vo to provide the output voltage Vo to power the load 200. The power factor corrector 100 includes a power factor correction circuit 1, a zero cross detection circuit 2, and a controller 3, and the power factor correction circuit 1 can be a boost or buck conversion circuit, or an isolated or non-isolated conversion circuit. Taking the boost conversion circuit as an example, the power factor correction circuit 1 includes a power inductor L and a power switch Q. The power factor correction circuit 100 receives the input voltage Vin, and rectifies the input voltage Vin into a direct current voltage Vdc through a bridge rectifier, and then switches the power switch Q to make the power inductor L store / release energy to generate an inductor current Il, so as to convert the direct current voltage Vdc into the output voltage Vo.

[0016] The zero-crossing detection circuit 2 is coupled to the power inductor L to detect the resonance of the switching voltage Vds across the power switch Q. The zero-crossing detection circuit 2 can be a winding coupled type, a current transformer type or a resistor type. For example, the zero-crossing detection circuit 2 is a winding coupled to the power inductor L to detect the resonance of the switching voltage Vds and to generate a corresponding voltage signal Sv. The controller 3 is coupled to the power switch Q and the zero-crossing detection circuit 2, and controls the switching of the power switch Q by a control signal Sc having an operating frequency to control the power factor correction circuit 1 to convert the input voltage Vin to the output voltage Vo. The power factor corrector 100 is characterized in that the controller 3 controls the switching of the power switch Q to control the input current Iin drawn by the power factor correction circuit 1 to follow the input voltage Vin to improve the power factor at the input of the power factor corrector 100 (typically to above 0.9). The operating frequency is substantially a fixed frequency (e.g. but not limited to, substantially 65 kHz).

[0017] For a better understanding of the present invention, reference will now be made to the following examples without limiting the scope of the application. Figure 2 and Figure 3 The main purpose and feature of the present invention is that the controller 3 can operate the power factor correction circuit 1 in the continuous conduction mode CCM, the boundary conduction mode BCM and the discontinuous conduction mode DCM based on the magnitude of the inductor current Il. When the inductor current Il is large, the power factor correction circuit 1 can be operated in the CCM mode to reduce the current stress and conduction loss of the power switch Q and other power elements with a small inductor current Il peak, thereby improving the efficiency at full load. When the inductor current Il is small, the power factor correction circuit 1 can be operated in the BCM or DCM mode, and the frequency of the switching of the power switch Q is limited to substantially equal to the fixed frequency to avoid the frequency of the switching of the power switch Q from rising to reduce the switching loss, thereby improving the efficiency of the power factor corrector (at light load or when the inductor current Il is close to the zero-crossing point P). The main reason is that the closer the inductor current Il is to the zero-crossing point P of the input voltage Vin, the more likely the inductor current Il will touch the input voltage Vin waveform and the zero-crossing point P (because the voltage difference is too low). If the operating frequency Fsw is not limited, the closer the inductor current Il is to the zero-crossing point P, the faster the frequency of the switching of the power switch Q will be.

[0018] Therefore, the controller 3 of the present invention determines that the timing of the switching of the power switch Q reaches the operating frequency, and the inductor current Il is low to zero and the zero-crossing detection is close to the threshold (e.g. but not limited to 0 ampere), and controls the power switch Q to turn on to limit the frequency of the switching of the power switch Q (i.e. the frequency of the control signal Sc) to substantially equal to the fixed frequency. The fixed frequency is substantially equal to the frequency at which the power factor correction circuit 1 operates in the continuous conduction mode CCM (i.e. fixed frequency operation).

[0019] Under this operation rule, it can be expected that the lower the representative inductance current II is, the closer the inductance current II is to the zero-crossing point P of the input voltage Vin, and vice versa. Therefore, the controller 3 controls the power factor correction circuit 1 to operate in the discontinuous conduction mode DCM based on the input voltage Vin in a first predetermined range around the zero-crossing point P (assuming 0 volts), and controls the power switch Q to be turned on under the condition that the switching time of the power switch Q reaches the operating frequency Fsw and the inductance current II is lowered to the threshold ZCD in the DCM mode. Since the inductance current II is lowered to the threshold ZCD in the DCM mode, the switching voltage Vds will resonate due to the composition of the parasitic capacitance of the power switch Q and the power inductance L, and the switching voltage Vds across the power switch Q will also resonate. Therefore, the optimal timing for turning on the power switch Q is to control the power switch Q to be turned on at the first valley of the resonance after the switching time of the power switch Q reaches the operating frequency Fsw, in addition to meeting the condition that the switching time of the power switch Q reaches the operating frequency Fsw and the inductance current II is lowered to the threshold ZCD. Under this condition, zero voltage / zero current switching can be ensured, and the switching loss of the power switch Q can be reduced.

[0020] On the other hand, the controller 3 controls the power factor correction circuit 1 to operate in the continuous conduction mode CCM based on the input voltage Vin in a second predetermined range around the peak value, and controls the power factor correction circuit 1 to operate in the boundary conduction mode BCM based on the input voltage Vin outside the first predetermined range and the second predetermined range. When the power factor correction circuit 1 operates in the continuous conduction mode CCM (or the boundary conduction mode BCM), the controller 3 controls the power switch Q to be turned on when the switching time of the power switch Q has reached the operating frequency. In the three switching modes, the corresponding control is mainly performed according to whether the inductance current II is zero, and the controller 3 limits the operating frequency Fsw of the three modes to be substantially equal to a fixed frequency, so as to avoid the operating frequency Fsw being too fast when the inductance current II is close to the zero-crossing point P of the input voltage Vin, thereby increasing the loss of the power switch Q. It is worth mentioning that in the prior art, the operation of DCM and BCM is usually variable frequency.

[0021] Referring to Figure 2 , 3 and 4, the controller 3 can be a microcontroller (MCU), a digital signal processor (DSP), or a signal processing device with signal processing function, and the elements shown inside can be control modules composed of physical circuits or software control. For example, Figure 4 The comparator shown can be a physical comparator or a comparison program composed of software.Figure 4 In the present embodiment, the solid line represents the control path for controlling the power switch Q to be turned on, and the dashed line represents the control path for controlling the power switch Q to be turned off. Since the control path for controlling the power switch Q to be turned off is a common control path for a general power factor corrector, the more common elements and their compositions are shown here, but the present embodiment is not limited thereto. Any control path for controlling the power switch Q to be turned off for a power factor correction should be included in the scope of the present embodiment.

[0022] Here, the control path of the dashed line is briefly described. The controller 3 takes the feedback signal Vo_fb of the output voltage Vo of the power factor correction circuit 1 and performs error amplification with the reference voltage Vrefl to provide an error signal, which is then compensated and input into the multiplier MULT. The controller 3 also takes the feedback signal Vin_fb / Vin_rms of the input voltage Vin of the power factor correction circuit 1 and inputs it into the multiplier MULT. The feedback signal Vin_fb is also a signal corresponding to the rectified input voltage Vin. The multiplier MULT provides the half-sine wave signal Iref based on the error signal and the feedback signal Vin_fb / Vin_rms, which represents the reference signal that the input current Iin needs to follow. Then, the controller 3 takes the current of the power factor correction circuit 1 and performs error amplification to provide the error amplified signal Ipfc. The half-sine wave signal Iref and the error amplified signal Ipfc are then compensated and compared with the triangular wave signal RAMP to provide the switch-off signal, which represents the signal that needs to control the power switch Q to be turned off. Thus, as shown in FIG. 2, when the power switch Q is turned on and the inductor current Il rises to a value corresponding to the current value of the input voltage Vin, the controller 3 knows that the power switch Q needs to be turned off through the switch-off signal, so that the inductor current Il starts to decrease to follow the input voltage Vin. Figure 3

[0023] The control path of the dashed line is divided into two paths, one of which (path 1) is used for the lock control of the power switch Q when the inductor current Il is lower than the threshold ZCD and the on-time of the power switch Q is not the operating frequency Fsw, and the other of which (path 2) is used for controlling the on-time of the power switch Q when the inductor current Il is lower than the threshold ZCD. As shown in FIG. 3, the controller 3 includes the comparison module 32, the trigger module 34, the first flip-flop RS1, the first OR module OR1, the second flip-flop RS2, the AND module, the second OR module OR2, and the third flip-flop RS3. The comparison module 32 is coupled to the zero-crossing detection circuit 2 and compares the voltage signal Sv corresponding to the switching voltage Vds with the reference voltage Vref2 corresponding to the threshold ZCD to provide the comparison signal Szcd. The trigger module 34 generates the pulse signal Sp based on the comparison signal Szcd, and the trigger module 34 can be a rising trigger. Figure 4 ​​

[0024] In path 1, the first flip-flop RS1 provides a first output signal S1 to the first OR module OR1 based on the pulse signal Sp and the control signal Sc, or the first OR module OR1 provides a logic signal Slg to the second flip-flop RS2 based on the first output signal S1 and the control signal Sc, and the second flip-flop RS2 provides a second output signal S2 based on the first output signal S1 and a clock signal Sck corresponding to the operating frequency Fsw. In path 2, the AND module provides a third output signal S3 based on the comparison signal Szcd and the clock signal Sck corresponding to the operating frequency Fsw. The second OR module OR2 receives the signals (i.e. the second output signal S2 and the third output signal S3) of the two paths (path 1, path 2) to provide a switch-on signal representing the need to turn on the power switch Q based on the two signals, and the switch-on signal and the switch-off signal are provided through the logical operation of the third flip-flop RS3 to provide the control signal Sc.

[0025] In the CCM mode, the main operation path of the controller 3 is the path 1 of the dashed control path and the solid control path. In the solid control path where the power switch Q is turned off, when the inductor current Il rises to a current value corresponding to the current input voltage Vin, the controller 3 knows that the power switch Q needs to be turned off through the switch-off signal. The switch-off signal causes the third flip-flop RS3 to reset so that the control signal Sc is at a low level (L), and in the solid path, the control signal Sc is at a high level (H) before the power switch is turned off, causing the switch-on signal to be at a low level (L). Therefore, the third flip-flop RS3 provides the control signal Sc at a low level (L) to the power switch Q.

[0026] In the dashed control path where the power switch Q is turned on, when the power switch Q is turned off, the switch-off signal is at a low level (L), and path 2 is mainly inactive because the inductor current Il does not drop below the threshold value ZCD. Path 1 is mainly active based on the clock signal Sck, when the clock signal Sck counts to a certain frequency (for example, but not limited to, 65KHz), the second flip-flop RS2 is set to provide a high level (H) second output signal S2 to the second OR module OR, so that the switch-on signal provided by the second OR module OR is at a high level (H). Therefore, the third flip-flop RS3 is triggered, so that the control signal Sc provided by the third flip-flop RS3 is at a high level (H). Therefore, in the CCM mode, the basis for controlling the power switch Q to be turned on is mainly based on the control signal Sc received by the second flip-flop RS2 and the clock signal Sck.

[0027] In the DCM mode or the BCM mode, the main operation paths of the controller 3 are the dashed-line control path and the solid-line control path of the path 1 and the path 2. The dashed-line control path in which the power switch Q is controlled to be turned off is the same as the CCM mode, which will not be described again. The solid-line control path in which the power switch Q is controlled to be turned on is mainly based on the pulse signal Sp to control the power switch Q to be turned off during the latch-up period, and the latch-up period is the period between the time when the inductor current Il is lower than the threshold ZCD and the time when the power switch Q is switched to reach the operating frequency Fsw. Wherein, the path 1 is mainly used to confirm the operation of the power switch Q to be turned off during the latch-up period, and the path 2 is mainly used to confirm the operation of the time when the power switch Q is switched to reach the operating frequency Fsw.

[0028] Specifically, when the inductor current Il is lower than the threshold ZCD and has not reached the operating frequency Fsw, the trigger module 34 generates the pulse signal Sp based on the inductor current Il being lower than the threshold ZCD. The first flip-flop RS1 provides the first output signal S1 to latch the second flip-flop RS2 based on the trigger of the pulse signal Sp, so as to lock the second output signal S2 output by the second flip-flop RS2 at the low level (L). On the other hand, the clock signal Sck of the path 2 has not counted to reach a certain frequency (i.e., has not reached the operating frequency Fsw), and thus the third output signal S3 provided by the AND module is also at the low level (L). The second OR module OR2 receives the low level (L) signals of the two paths to provide the low level (L) switch-on signal to control the power switch Q to be turned off during the latch-up period. Referring back to Figure 3 That is, the controller 3 will latch the second flip-flop RS2 at the time t0~t1 to control the power switch Q to be turned off during the latch-up period, so as to avoid the situation that the operating frequency Fsw is too high near the zero-crossing point P of the input voltage Vin.

[0029] On the other hand, when the inductor current Il is lower than the threshold ZCD and reaches the operating frequency Fsw, the AND module knows that the time when the power switch Q is switched reaches the operating frequency Fsw based on the comparison between the comparison signal Szcd and the clock signal Sck, and the inductor current Il is also lower than the threshold ZCD. Therefore, the AND module correspondingly provides the third output signal S3 (i.e., the high level (H)) that can control the power switch to be turned on. Therefore, in the DCM and BCM modes, the basis for controlling the power switch Q to be turned on is mainly based on the comparison between the comparison signal Szcd and the clock signal Sck.

[0030] It is worth mentioning that in an embodiment of the present application, the elements shown inside the controller 3 can be control circuits composed of physical elements, or control logic composed of software programs. For example, the AND module can be an AND gate, an AND circuit composed of electronic elements, or an AND function program language written by software. The same applies to other elements, which will not be described again.

[0031] Referring to Figure 2 , 3 and 5, the mixed-mode operation method of the power factor corrector 100 is mainly to control the power factor correction circuit 1 to operate in CCM, BCM and DCM modes, so as to reduce switching loss to improve the efficiency of the power factor corrector when the inductor current Il is small (at light load or when the inductor current Il is close to the zero-crossing point P), and to have a small inductor current Il peak value to reduce the current stress and conduction loss of the power element when the inductor current Il is large. On the other hand, when the power factor correction circuit 1 operates in CCM, BCM and DCM modes, the frequency of the switching of the power switch Q (i.e. the frequency of the control signal Sc) is substantially equal to a fixed frequency, so as to avoid the operating frequency Fsw from increasing too fast when the inductor current Il is close to the zero-crossing point P of the input voltage Vin, thereby increasing the loss of the power switch Q.

[0032] Therefore, the mixed-mode operation method of the power factor corrector 100 includes controlling the power factor correction circuit to convert the input voltage into the output voltage by controlling the switching of the power switch of the power factor correction circuit through the operating frequency, and controlling the input current drawn by the power factor correction circuit to follow the input voltage (S100). Preferably, the controller 3 is used to control the switching of the power switch Q through the control signal Sc with the operating frequency, so as to control the power factor correction circuit 1 to convert the input voltage Vin into the output voltage Vo, and by controlling the switching timing of the power switch Q, the waveform of the input current Iin drawn by the power factor correction circuit 1 can be controlled to follow the input voltage Vin, so as to improve the power factor at the input end of the power factor corrector 100 (which can be improved to above 0.9 in general).

[0033] Then, the inductor current of the power inductor of the power factor correction circuit is detected (S200). Preferably, the zero-crossing detection circuit 2 is coupled to the power inductor L to detect the resonance of the switching voltage Vds of the power switch and to generate a corresponding voltage signal Sv. Finally, when the inductor current is lowered to a threshold value close to zero, the resonance of the switching voltage is close to the threshold value of the zero-crossing detection circuit, and the switching time of the power switch reaches the operating frequency, the power switch is turned on (S300). Preferably, the controller 3 determines that the switching time of the power switch Q reaches the operating frequency, and the inductor current Il is lowered to zero and the zero-crossing detection is close to the threshold value (for example, but not limited to, 0 ampere), and the power switch Q is turned on to limit the frequency of the power switch Q (i.e. the frequency of the control signal Sc) to substantially equal to the fixed frequency. Wherein, the fixed frequency is substantially equal to the frequency of the power factor correction circuit 1 operating in the continuous conduction mode CCM (i.e. fixed frequency operation). Alternatively, the power switch is turned on based on the switching time of the power switch reaching the operating frequency in advance (S400), which is the control behavior of the power factor correction circuit 1 operating in the continuous conduction mode CCM (or the boundary conduction mode BCM).

[0034] However, the above is only a detailed description of the preferred embodiments of the application and the drawings, but the characteristics of the application are not limited to this, and are not intended to limit the application. The scope of the application should be based on the following patent claims, and any embodiments similar to the spirit and scope of the application should be included in the scope of the application. Any changes or modifications in the field of the application can be covered by the following patent claims.

Claims

1. A mixed-mode power factor corrector, comprising: A power factor correction circuit receives input voltage and includes a power inductor and a power switch; A zero-crossover detection circuit is coupled to the power inductor to detect the resonance of the switching voltage across the power switch. The controller is coupled to the power switch and the zero-crossing detection circuit, and controls the switching of the power switch by the operating frequency to control the power factor correction circuit to convert the input voltage to the output voltage, and controls the input current drawn by the power factor correction circuit to follow the input voltage. The controller is characterized by the fact that when the inductor current flowing through the power inductor is as low as zero, the resonance generated by the switching voltage is equal to the threshold of the zero-crossover detection circuit, and the switching point of the power switch reaches the operating frequency, thereby controlling the power switch to turn on.

2. A mixed-mode power factor corrector according to claim 1, characterized in that: The controller includes: a comparison module coupled to the zero-crossover detection circuit, which provides a comparison signal by comparing a voltage signal corresponding to the inductor current with a reference voltage corresponding to the threshold; and a trigger module that generates a pulse signal based on the comparison signal; wherein the controller controls the power switch to remain off during a latching period based on the pulse signal, and the latching period is the time between the inductor current falling to the threshold and the point at which the power switch switches to the operating frequency.

3. A mixed-mode power factor corrector according to claim 2, characterized in that: The controller further includes: a first trigger that provides a first output signal based on the pulse signal; and a second trigger that provides a second output signal based on the first output signal; wherein the first trigger provides the first output signal to latch the second trigger based on the triggering of the pulse signal, so as to lock the second output signal and control the power switch to remain off during the latching period.

4. A mixed-mode power factor corrector according to claim 2, characterized in that: The controller further includes a module that provides a third output signal based on the comparison signal and a clock signal corresponding to the operating frequency; wherein the module determines, based on the comparison signal and the clock signal, that the power switch switching point reaches the operating frequency, and when the inductor current is low to zero, the resonance generated by the switch voltage is equal to the threshold of the zero-crossover detection circuit, and accordingly provides the third output signal that can control the power switch to turn on.

5. A mixed-mode power factor corrector according to claim 1, characterized in that: The controller controls the power factor correction circuit to operate in a discontinuous conduction mode based on the input voltage being within a first predetermined range around the zero crossover point, controls the power factor correction circuit to operate in a continuous conduction mode based on the input voltage being within a second predetermined range of the peak value, and controls the power factor correction circuit to operate in a critical conduction mode based on the input voltage being outside the first predetermined range and the second predetermined range.

6. A mixed-mode power factor corrector according to claim 5, characterized in that: The controller operates in the discontinuous conduction mode and, when the power switch switching point reaches the operating frequency and the inductor current drops to zero, the resonance generated by the switch voltage equals the threshold of the zero-crossover detection circuit. The controller then turns on the power switch when the switch voltage resonates to a low point.

7. A mixed-mode power factor corrector according to claim 1, characterized in that: The zero-crossover detection circuit is a winding that couples with the power inductor to detect the resonance of the switching voltage.

8. A mixed-mode power factor corrector according to claim 1, characterized in that: The controller reaches the operating frequency in advance based on the timing of the power switch switching, and controls the power switch to turn on.

9. A mixed-mode operation method for a power factor correction circuit, comprising the following steps: controlling the switching of a power switch of the power factor correction circuit by controlling the operating frequency to switch the input voltage to the output voltage, and controlling an input current drawn by the power factor correction circuit to follow the input voltage; detecting the resonance of the switching voltage at both ends of the power switch; and based on the fact that when the inductor current flowing through the power inductor is as low as zero, the resonance generated by the switching voltage equals the threshold of the zero-crossing detection circuit, and the switching time of the power switch reaches the operating frequency, controlling the power switch to be turned on.

10. The mixed-mode operation method according to claim 9, characterized in that: It also includes the following steps: The power switch is controlled to turn off based on the current in the inductor rising to the current value corresponding to the input voltage when the power switch is turned on.

11. The mixed-mode operation method according to claim 9, characterized in that: It also includes the following steps: providing a comparison signal by comparing a voltage signal corresponding to the inductor current with a reference voltage corresponding to the threshold. A pulse signal is generated based on the comparison signal; and the power switch is controlled to remain off during a latching period based on the pulse signal; wherein the latching period is the time between the inductor current falling to the threshold and the time when the power switch switches to the operating frequency.

12. The mixed-mode operation method according to claim 11, characterized in that: It further includes the following steps: providing a first output signal based on the pulse signal; and providing a second output signal based on the first output signal; Based on the triggering of the pulse signal, the first output signal is provided to lock the second output signal, so as to control the power switch to remain off during the locking period.

13. The mixed-mode operation method according to claim 11, characterized in that: It also includes the following steps: providing a third output signal based on the comparison signal and a clock signal corresponding to the operating frequency; determining, based on the comparison signal and the clock signal, that the power switch switching point reaches the operating frequency and the inductor current is as low as zero, that the resonance generated by the switch voltage is equal to the threshold of the zero-crossover detection circuit, and accordingly providing the third output signal that can control the power switch to turn on.

14. The mixed-mode operation method according to claim 11, characterized in that: It further includes the following steps: controlling the power factor correction circuit to operate in a discontinuous conduction mode based on the input voltage within a first predetermined range around the zero crossover point; controlling the power factor correction circuit to operate in a continuous conduction mode based on the input voltage within a second predetermined range of the peak value; and controlling the power factor correction circuit to operate in a critical conduction mode based on the input voltage outside the first predetermined range and the second predetermined range.

15. The mixed-mode operation method according to claim 14, characterized in that: It also includes the following steps: based on the operation in the discontinuous conduction mode, and satisfying the condition that when the power switch switching point reaches the operating frequency and the inductor current is low to zero, the resonance generated by the switch voltage is equal to the threshold of the zero crossover detection circuit, the power switch is turned on when the switch voltage resonates to a low point.

16. The mixed-mode operation method according to claim 9, characterized in that: It also includes the following steps: Based on the fact that the operating frequency is reached before the power switch switches, the power switch is controlled to turn on.

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