Silicon carbide mos device and method of manufacturing the same

Abstract

The application provides a silicon carbide MOS device and a manufacturing method thereof, wherein the mobility of the crystal surface on the second side of the trench type gate structure is higher than the mobility of the crystal surface on the first side of the trench type gate structure, and correspondingly, the depth of the second well region is deeper than the depth of the first well region and / or the doping concentration of the second well region is higher than the doping concentration of the first well region, the second well region is located in the silicon carbide epitaxial layer on the second side of the trench type gate structure, and the first well region is located in the silicon carbide epitaxial layer on the first side of the trench type gate structure. Thus, the consistency difference of the gate opening caused by the mobility difference of the crystal surfaces on both sides of the trench type gate structure can be balanced, so that the consistency of the gate opening is improved, and the performance and reliability of the silicon carbide MOS device are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a silicon carbide MOS device and its manufacturing method. Background Technology

[0002] Silicon carbide (SiC) is currently the most mature wide-bandgap semiconductor material. Compared with other semiconductor materials, SiC has advantages such as a wide bandgap, high saturated electron drift velocity, high breakdown strength, low dielectric constant, and high thermal conductivity. Therefore, SiC is an ideal material for high-temperature, high-frequency, and high-power applications. Under the same voltage and current conditions, the drift region resistance of SiC devices is 200 times lower than that of silicon. Even the on-state voltage drop of high-voltage SiC MOS devices is much lower than that of unipolar and bipolar silicon devices. Moreover, the switching time of SiC devices can reach the 10ns level.

[0003] Currently, commonly used silicon carbide MOS devices suffer from poor gate turn-on consistency. How to further improve the performance of silicon carbide MOS devices has become the direction of research and development efforts for those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a silicon carbide MOS device and its manufacturing method to solve the problem of poor gate turn-on consistency in existing silicon carbide MOS devices.

[0005] To address the aforementioned technical problems, the present invention provides a silicon carbide MOS device, the silicon carbide MOS device comprising:

[0006] A silicon carbide substrate and a silicon carbide epitaxial layer formed on the silicon carbide substrate, wherein both the silicon carbide substrate and the silicon carbide epitaxial layer are of a first conductivity type;

[0007] A trench gate structure is located in the silicon carbide epitaxial layer, wherein the crystal mobility of the second side of the trench gate structure is higher than that of the first side of the trench gate structure.

[0008] A first well region and a second well region, both of which are of the second conductivity type, wherein the second well region is deeper than the first well region and / or has a higher doping concentration than the first well region, the first well region is located in the silicon carbide epitaxial layer on the first side of the trench gate structure, and the second well region is located in the silicon carbide epitaxial layer on the second side of the trench gate structure; and...

[0009] The source region is of a first conductivity type and is located in the first well region and the second well region.

[0010] Optionally, in the silicon carbide MOS device, the crystal plane of the second side is a <11-20> crystal plane, and the crystal plane of the first side is a non-<11-20> crystal plane.

[0011] Optionally, in the silicon carbide MOS device, the silicon carbide MOS device further includes: a pillar region, the pillar region being of a second conductivity type, the pillar region being located in the silicon carbide epitaxial layer on the side of the first well region and the second well region.

[0012] Optionally, in the silicon carbide MOS device, the depth of the pillar region is deeper than the depths of the first well region and the second well region.

[0013] Optionally, in the silicon carbide MOS device, the depth of the gate structure is deeper than the depth of the first well region and the second well region, and the depth of the gate structure is shallower than the depth of the pillar region.

[0014] Optionally, in the silicon carbide MOS device, the silicon carbide MOS device further includes: a metal gate electrode electrically connected to the gate structure; a metal source electrode electrically connected to the source region; and a metal drain electrode electrically connected to the silicon carbide substrate.

[0015] The present invention also provides a method for manufacturing a silicon carbide MOS device, the method comprising:

[0016] A silicon carbide substrate is provided, wherein the silicon carbide substrate is of a first conductivity type;

[0017] A silicon carbide epitaxial layer is formed on the silicon carbide substrate, wherein the silicon carbide epitaxial layer is of a first conductivity type;

[0018] A trench gate structure is formed in the silicon carbide epitaxial layer, wherein the crystal mobility of the second side of the trench gate structure is higher than that of the first side of the trench gate structure.

[0019] A first well region and a second well region are formed in the silicon carbide epitaxial layer. Both the first well region and the second well region are of a second conductivity type. The depth of the second well region is greater than the depth of the first well region and / or the doping concentration of the second well region is greater than that of the first well region. The first well region is located in the silicon carbide epitaxial layer on a first side of the trench gate structure, and the second well region is located in the silicon carbide epitaxial layer on a second side of the trench gate structure.

[0020] Source regions are formed in the first well region and the second well region, wherein the source regions are of a first conductivity type.

[0021] Optionally, in the method for manufacturing the silicon carbide MOS device, before forming a trench gate structure in the silicon carbide epitaxial layer, the formation of a first well region and a second well region in the silicon carbide epitaxial layer is performed; or, after forming a trench gate structure in the silicon carbide epitaxial layer, the formation of a first well region and a second well region in the silicon carbide epitaxial layer is performed.

[0022] Optionally, in the manufacturing method of the silicon carbide MOS device, the crystal plane of the second side is a <11-20> crystal plane, and the crystal plane of the first side is a non-<11-20> crystal plane.

[0023] Optionally, in the method for manufacturing the silicon carbide MOS device, the method further includes:

[0024] A pillar region is formed in the silicon carbide epitaxial layer. The pillar region is of a second conductivity type and is located on the side of the first well region and the second well region.

[0025] The inventors discovered that in a silicon carbide substrate, for the same trench gate structure, the crystal mobility on both sides is different, with one side having a higher crystal mobility and the other side having a lower crystal mobility, which leads to poor gate turn-on consistency.

[0026] Therefore, in the silicon carbide MOS device and its manufacturing method provided by the present invention, the crystal mobility of the second side of the trench gate structure is higher than that of the first side of the trench gate structure. Correspondingly, the depth of the second well region is greater than that of the first well region and / or the doping concentration of the second well region is greater than that of the first well region. The second well region is located in the silicon carbide epitaxial layer on the second side of the trench gate structure, and the first well region is located in the silicon carbide epitaxial layer on the first side of the trench gate structure. This balances the difference in gate turn-on consistency caused by the difference in crystal mobility on both sides of the trench gate structure, thereby improving the gate turn-on consistency and ultimately improving the performance and reliability of the silicon carbide MOS device. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of an existing silicon carbide MOS device.

[0028] Figure 2 This is a schematic flowchart of the manufacturing method of the silicon carbide MOS device according to Embodiment 1 of the present invention.

[0029] Figures 3 to 10 This is a cross-sectional schematic diagram of the device structure formed by implementing the manufacturing method of the silicon carbide MOS device according to Embodiment 1 of the present invention.

[0030] Figure 11This is a schematic diagram of the turn-on voltage on both sides of the trench gate structure in the silicon carbide MOS device according to an embodiment of the present invention.

[0031] Figure 12 This is a schematic diagram of the turn-on voltage on both sides of the trench gate structure in an existing silicon carbide MOS device.

[0032] Figure 13 This is a schematic diagram comparing the on-resistance of a silicon carbide MOS device according to an embodiment of the present invention with that of a conventional silicon carbide MOS device.

[0033] Figure 14 This is a schematic diagram comparing the input capacitance of a silicon carbide MOS device according to an embodiment of the present invention with that of a conventional silicon carbide MOS device.

[0034] Figure 15 This is a schematic diagram comparing the output capacitance of a silicon carbide MOS device according to an embodiment of the present invention with that of a conventional silicon carbide MOS device.

[0035] Figure 16 This is a schematic flowchart of the manufacturing method of the silicon carbide MOS device according to Embodiment 2 of the present invention.

[0036] Figures 17 to 24 This is a cross-sectional schematic diagram of the device structure formed by implementing the manufacturing method of the silicon carbide MOS device according to Embodiment 2 of the present invention.

[0037] The reference numerals in the attached figures are explained as follows:

[0038] 10 - Silicon carbide MOS device; 100 - Silicon carbide substrate; 102 - Silicon carbide epitaxial layer; 104 - Well region; 106 - Trench gate structure; 108 - Source region.

[0039] 20 - Silicon carbide MOS device; 200 - Silicon carbide substrate; 202 - Silicon carbide epitaxial layer; 204 - Pillar region; 206 - First well region; 208 - Second well region; 210 - Source region; 212 - Trench; 2120 - First side; 2122 - Second side; 214 - Trench gate structure; 2140 - Gate dielectric layer; 2142 - Gate conductive layer; 216 - Metal gate electrode; 218 - Metal source electrode; 220 - Metal drain electrode.

[0040] 300, 302, 304, 306 - Turn-on voltage curves; 308 - Source-drain voltage-source-drain current curves; 310 - Source-drain voltage-source-drain current curves; 312 - Source-drain voltage-input capacitance curves; 314 - Source-drain voltage-input capacitance curves; 316 - Source-drain voltage-output capacitance curves; 318 - Source-drain voltage-output capacitance curves.

[0041] 40 - Silicon carbide MOS device; 400 - Silicon carbide substrate; 402 - Silicon carbide epitaxial layer; 404 - Pillar region; 406 - Trench; 4060 - First side; 4062 - Second side; 408 - Trench gate structure; 4080 - Gate dielectric layer; 4082 - Gate conductive layer; 410 - First well region; 412 - Second well region; 414 - Source region; 416 - Metal gate electrode; 418 - Metal source electrode; 420 - Metal drain electrode. Detailed Implementation

[0042] The silicon carbide MOS device and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0043] The terminology used in this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. Unless otherwise defined in this application, the technical or scientific terms used in this invention should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. "A plurality" or "several" indicates two or more. Unless otherwise stated, terms such as "front," "rear," "lower," and / or "upper" are for ease of description only and are not limited to a location or spatial orientation. Terms such as "comprising" or "including" indicate that the element or object preceding "comprising" encompasses the element or object listed following "comprising" or its equivalents, and do not exclude other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this specification and appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0044] Please refer to Figure 1 This is a schematic diagram of the structure of an existing silicon carbide MOS device. Figure 1As shown, the silicon carbide MOS device 10 includes: an N-type silicon carbide substrate 100; an N-type silicon carbide epitaxial layer 102 formed on the silicon carbide substrate 100; a P-type well region 104 formed in the silicon carbide epitaxial layer 102; a trench gate structure 106 formed in the well region 104 and extending into the silicon carbide epitaxial layer 102; and a source region 108 formed in the well region 104.

[0045] The silicon carbide MOS device 10 has a problem with poor gate turn-on consistency.

[0046] The inventors conducted in-depth research and found that in the prior art, the depth of the P-type well region of silicon carbide MOS devices is the same on both sides of the trench gate structure. However, in the silicon carbide substrate, for the same trench gate structure, the crystal mobility on both sides is different, with one side having a higher crystal mobility and the other side having a lower crystal mobility, which leads to poor gate turn-on consistency.

[0047] Therefore, the core idea of ​​this invention is to provide a silicon carbide MOS device and its manufacturing method, wherein the crystal mobility of the second side of the trench gate structure is higher than that of the first side of the trench gate structure, and correspondingly, the depth of the second well region is greater than that of the first well region and / or the doping concentration of the second well region is greater than that of the first well region. The second well region is located in the silicon carbide epitaxial layer on the second side of the trench gate structure, and the first well region is located in the silicon carbide epitaxial layer on the first side of the trench gate structure. This balances the difference in gate turn-on consistency caused by the difference in crystal mobility on both sides of the trench gate structure, thereby improving the gate turn-on consistency and ultimately improving the performance and reliability of the silicon carbide MOS device.

[0048] The silicon carbide MOS device and its manufacturing method provided by the present invention will be further described below with reference to the following embodiments.

[0049] Example 1

[0050] Please refer to Figure 2 This is a schematic flowchart illustrating the manufacturing method of a silicon carbide MOS device according to Embodiment 1 of the present invention. Figure 2 As shown, in this embodiment, the manufacturing method of the silicon carbide MOS device includes the following steps:

[0051] Step S10: Provide a silicon carbide substrate, wherein the silicon carbide substrate is of a first conductivity type;

[0052] Step S11: A silicon carbide epitaxial layer is formed on the silicon carbide substrate, wherein the silicon carbide epitaxial layer is of a first conductivity type;

[0053] Step S12: A first well region is formed in the silicon carbide epitaxial layer, wherein the first well region is of the second conductivity type;

[0054] Step S13: A second well region is formed in the silicon carbide epitaxial layer. The second well region is of a second conductivity type and the depth of the second well region is greater than the depth of the first well region.

[0055] Step S14: Form source regions in the first well region and the second well region, wherein the source regions are of a first conductivity type; and,

[0056] Step S15: A trench gate structure is formed in the silicon carbide epitaxial layer, wherein the crystal mobility of the second side of the trench gate structure is higher than that of the first side of the trench gate structure, the first well region is located in the silicon carbide epitaxial layer on the first side, and the second well region is located in the silicon carbide epitaxial layer on the second side.

[0057] In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments of this application, the first conductivity type may also be P-type, and correspondingly, the second conductivity type may be N-type.

[0058] For details, please refer to the reference. Figures 3 to 10 It is a cross-sectional schematic diagram of the device structure formed by the manufacturing method of the silicon carbide MOS device according to Embodiment 1 of the present invention.

[0059] like Figure 3 As shown, a silicon carbide substrate 200 is provided, wherein the conductivity type of the silicon carbide substrate 200 is N-type. Next, a silicon carbide epitaxial layer 202 is formed on the silicon carbide substrate 200, wherein the conductivity type of the silicon carbide epitaxial layer 202 is N-type.

[0060] Please refer to Figure 4 In this embodiment, pillar regions 204 are then formed in the silicon carbide epitaxial layer 202, and the conductivity type of the pillar regions 204 is P-type. Preferably, the pillar regions 204 are formed by performing P-type heavy doping on the silicon carbide epitaxial layer 202. The pillar regions 204 extend from the surface of the silicon carbide epitaxial layer 202 into the silicon carbide epitaxial layer 202, and the pillar regions 204 are in the extension direction of the silicon carbide epitaxial layer 202 (i.e., Figure 4 The device region is defined in the horizontal direction. In this embodiment, a superjunction structure is formed through the pillar region 204, which can improve the breakdown voltage characteristics of the formed silicon carbide MOS device, reduce the on-resistance and switching loss of the device, and increase the switching frequency of the device.

[0061] Please refer to Figure 5In this embodiment, a first well region 206 is then formed in the silicon carbide epitaxial layer 202, wherein the conductivity type of the first well region 206 is P-type. Specifically, a patterned mask layer can be formed on the silicon carbide epitaxial layer 202 using a photomask, the patterned mask layer exposing a portion of the silicon carbide epitaxial layer 202; then, a P-type ion implantation process is performed on the exposed silicon carbide epitaxial layer 202 to form the first well region 206 in the silicon carbide epitaxial layer 202.

[0062] The first well region 206 extends from the surface of the silicon carbide epitaxial layer 202 into the silicon carbide epitaxial layer 202. Furthermore, the first well region 206 is located within the device region defined by the pillar region 204 and is connected to the pillar region 204 in the horizontal direction. In the vertical direction (i.e., the thickness direction of the silicon carbide epitaxial layer 202), the depth of the first well region 206 is shallower than the depth of the pillar region 204.

[0063] Please refer to the following: Figure 6 A second well region 208 is formed in the silicon carbide epitaxial layer 202. The second well region 208 has a P-type conductivity and a depth greater than that of the first well region 206. Similarly, a patterned mask layer can be formed on the silicon carbide epitaxial layer 202 using another photomask, exposing a portion of the silicon carbide epitaxial layer 202. Then, a P-type ion implantation process is performed on the exposed silicon carbide epitaxial layer 202 to form the second well region 208 within it.

[0064] The second well region 208 extends from the surface of the silicon carbide epitaxial layer 202 into the silicon carbide epitaxial layer 202. Further, the second well region 208 is located within the device region defined by the pillar region 204 and is horizontally connected to the pillar region 204. Vertically, the depth of the second well region 208 is shallower than the depth of the pillar region 204. In this embodiment, horizontally, the second well region 208 is also connected to the first well region 206. That is, on opposite sides of the second well region 208 are the first well region 206 and the pillar region 204, respectively; and on opposite sides of the first well region 206 are the second well region 208 and the pillar region 204, respectively. In other embodiments of this application, horizontally, the second well region 208 may also be spaced apart from the first well region 206, with the spacing being less than or equal to the cross-sectional width of the subsequently formed gate structure.

[0065] like Figure 7As shown, a source region 210 is then formed in the first well region 206 and the second well region 208, wherein the conductivity type of the source region 210 is N-type. Specifically, the source region 210 can be formed by performing N-type heavy doping on the first well region 206 and the second well region 208.

[0066] In this embodiment, the source region 210 extends from the surfaces of the first well region 206 and the second well region 208 into the first well region 206 and the second well region 208, meaning the depth of the source region 210 is shallower than the depth of the first well region 206 and the second well region 208. Furthermore, both sides of the source region 210 are respectively connected to the pillar region 204.

[0067] like Figure 8 As shown, a trench 212 is then formed in the silicon carbide epitaxial layer 202, extending from the surface of the silicon carbide epitaxial layer 202 into the silicon carbide epitaxial layer 202. Specifically, the trench 212 can be formed by etching the silicon carbide epitaxial layer 202 using either a dry etching process or a wet etching process. Here, the trench 212 penetrates through the first well region 206 and the second well region 208 into the silicon carbide epitaxial layer 202, thereby positioning the first well region 206 and the second well region 208 on opposite sides of the trench 212.

[0068] Because silicon carbide wafers have an angle during growth, typically around 4°, etching the silicon carbide epitaxial layer 202 to form the trench 212 will result in different crystal surface mobility on opposite sides of the trench 212. For example... Figure 8 As shown in this embodiment, the crystal plane mobility of the second side 2122 of the trench 212 is higher than that of the first side 2120 of the trench 212. Specifically, the second side 2122 is an <11-20> crystal plane, which is the crystal plane with the highest mobility in the vertical direction; the first side 2120 is a non-<11-20> crystal plane, and its mobility is relatively low, that is, lower than that of the second side 2122.

[0069] Please refer to Figure 9 Next, a trench-type gate structure 214 is formed in the trench 212. The trench-type gate structure 214 includes a gate dielectric layer 2140 covering the surface of the trench 212 and a gate conductive layer 2142 covering the gate dielectric layer 2140 and filling the trench 212. Specifically, the gate dielectric layer 2140 can be formed on the surface of the trench 212 by an oxidation process or a deposition process; then, the gate conductive layer 2142 can be formed by depositing polysilicon on the gate dielectric layer 2140.

[0070] Here, the trench gate structure 214 is formed in the trench 212, so that the first side 2120 and the second side 2122 are respectively located on opposite sides of the trench gate structure 214, that is, the crystal mobility of the second side 2122 of the trench gate structure 214 is higher than the crystal mobility of the first side 2120 of the trench gate structure 214.

[0071] In this embodiment, the surfaces of the trench gate structure 214, the source region 210, and the pillar region 204 are flush. Furthermore, the depth of the trench gate structure 214 is deeper than the depths of the first well region 206 and the second well region 208, but shallower than the depth of the pillar region 204.

[0072] like Figure 10 As shown, a metal gate electrode 216, a metal source electrode 218, and a metal drain electrode 220 are formed, wherein the metal gate electrode 216 and the metal source electrode 218 are located on the same side, and the metal drain electrode 220 is located on the other side. Specifically, the metal gate electrode 216 and the metal source electrode 218 are formed on the surface of the silicon carbide epitaxial layer 202, and the metal gate electrode 216 is electrically connected to the trench gate structure 214; the metal source electrode 218 is electrically connected to the source region 210, wherein the metal gate electrode 216 and the metal source electrode 218 can be isolated by a dielectric layer. The metal drain electrode 220 is formed on the surface of the silicon carbide substrate 200, where the silicon carbide substrate 200 serves as the drain region, and the metal drain electrode 220 is electrically connected to the silicon carbide substrate 200.

[0073] Please continue to refer to this. Figure 10A silicon carbide MOS device 20 was formed by the manufacturing method of the silicon carbide MOS device. The silicon carbide MOS device 20 includes: a silicon carbide substrate 200 and a silicon carbide epitaxial layer 202 formed on the silicon carbide substrate 200, both the silicon carbide substrate 200 and the silicon carbide epitaxial layer 202 being of a first conductivity type; a trench gate structure 214 located in the silicon carbide epitaxial layer 202, wherein the crystal mobility of the second side 2122 of the trench gate structure 214 is higher than that of the first side 2120 of the trench gate structure 214. The crystal plane mobility; a first well region 206 and a second well region 208, both of which are of the second conductivity type, the depth of the second well region 208 being greater than the depth of the first well region 206, the first well region 206 being located in the silicon carbide epitaxial layer 202 on the first side 2120, and the second well region 208 being located in the silicon carbide epitaxial layer 202 on the second side 2122; and a source region 210, which is of the first conductivity type and is located in the first well region 206 and the second well region 208.

[0074] In this embodiment, the crystal mobility of the second side 2122 is higher than that of the first side 2120. Correspondingly, the depth of the second well region 208 is deeper than that of the first well region 206. Thus, the difference in gate turn-on consistency caused by the difference in crystal mobility on both sides of the trench gate structure 214 can be balanced, thereby improving the gate turn-on consistency and thus improving the performance and reliability of the silicon carbide MOS device 20.

[0075] Furthermore, the silicon carbide MOS device 20 further includes a pillar region 204, which is of a second conductivity type and is located in the silicon carbide epitaxial layer 202 on the sides of the first well region 206 and the second well region 208. A superjunction structure is formed through the pillar region 204, thereby improving the breakdown voltage characteristics of the formed silicon carbide MOS device, reducing the on-resistance and switching losses, and increasing the switching frequency of the device.

[0076] Please refer to Figure 11 and Figure 12 In this embodiment, the turn-on voltages on both sides of the trench gate structure in the silicon carbide MOS device 20 and the silicon carbide MOS device 10 were detected, respectively. Figure 11 and Figure 12As shown, the turn-on voltage curves 300 and 302 on both sides of the trench gate structure 214 are basically overlapping, while the turn-on voltage curves 304 and 306 on both sides of the trench gate structure 106 are significantly separated. In other words, the separation degree of the turn-on voltage curves 300 and 302 on both sides of the trench gate structure 214 is significantly less than that of the turn-on voltage curves 304 and 306 on both sides of the trench gate structure 106. It can be seen that the silicon carbide MOS device 20 provided in this embodiment of the invention can balance the difference in gate turn-on consistency caused by the difference in crystal mobility on both sides of the trench gate structure 214, thereby improving the gate turn-on consistency.

[0077] For further details, please refer to... Figures 13 to 15 In this embodiment of the application, multiple parameters of silicon carbide MOS device 20 and silicon carbide MOS device 10 were also detected to obtain the source-drain voltage-source-drain current curve 308, the source-drain voltage-input capacitance curve 312 and the source-drain voltage-output capacitance curve 316 of silicon carbide MOS device 20, and the source-drain voltage-source-drain current curve 310, the source-drain voltage-input capacitance curve 314 and the source-drain voltage-output capacitance curve 318 of silicon carbide MOS device 10. Therefore, we can conclude that: the on-resistance of silicon carbide MOS device 20 is approximately 6.5Ω, while that of silicon carbide MOS device 10 is approximately 6.9Ω, indicating that the on-resistance of silicon carbide MOS device 20 is superior to that of silicon carbide MOS device 10; the input capacitance (Ciss) of silicon carbide MOS device 20 is approximately 6.01pF, while that of silicon carbide MOS device 10 is approximately 6.25pF, meaning that the input capacitance of silicon carbide MOS device 20 is lower than that of silicon carbide MOS device 10, resulting in a higher switching frequency for silicon carbide MOS device 20; the output capacitance (Coss) of silicon carbide MOS device 20 is approximately 0.225pF, while that of silicon carbide MOS device 10 is approximately 0.224pF, which are essentially equivalent. Thus, in Figure 13 As shown, the two curves largely overlap. This demonstrates that the silicon carbide MOS device 20 provided in this embodiment exhibits superior performance.

[0078]

Example 2

[0079] Please refer to Figure 16 This is a schematic flowchart illustrating the manufacturing method of the silicon carbide MOS device according to Embodiment 2 of the present invention. Figure 16 As shown, in this second embodiment, the manufacturing method of the silicon carbide MOS device includes the following steps:

[0080] Step S20: Provide a silicon carbide substrate, wherein the silicon carbide substrate is of a first conductivity type;

[0081] Step S21: A silicon carbide epitaxial layer is formed on the silicon carbide substrate, wherein the silicon carbide epitaxial layer is of a first conductivity type;

[0082] Step S22: A trench gate structure is formed in the silicon carbide epitaxial layer, wherein the crystal mobility of the second side of the trench gate structure is higher than that of the first side.

[0083] Step S23: A first well region is formed in the silicon carbide epitaxial layer on the first side of the trench gate structure, wherein the first well region is of the second conductivity type;

[0084] Step S24: A second well region is formed in the silicon carbide epitaxial layer on the second side of the trench gate structure. The second well region has a second conductivity type, a greater depth than the first well region, and a higher doping concentration than the first well region.

[0085] Step S25: Form source regions in the first well region and the second well region, wherein the source regions are of a first conductivity type.

[0086] In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments of this application, the first conductivity type may also be P-type, and correspondingly, the second conductivity type may be N-type.

[0087] For details, please refer to the reference. Figures 17 to 24 This is a cross-sectional schematic diagram of the device structure formed by the manufacturing method of the silicon carbide MOS device according to Embodiment 2 of the present invention.

[0088] like Figure 17 As shown, a silicon carbide substrate 400 is provided, wherein the conductivity type of the silicon carbide substrate 400 is N-type. Next, a silicon carbide epitaxial layer 402 is formed on the silicon carbide substrate 400, wherein the conductivity type of the silicon carbide epitaxial layer 402 is N-type.

[0089] Please refer to Figure 18 In this embodiment, pillar regions 404 are then formed in the silicon carbide epitaxial layer 402, and the conductivity type of the pillar regions 404 is P-type. Preferably, the pillar regions 404 are formed by performing P-type heavy doping on the silicon carbide epitaxial layer 402. The pillar regions 404 extend from the surface of the silicon carbide epitaxial layer 402 into the silicon carbide epitaxial layer 402, and the pillar regions 404 are in the extension direction of the silicon carbide epitaxial layer 402 (i.e., Figure 16 The device region is defined in the horizontal direction. In this embodiment, a superjunction structure is formed through the pillar region 404, which can improve the breakdown voltage characteristics of the formed silicon carbide MOS device, reduce the on-resistance and switching loss of the device, and increase the switching frequency of the device.

[0090] Please refer to Figure 19 Next, a trench 406 is formed in the silicon carbide epitaxial layer 402 in the device region, the trench 406 extending from the surface of the silicon carbide epitaxial layer 402 into the silicon carbide epitaxial layer 402. Specifically, the trench 406 can be formed by etching the silicon carbide epitaxial layer 402 using a dry etching process or a wet etching process.

[0091] Here, after etching the silicon carbide epitaxial layer 402 to form the trench 406, an <11-20> crystal plane is formed on one side of the trench 406. The <11-20> crystal plane is the crystal plane with the highest mobility in the vertical direction. Since the silicon carbide wafer has a tilt angle during growth, usually around 4°, the other side of the trench 406 is a non-<11-20> crystal plane, and its mobility is relatively low. Here, the first side 4060 and the second side 4062 of the trench 406 are respectively, wherein the crystal plane mobility of the second side 4062 is higher than that of the first side 4060. Furthermore, in this embodiment, the second side 4062 is an <11-20> crystal plane, and the first side 4060 is a non-<11-20> crystal plane.

[0092] Next, please refer to Figure 20 A trench-type gate structure 408 is formed in the trench 406. The trench-type gate structure 408 includes a gate dielectric layer 4080 covering the surface of the trench 406 and a gate conductive layer 4082 covering the gate dielectric layer 4080 and filling the trench 406. Specifically, the gate dielectric layer 4080 can be formed on the surface of the trench 406 by an oxidation process or a deposition process; then, the gate conductive layer 4082 can be formed by depositing polysilicon on the gate dielectric layer 4080. Accordingly, the first side 4060 and the second side 4062 are respectively located on both sides of the trench-type gate structure 408.

[0093] The surface of the trench gate structure 408 is flush with the surfaces of the silicon carbide epitaxial layer 402 and the pillar region 404, and the depth of the trench gate structure 408 is shallower than the depth of the pillar region 404.

[0094] Please refer to Figure 21In this embodiment, a first well region 410 is then formed in the silicon carbide epitaxial layer 402 on the first side 4060 of the trench gate structure 408. Here, the conductivity type of the first well region 410 is P-type. Specifically, a patterned mask layer can be formed on the silicon carbide epitaxial layer 402 using a photomask, which exposes the silicon carbide epitaxial layer 402 on the first side 4060. Then, a P-type ion implantation process is performed on the exposed silicon carbide epitaxial layer 402 to form the first well region 410 in the silicon carbide epitaxial layer 402 on the first side 4060.

[0095] The first well region 410 extends from the surface of the silicon carbide epitaxial layer 402 into the silicon carbide epitaxial layer 402. Further, in the horizontal direction, the two sides of the first well region 410 are respectively connected to the pillar region 404 and the trench gate structure 408; in the vertical direction, the depth of the first well region 410 is shallower than the depth of both the pillar region 404 and the trench gate structure 408.

[0096] like Figure 22 As shown, a second well region 412 is then formed in the silicon carbide epitaxial layer 402 on the second side 4062 of the trench gate structure 408. Here, the second well region 412 has a P-type conductivity, and its depth is greater than that of the first well region 410. Furthermore, the doping concentration of the second well region 412 is greater than that of the first well region 410. Similarly, a patterned mask layer can be formed on the silicon carbide epitaxial layer 402 using another photomask, exposing the silicon carbide epitaxial layer 402 on the second side 4062. Then, a P-type ion implantation process is performed on the exposed silicon carbide epitaxial layer 402 to form the second well region 412 within it.

[0097] The second well region 412 extends from the surface of the silicon carbide epitaxial layer 402 into the silicon carbide epitaxial layer 402. Further, in the horizontal direction, the two sides of the second well region 412 are respectively connected to the pillar region 404 and the trench gate structure 408; in the vertical direction, the depth of the second well region 412 is shallower than the depth of both the pillar region 404 and the trench gate structure 408.

[0098] Please refer to the following: Figure 23 A source region 414 is formed in the first well region 410 and the second well region 412, wherein the conductivity type of the source region 414 is N-type. Specifically, the source region 414 can be formed by performing N-type heavy doping on the first well region 410 and the second well region 412.

[0099] In this embodiment, the source region 414 extends from the surfaces of the first well region 410 and the second well region 412 into the first well region 410 and the second well region 412, meaning the depth of the source region 414 is shallower than the depth of the first well region 410 and the second well region 412. Furthermore, in the horizontal direction, both sides of the source region 414 are respectively connected to the pillar region 404, and the source region 414 is also connected to the trench gate structure 408, meaning the trench gate structure 408 passes through the source region 414.

[0100] Please refer to Figure 24 A metal gate electrode 416, a metal source electrode 418, and a metal drain electrode 420 are formed, wherein the metal gate electrode 416 and the metal source electrode 418 are located on the same side, and the metal drain electrode 420 is located on the other side. Specifically, the metal gate electrode 416 and the metal source electrode 418 are formed on the surface of the silicon carbide epitaxial layer 402, the metal gate electrode 416 is electrically connected to the trench gate structure 408; the metal source electrode 418 is electrically connected to the source region 414, wherein the metal...

[0101] The gate electrode 416 and the metal source electrode 418 can be isolated by a dielectric layer. The metal drain electrode 420 is formed on the surface of the silicon carbide substrate 400, where the silicon carbide substrate 400 serves as the drain region, and the metal drain electrode 420 is electrically connected to the silicon carbide substrate 400.

[0102] Please continue to refer to this. Figure 24 A silicon carbide MOS device 40 was formed by the aforementioned manufacturing method. The silicon carbide MOS device 40 includes: a silicon carbide substrate 400 and a silicon carbide MOS device formed on the substrate.

[0103] A silicon carbide epitaxial layer 402 on a silicon substrate 400, both the silicon carbide substrate 400 and the silicon carbide epitaxial layer 402 being of a first conductivity type; a trench gate structure 408 located within the silicon carbide epitaxial layer 402, wherein the crystal mobility of the second side 4062 of the trench gate structure 408 is higher than the crystal mobility of the first side 4060 of the trench gate structure 408; a first well region 410 and a second well region 412, both of which are of a second conductivity type, wherein the first well region 410 and the second well region 412 ...

[0104] The depth of the second well region 412 is greater than the depth of the first well region 410, and the doping concentration of the second well region 412 is greater than the doping concentration of the first well region 410. The first well region 410 is located in the silicon carbide epitaxial layer 402 of the first side 4060, and the second well region 412 is located in the silicon carbide epitaxial layer 402 of the second side 4062; and a source region 414, which is of a first conductivity type, is located in the first well region 410 and the second well region 412.

[0105] In this embodiment, the crystal plane mobility of the second side 4062 is higher than the 0 crystal plane mobility of the first side 4060. Correspondingly, the depth of the second well region 412 is deeper than the depth of the first well region 410.

[0106] Furthermore, the doping concentration of the second well region 412 is higher than that of the first well region 410. This balances the difference in gate turn-on consistency caused by the difference in crystal mobility on both sides of the trench gate structure 408, thereby improving the gate turn-on consistency and ultimately enhancing the performance and reliability of the silicon carbide MOS device 40.

[0107] 5. Furthermore, the silicon carbide MOS device 40 further includes: a pillar region 404, the pillar region 404 being of a second conductivity type, the pillar region 404 being located in the silicon carbide epitaxial layer 402 on the side of the first well region 410 and the second well region 412. A superjunction structure is formed through the pillar region 404, thereby improving the breakdown voltage characteristics of the formed silicon carbide MOS device, reducing the on-resistance and switching losses of the device, and increasing the switching frequency of the device.

[0108] Furthermore, in other implementations of this application, different combinations can be made according to the claims and the above embodiments to form different specific implementations. These will not be listed here. Those skilled in the art can make more variations based on the disclosed content without creative effort.

[0109] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A silicon carbide MOS device, characterized in that, The silicon carbide MOS device includes: A silicon carbide substrate and a silicon carbide epitaxial layer formed on the silicon carbide substrate, wherein both the silicon carbide substrate and the silicon carbide epitaxial layer are of a first conductivity type; A trench gate structure is located in the silicon carbide epitaxial layer, wherein the crystal mobility of the second side of the trench gate structure is higher than that of the first side of the trench gate structure. A first well region and a second well region, both of which are of the second conductivity type, wherein the second well region is deeper than the first well region and / or has a higher doping concentration than the first well region, the first well region is located in the silicon carbide epitaxial layer on the first side of the trench gate structure, and the second well region is located in the silicon carbide epitaxial layer on the second side of the trench gate structure; and... The source region is of a first conductivity type and is located in the first well region and the second well region.

2. The silicon carbide MOS device as described in claim 1, characterized in that, The crystal plane on the second side is a <11-20> crystal plane, and the crystal plane on the first side is not a <11-20> crystal plane.

3. The silicon carbide MOS device as described in claim 1 or 2, characterized in that, The silicon carbide MOS device further includes a pillar region, which is of a second conductivity type and is located in the silicon carbide epitaxial layer on the side of the first well region and the second well region.

4. The silicon carbide MOS device as described in claim 3, characterized in that, The depth of the column region is greater than the depth of the first well region and the second well region.

5. The silicon carbide MOS device as described in claim 4, characterized in that, The depth of the gate structure is deeper than the depth of the first well region and the second well region, and the depth of the gate structure is shallower than the depth of the pillar region.

6. The silicon carbide MOS device as described in claim 3, characterized in that, The silicon carbide MOS device further includes: a metal gate electrode electrically connected to the gate structure; a metal source electrode electrically connected to the source region; and a metal drain electrode electrically connected to the silicon carbide substrate.

7. A method for manufacturing a silicon carbide MOS device, characterized in that, The method for manufacturing the silicon carbide MOS device includes: A silicon carbide substrate is provided, wherein the silicon carbide substrate is of a first conductivity type; A silicon carbide epitaxial layer is formed on the silicon carbide substrate, wherein the silicon carbide epitaxial layer is of a first conductivity type; A trench gate structure is formed in the silicon carbide epitaxial layer, wherein the crystal mobility of the second side of the trench gate structure is higher than that of the first side of the trench gate structure. A first well region and a second well region are formed in the silicon carbide epitaxial layer. Both the first well region and the second well region are of a second conductivity type. The depth of the second well region is greater than the depth of the first well region and / or the doping concentration of the second well region is greater than that of the first well region. The first well region is located in the silicon carbide epitaxial layer on a first side of the trench gate structure, and the second well region is located in the silicon carbide epitaxial layer on a second side of the trench gate structure. Source regions are formed in the first well region and the second well region, wherein the source regions are of a first conductivity type.

8. The method for manufacturing a silicon carbide MOS device as described in claim 7, characterized in that, Before forming a trench gate structure in the silicon carbide epitaxial layer, the formation of a first well region and a second well region in the silicon carbide epitaxial layer is performed; or, after forming a trench gate structure in the silicon carbide epitaxial layer, the formation of a first well region and a second well region in the silicon carbide epitaxial layer is performed.

9. The method for manufacturing a silicon carbide MOS device as described in claim 8, characterized in that, The crystal plane on the second side is a <11-20> crystal plane, and the crystal plane on the first side is not a <11-20> crystal plane.

10. The method for manufacturing a silicon carbide MOS device according to any one of claims 7 to 9, characterized in that, The method for manufacturing the silicon carbide MOS device further includes: A pillar region is formed in the silicon carbide epitaxial layer. The pillar region is of a second conductivity type and is located on the side of the first well region and the second well region.

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