Compensation Method for Charging Time in Printed Circuit Board and Chip-on-Film

Abstract

Embodiments of the present application disclose a printed circuit board and a method for compensating the charging time in a flip chip thin film. The printed circuit board includes a substrate, a flip chip thin film, and test terminals. The flip chip thin film is provided with 960 interfaces along the long side direction of the substrate. At least four test terminals are correspondingly arranged for any flip chip thin film. The at least four test terminals include a first compensation test terminal, a second compensation test terminal, a first test terminal connected to the first interface on the flip chip thin film, and a second test terminal connected to the 960th interface on the flip chip thin film. The first compensation test terminal is connected to any one of the second interface to the 480th interface, and the second compensation test terminal is connected to any one of the 481st interface to the 959th interface. By enabling any flip chip thin film to be correspondingly connected with four test terminals, it is possible to measure and compensate the charging time of multiple fan-out traces in a single flip chip thin film.

Description

Technical Field

[0001] The present application relates to the field of display technology, and particularly to a printed circuit board and a method for compensating the charging time in a chip-on-film. Background Art

[0002] In large-size (≥75 inches) panel high-refresh-rate (≥120 Hz) products, in a monochromatic picture, due to the charging delay caused by the impedance of the fan-out traces, there is a phenomenon that the charging times are different among different fan-out traces within a single chip-on-film, resulting in bright bands or dark bands within a single chip-on-film, affecting the quality.

[0003] Please refer to Figure 1 , the current printed circuit board corresponds to only two test terminals for a single chip-on-film 20. Therefore, when measuring the charging time of the traces, the current printed circuit board can only compensate for the charging time difference between different chip-on-films, but cannot compensate for the charging time difference among the fan-out traces within a single chip-on-film. As a result, there is currently no simple and efficient method for the current printed circuit board design to test the charging time within a single chip-on-film. Therefore, there is a technical problem that there are bright bands or dark bands within a single chip-on-film in the existing printed circuit board. Summary of the Invention

[0004] Embodiments of the present application provide a printed circuit board and a method for compensating the charging time in a chip-on-film, which can alleviate the technical problem that there are bright bands or dark bands within a single chip-on-film in the existing printed circuit board.

[0005] Embodiments of the present application provide a printed circuit board, including:

[0006] A substrate;

[0007] At least two chip-on-films, the chip-on-films are disposed on the substrate, and 960 interfaces are disposed on the chip-on-films along the long side direction of the substrate;

[0008] Test terminals, at least four test terminals are correspondingly disposed for any one of the chip-on-films, the test terminals are connected to the interfaces one by one through connection traces, and the at least four test terminals include a first test terminal connected to the first interface on the chip-on-film and a second test terminal connected to the 960th interface on the chip-on-film;

[0009] Wherein, the at least four test terminals further include at least a first compensation test terminal and a second compensation test terminal, the first compensation test terminal is connected to any one of the second interface to the 480th interface, and the second compensation test terminal is connected to any one of the 481st interface to the 959th interface.

[0010] Optionally, in some embodiments of the present application, the number of interfaces between the interface corresponding to the first compensation test terminal and the interface corresponding to the first test terminal is equal to the number of interfaces between the interface corresponding to the second compensation test terminal and the interface corresponding to the second compensation test terminal.

[0011] Optionally, in some embodiments of the present application, adjacent interfaces are arranged at equal intervals, and the distance between the first compensation test terminal and the first test terminal is equal to the distance between the second compensation test terminal and the second test terminal.

[0012] Optionally, in some embodiments of the present application, the first compensation test terminal is correspondingly connected to the 480th interface, and the second compensation test terminal is correspondingly connected to the 481st interface.

[0013] Optionally, in some embodiments of the present application, the interface corresponding to the first compensation test terminal is connected to the first fan-out trace, the interface corresponding to the second compensation test terminal is connected to the second fan-out trace, the interface corresponding to the first test terminal is connected to the third fan-out trace, the interface corresponding to the second test terminal is connected to the fourth fan-out trace, the length of the third fan-out trace is greater than the length of the first fan-out trace, and the length of the fourth fan-out trace is greater than the length of the second fan-out trace.

[0014] Optionally, in some embodiments of the present application, the length of the first fan-out trace is equal to the length of the second fan-out trace.

[0015] Optionally, in some embodiments of the present application, the length of the third fan-out trace is equal to the length of the fourth fan-out trace.

[0016] Optionally, in some embodiments of the present application, the shapes and sizes of the first compensation test terminal, the second compensation test terminal, the first test terminal, and the second test terminal are the same.

[0017] Optionally, in some embodiments of the present application, the first compensation test terminal, the second compensation test terminal, the first test terminal, and the second test terminal are arranged side by side along the long side direction of the substrate, and the first compensation test terminal, the second compensation test terminal, the first test terminal, and the second test terminal are arranged at one end of the substrate close to the flip chip film.

[0018] An embodiment of the present application provides a method for compensating the charging time in a flip chip film, using the printed circuit board described in any of the above embodiments, including:

[0019] Providing one of the printed circuit boards;

[0020] Measure the charging time of the first test terminal and the first compensation test terminal of any flip chip thin film, estimate the charging time of each interface between the interface corresponding to the first test terminal and the interface corresponding to the first compensation test terminal, compensate for the charging time of the third fan-out wire corresponding to the first test terminal and the first fan-out wire corresponding to the first compensation test terminal, and compensate for each wire between the first test terminal and the first compensation test terminal one by one;

[0021] Measure the charging time of the second test terminal and the second compensation test terminal of the same flip chip thin film, estimate the charging time of each interface between the interface corresponding to the second test terminal and the interface corresponding to the second compensation test terminal, compensate for the charging time of the fourth fan-out wire corresponding to the second test terminal and the second fan-out wire corresponding to the second compensation test terminal, and compensate for each fan-out wire between the second test terminal and the second compensation test terminal one by one.

[0022] Beneficial effects: Any flip chip thin film is correspondingly connected with four test terminals. Among them, the first compensation test terminal is connected to any one of the 2nd interface to the 480th interface, and the second compensation test terminal is connected to any one of the 481st interface to the 959th interface; By measuring the charging time of the first test terminal and the first compensation test terminal, the charging time of the wire between the first test terminal and the first compensation test terminal can be compensated. Similarly, by measuring the charging time of the second test terminal and the second compensation test terminal, the charging time of the wire between the second test terminal and the second compensation test terminal can be compensated, so that the charging time within a single flip chip thin film can be measured and compensated, alleviating the technical problem of bright or dark bands existing in a single flip chip thin film in the existing printed circuit board. Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0024] Figure 1 is a cross-sectional schematic diagram of a printed circuit board provided by the prior art;

[0025] Figure 2 is a cross-sectional schematic diagram of a printed circuit board provided by the present application;

[0026] Figure 3 is an enlarged schematic diagram of a specific area 2 in the printed circuit board provided by the present application;

[0027] Figure 4 It is a schematic flow chart of the compensation method for the in-chip charging time provided by this application.

[0028] Explanation of the reference numerals:

[0029] Specific embodiments

[0030] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain this application, and are not used to limit this application. In this application, unless otherwise stated, the orientation terms such as "upper" and "lower" usually refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; and "inner" and "outer" refer to the outline of the device.

[0031] Please refer to Figure 2 、 Figure 3 The printed circuit board 1 provided by this application includes a substrate 10, a flip-chip thin film 20, and test terminals. The flip-chip thin film 20 is disposed on the substrate 10. There are 960 interfaces 30 disposed on the flip-chip thin film 20 along the long side direction of the substrate 10. Any one of the flip-chip thin films 20 is correspondingly provided with at least four test terminals. The test terminals and the interfaces 30 are connected in one-to-one correspondence through connection traces. The at least four test terminals include a first test terminal 40 connected to the first interface 30 on the flip-chip thin film 20 and a second test terminal 50 connected to the 960th interface 30 on the flip-chip thin film 20. Among them, the at least four test terminals further include at least a first compensation test terminal 60 and a second compensation test terminal 70. The first compensation test terminal 60 is connected to any one of the second interface 30 to the 480th interface 30, and the second compensation test terminal 70 is connected to any one of the 481st interface 30 to the 959th interface 30.

[0032] It can be understood that the length change rule of the fan-out traces corresponding to a single flip-chip thin film 20 is as follows: from the fan-out trace corresponding to the 480th interface 30 to the fan-out trace corresponding to the first interface 30, the length of the fan-out trace gradually increases; from the fan-out trace corresponding to the 481st interface 30 to the fan-out trace connected to the 960th interface 30, the length of the fan-out trace gradually increases.

[0033] Further, the length of the fan-out trace connected to the first interface 30 can be equal to that of the fan-out trace connected to the 960th interface 30, the length of the fan-out trace connected to the second interface 30 can be equal to that of the fan-out trace connected to the 959th interface 30, the length of the fan-out trace connected to the third interface 30 can be equal to that of the fan-out trace connected to the 958th interface 30, and so on... The length of the fan-out trace connected to the 480th interface 30 can be equal to that of the fan-out trace connected to the 481st interface 30.

[0034] In this embodiment, each flip-chip thin film 20 is correspondingly connected with four test terminals. Among them, the first compensation test terminal 60 is connected to any one of the second to 480th interfaces 30, and the second compensation test terminal 70 is connected to any one of the 481st to 959th interfaces 30. By measuring the charging time of the first test terminal 40 and the first compensation test terminal 60, the charging time of the fan-out trace between the first test terminal 40 and the first compensation test terminal 60 can be compensated. Similarly, by measuring the charging time of the second test terminal 50 and the second compensation test terminal 70, the charging time of the fan-out trace between the second test terminal 50 and the second compensation test terminal 70 can be compensated, so that the charging time within a single flip-chip thin film 20 can be measured and compensated, alleviating the technical problem of bright or dark bands existing within a single flip-chip thin film 20 in the existing printed circuit board 1.

[0035] The technical solution of the present application will now be described in combination with specific embodiments.

[0036] The following embodiments only illustrate with a flip-chip thin film 20 having 960 interfaces 30. The inventive concept of the present application should also include flip-chip thin films 20 with other numbers of interfaces 30. The number of flip-chip thin films 20 on the printed circuit board 1 can be 12, 24, etc., which are specifically selected according to the resolution of the panel and are not limited herein.

[0037] Further, the fact that the flip-chip thin film 20 includes 960 interfaces 30 means that it includes 960 effective interfaces 30 connected with fan-out traces. In some embodiments, the flip-chip thin film 20 includes 966 pins, and 6 of them are invalid interfaces 30, and no fan-out traces are connected to the invalid interfaces 30.

[0038] Further, Figure 3 For Figure 2 The enlarged schematic diagram of the specific area 2.

[0039] In one embodiment, please refer to Figure 3, the first compensation test terminal 60 is connected to its corresponding interface 30 through a first connection trace 120, the second test terminal 50 is connected to its corresponding interface 30 through a second connection trace 130, the first test terminal 40 is connected to the first interface 30 through a third connection trace 140, and the second test terminal 50 is connected to the 960th interface 30 through a fourth connection trace 150.

[0040] Among them, the first compensation test terminal 60 can be connected to any one of the second interface 30 to the 480th interface 30 through the first connection trace 120.

[0041] Among them, the second test terminal 50 is connected to any one of the 481st interface 30 to the 959th interface 30 through the second connection trace 130.

[0042] In an embodiment, the number of interfaces 30 between the interface 30 corresponding to the first compensation test terminal 60 and the interface 30 corresponding to the first test terminal 40 is equal to the number of interfaces 30 between the interface 30 corresponding to the second compensation test terminal 70 and the interface 30 corresponding to the second compensation test terminal 70.

[0043] Among them, the interface 30 corresponding to the first compensation test terminal 60 and the interface 30 corresponding to the second compensation test terminal 70 can be symmetrically arranged about the center line of the flip chip film 20.

[0044] It can be understood that when the interface 30 corresponding to the first compensation test terminal 60 and the interface 30 corresponding to the second compensation test terminal 70 are symmetrically arranged about the center line of the flip chip film 20, the length of the fan-out trace of the interface 30 corresponding to the first compensation test terminal 60 is equal to the fan-out trace of the interface 30 corresponding to the second compensation test terminal 70.

[0045] It should be noted that the charging time difference of the fan-out traces is mainly caused by the different lengths of the fan-out traces. On a single flip chip film 20, along the long side direction from both sides to the middle, the length of the fan-out traces gradually decreases. Therefore, the charging time of any one of the second interface 30 to the 480th interface 30 can be tested through the first compensation test terminal 60, so as to obtain the charging time between the first test terminal 40 and the first compensation test terminal 60, and then perform a linearly stepped compensation on the fan-out traces at other interfaces 30 between the two; similarly, the charging time of any one of the 481st interface 30 to the 959th interface 30 can be tested through the second compensation test terminal 70, so as to obtain the charging time between the second test terminal 50 and the second compensation test terminal 70, and then perform a linearly stepped compensation on the fan-out traces at other interfaces 30 between the two.

[0046] In one embodiment, the adjacent interfaces 30 are arranged at equal intervals, and the distance between the first compensation test terminal 60 and the first test terminal 40 is equal to the distance between the second compensation test terminal 70 and the second test terminal 50.

[0047] Among them, the first compensation test terminal 60 can be arranged in alignment with its corresponding interface 30, and the first test terminal 40 can be arranged in alignment with the first interface 30; further, the first compensation test terminal 60 is connected to its corresponding interface 30 through a straight-line trace, and the first test terminal 40 is connected to the first interface 30 through a straight-line trace.

[0048] Among them, the second compensation test terminal 70 can be arranged in alignment with its corresponding interface 30, and the second test terminal 50 can be arranged in alignment with the 960th interface 30; further, the second compensation test terminal 70 is connected to its corresponding interface 30 through a straight-line trace, and the second test terminal 50 is connected to the 960th interface 30 through a straight-line trace.

[0049] Among them, the distance between the interface 30 corresponding to the first compensation test terminal 60 and the interface 30 corresponding to the first test terminal 40 is equal to the distance between the interface 30 corresponding to the second compensation test terminal 70 and the interface 30 corresponding to the second test terminal 50.

[0050] In one embodiment, please refer to Figure 3 , the first compensation test terminal 60 is correspondingly connected to the 480th interface 30, and the second compensation test terminal 70 is correspondingly connected to the 481st interface 30.

[0051] It can be understood that the fan-out traces corresponding to the first interface 30 and the 960th interface 30 have the longest lengths, and the fan-out traces corresponding to the 480th interface 30 and the 481st interface 30 have the shortest lengths. By connecting the first compensation test terminal 60 to the 480th interface 30 correspondingly and the second compensation test terminal 70 to the 481st interface 30 correspondingly, the charging time when the length of the fan-out trace is the shortest can be measured; by connecting the first test terminal 40 to the first interface 30 correspondingly and the second test terminal 50 to the 960th interface 30 correspondingly, the charging time when the length of the fan-out trace is the longest can be measured. According to the longest charging time and the shortest charging time within the flip chip thin film 20, the charging times of the fan-out traces corresponding to each interface 30 between the second interface 30 and the 479th interface 30, and between the 482nd interface 30 and the 959th interface 30 can be estimated, so as to compensate the charging times of the fan-out traces corresponding to the first interface 30 to the 960th interface 30.

[0052] It should be noted that the compensation can be linear compensation or non-linear compensation; further, the compensation can be in a gradually changing form or in a gradient changing form.

[0053] In one embodiment, the interface 30 corresponding to the first compensation test terminal 60 is connected to the first fan-out trace 80, the interface 30 corresponding to the second compensation test terminal 70 is connected to the second fan-out trace 90, the interface 30 corresponding to the first test terminal 40 is connected to the third fan-out trace 100, the interface 30 corresponding to the second test terminal 50 is connected to the fourth fan-out trace 110, the length of the third fan-out trace 100 is greater than the length of the first fan-out trace 80, and the length of the fourth fan-out trace 110 is greater than the length of the second fan-out trace 90.

[0054] In one embodiment, in some embodiments of the present application, the length of the first fan-out trace 80 is equal to the length of the second fan-out trace 90.

[0055] In one embodiment, in some embodiments of the present application, the length of the third fan-out trace 100 is equal to the length of the fourth fan-out trace 110.

[0056] In one embodiment, the shapes and sizes of the first compensation test terminal 60, the second compensation test terminal 70, the first test terminal 40, and the second test terminal 50 are the same.

[0057] In one embodiment, the first compensation test terminal 60, the second compensation test terminal 70, the first test terminal 40, and the second test terminal 50 are arranged side by side along the long side direction of the substrate 10, and the first compensation test terminal 60, the second compensation test terminal 70, the first test terminal 40, and the second test terminal 50 are disposed at one end of the substrate 10 close to the flip chip film 20.

[0058] In one embodiment, the number of the flip chip films 20 can be 12 or 24.

[0059] Please refer to Figure 4 , the method for compensating the charging time in the flip chip film 20 of the embodiment of the present application includes:

[0060] S1: Provide one of the printed circuit boards 1;

[0061] S2: Measure the charging time of the first test terminal 40 and the first compensation test terminal 60 of any flip chip film 20, estimate the charging time of each interface 30 between the interface 30 corresponding to the first test terminal 40 and the interface 30 corresponding to the first compensation test terminal 60, compensate the charging time of the third fan-out trace 100 corresponding to the first test terminal 40 and the first fan-out trace 80 corresponding to the first compensation test terminal 60, and compensate each trace between the first test terminal 40 and the first compensation test terminal 60 one by one;

[0062] S3: Measure the charging time of the second test terminal 50 and the second compensation test terminal 70 of the same flip chip film 20, estimate the charging time of each interface 30 between the interface 30 corresponding to the second test terminal 50 and the interface 30 corresponding to the second compensation test terminal 70, compensate the charging time of the fourth fan-out trace 110 corresponding to the second test terminal 50 and the second fan-out trace 90 corresponding to the second compensation test terminal 70, and compensate each fan-out trace between the second test terminal 50 and the second compensation test terminal 70 one by one.

[0063] Wherein, the first compensation test terminal 60 and the second compensation test terminal 70 can be obtained by using the preparation method of the existing test terminal, without additional new processes, reducing the cost.

[0064] It can be understood that when the number of interfaces 30 between the interface 30 corresponding to the first compensation test terminal 60 and the interface 30 corresponding to the first test terminal 40 is equal to the number of interfaces 30 between the interface 30 corresponding to the second compensation test terminal 70 and the interface 30 corresponding to the second compensation test terminal 70, step S3 can compensate the charging time of each interface 30 between the interface 30 corresponding to the second test terminal 50 and the interface 30 corresponding to the second compensation test terminal 70 with reference to step S2, without measuring and estimating the second test terminal 50 and the second compensation test terminal 70, further reducing the cost.

[0065] In this embodiment, it is possible to estimate the charging time of different fan-out traces in a single flip-chip thin film 20, so as to perform appropriate compensation, alleviating the technical problem of bright bands or dark bands existing in a single flip-chip thin film 20 in the existing printed circuit board 1.

[0066] This application also provides a display panel, a display module, and a display device. The display panel, the display module, and the display device all include the above-mentioned printed circuit board, which will not be elaborated here.

[0067] The printed circuit board provided in this embodiment includes a substrate, a flip-chip thin film, and test terminals. The flip-chip thin film is disposed on the substrate. There are 960 interfaces arranged along the long side direction of the substrate on the flip-chip thin film. Any flip-chip thin film is correspondingly provided with at least four test terminals. The test terminals are connected to the interfaces one by one through connection traces. The at least four test terminals include a first test terminal connected to the first interface on the flip-chip thin film and a second test terminal connected to the 960th interface on the flip-chip thin film. Among them, the at least four test terminals further include at least a first compensation test terminal and a second compensation test terminal. The first compensation test terminal is connected to any one of the interfaces from the second interface to the 480th interface, and the second compensation test terminal is connected to any one of the interfaces from the 481st interface to the 959th interface. So that any flip-chip thin film is correspondingly connected with four test terminals. Among them, the first compensation test terminal is connected to any one of the interfaces from the second interface to the 480th interface, and the second compensation test terminal is connected to any one of the interfaces from the 481st interface to the 959th interface. By measuring the charging time of the first test terminal and the first compensation test terminal, it is possible to compensate the charging time of the fan-out traces between the first test terminal and the first compensation test terminal. Similarly, by measuring the charging time of the second test terminal and the second compensation test terminal, it is possible to compensate the charging time of the fan-out traces between the second test terminal and the second compensation test terminal, so as to be able to measure and compensate the charging time in a single flip-chip thin film, alleviating the technical problem of bright bands or dark bands existing in a single flip-chip thin film in the existing printed circuit board.

[0068] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0069] The printed circuit board and the method for compensating the charging time in the flip chip film provided by the embodiments of the present application have been introduced in detail above. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A printed circuit board, characterized in that, Comprising: A substrate; At least two flip-chip thin films disposed on the substrate, and 960 interfaces are provided on the flip-chip thin films along the long side direction of the substrate; Test terminals, at least four test terminals are correspondingly provided for any one of the flip-chip thin films, and the test terminals and the interfaces are connected in one-to-one correspondence through connection traces. The at least four test terminals include a first test terminal connected to the first interface on the flip-chip thin film and a second test terminal connected to the 960th interface on the flip-chip thin film; Wherein, the at least four test terminals further include at least a first compensation test terminal and a second compensation test terminal. The first compensation test terminal is connected to any one of the interfaces from the second interface to the 480th interface, and the second compensation test terminal is connected to any one of the interfaces from the 481st interface to the 959th interface.

2. The printed circuit board according to claim 1, wherein The number of interfaces between the interface corresponding to the first compensation test terminal and the interface corresponding to the first test terminal is equal to the number of interfaces between the interface corresponding to the second compensation test terminal and the interface corresponding to the second compensation test terminal.

3. The printed circuit board according to claim 2, characterized in that, Adjacent interfaces are arranged at equal intervals, and the distance between the first compensation test terminal and the first test terminal is equal to the distance between the second compensation test terminal and the second test terminal.

4. The printed circuit board according to claim 1, wherein The first compensation test terminal is correspondingly connected to the 480th interface, and the second compensation test terminal is correspondingly connected to the 481st interface.

5. The printed circuit board according to claim 1, wherein, The interface corresponding to the first compensation test terminal is connected to a first fan-out trace, the interface corresponding to the second compensation test terminal is connected to a second fan-out trace, the interface corresponding to the first test terminal is connected to a third fan-out trace, and the interface corresponding to the second test terminal is connected to a fourth fan-out trace. The length of the third fan-out trace is greater than the length of the first fan-out trace, and the length of the fourth fan-out trace is greater than the length of the second fan-out trace.

6. The printed circuit board according to claim 5, characterized in that, The length of the first fan-out trace is equal to the length of the second fan-out trace.

7. The printed circuit board according to claim 5, wherein The length of the third fan-out trace is equal to the length of the fourth fan-out trace.

8. The printed circuit board according to claim 1, characterized in that, The shapes and sizes of the first compensation test terminal, the second compensation test terminal, the first test terminal, and the second test terminal are the same.

9. The printed circuit board according to claim 1, wherein The first compensation test terminal, the second compensation test terminal, the first test terminal, and the second test terminal are arranged side by side along the long side direction of the substrate, and the first compensation test terminal, the second compensation test terminal, the first test terminal, and the second test terminal are disposed at one end of the substrate close to the flip-chip thin film.

10. A method for compensating the charging time in a flip-chip thin film, characterized in that, Using the printed circuit board according to any one of claims 5 to 7, comprising: Providing one such printed circuit board; Measuring the charging time of the first test terminal and the first compensation test terminal of any flip-chip thin film, estimating the charging time of each interface between the interface corresponding to the first test terminal and the interface corresponding to the first compensation test terminal, compensating the charging time of the third fan-out trace corresponding to the first test terminal and the first fan-out trace corresponding to the first compensation test terminal, and compensating each fan-out trace between the first test terminal and the first compensation test terminal one by one; Measure the charging times of the second test terminal and the second compensation test terminal of the same flip chip thin film, estimate the charging times of the interfaces between the interface corresponding to the second test terminal and the interface corresponding to the second compensation test terminal, compensate for the charging times of the fourth fan-out wiring corresponding to the second test terminal and the second fan-out wiring corresponding to the second compensation test terminal, and compensate for each fan-out wiring between the second test terminal and the second compensation test terminal one by one.

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