High-order temperature-compensated bandgap reference circuit for low-dropout linear regulator ICs

Abstract

The present invention claims a high-order temperature compensation bandgap reference circuit for a low voltage drop linear regulator chip, comprising (μ n ) ‑1 Bias current generating circuit, (μ n ) ‑3 (V THn ) ‑2 Bias current generating circuit and bandgap reference core circuit. The present invention uses MOS tubes M7-M8, M12-M13 and M10 to form a negative feedback loop, uses MOS tubes M7-M9 to form a positive feedback loop, and resistors R2 and capacitors C2 form a low-pass filter and reduce the positive feedback loop gain to ensure circuit stability; the bias current generating circuit provides a bias current for the bandgap reference core circuit to generate a current I with a high-order temperature characteristic. Q2 , effectively compensates for V EB1 The high-order temperature nonlinearity is reduced, thereby obtaining a high-order compensated bandgap reference voltage, and further realizing a high-order temperature compensated bandgap reference circuit.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a high-order temperature compensation bandgap reference circuit for a low-voltage difference linear regulator chip. Background Art

[0002] The bandgap reference voltage source (BGR) is one of the core circuits of the low-dropout linear regulator chip, and its accuracy directly affects the overall performance of the low-dropout linear regulator chip.

[0003] Figure 1 This is a schematic diagram of a traditional bandgap reference circuit, which is mainly composed of amplifier A1, amplifier A2, PMOS tube M1, PMOS tube M2, PMOS tube M3, PMOS tube M4, PMOS tube M5, PNP transistor Q1, PNP transistor Q2, resistor R1, resistor R2 and resistor R3. M1 to M5 are MOS tubes of the same size. The emitter area of ​​PNP transistor Q2 is n times the emitter area of ​​PNP transistor Q1. All resistors are made of the same material. Then the output voltage of the output terminal VREF of the bandgap reference circuit is Where R1 is the resistance value of resistor R1, R2 is the resistance value of resistor R2, R3 is the resistance value of resistor R3, V T is the thermal voltage, V EB1 is the emitter-base voltage of the PNP transistor Q1. By optimizing the resistance values ​​of resistors R1 and R2 and parameter n, a reference voltage V with zero temperature drift characteristics can be obtained within a certain temperature range. REF . Since V EB1 The traditional first-order bandgap reference circuit has temperature nonlinearity, so the output voltage has a high temperature drift coefficient, which greatly limits the application of the traditional first-order bandgap reference circuit in high-precision systems. Summary of the invention

[0004] The present invention aims to solve the above problems of the prior art. A method is proposed. The technical solution of the present invention is as follows:

[0005] A high-order temperature compensation bandgap reference circuit for a low-dropout linear regulator chip, comprising (μ n ) -1 Bias current generating circuit, (μ n ) -3 (V THn ) -2 Bias current generating circuit and bandgap reference core circuit, wherein the (μ n ) -1 The signal output terminals of the bias current generating circuit are respectively connected to the (μ n ) -3 (V THn ) -2The bias current generating circuit and the signal input end of the bandgap reference core circuit, the (μ n ) -3 (V THn ) -2 The signal output end of the bias current generating circuit and the signal input end of the bandgap reference core circuit; the (μ n ) -1 Bias current generating circuit and (μ n ) -3 (V THn ) -2 The bias current generating circuit provides a bias current related to temperature for the bandgap reference core circuit, and the bandgap reference core circuit generates a bandgap reference voltage with high performance characteristics at the output terminal VREF.

[0006] Furthermore, the (μ n ) -1 The bias current generating circuit comprises: a PMOS tube Ms1, a PMOS tube Ms2, an NMOS tube Ms3, an NMOS tube Ms4, a PMOS tube M1, a PMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6 and a resistor R1, wherein the source of the PMOS tube Ms1 is respectively connected to the source of the PMOS tube M1, the source of the PMOS tube M2 and an external power supply VDD, the gate of the PMOS tube Ms1 is respectively connected to the drain of the PMOS tube Ms1 and the source of the PMOS tube Ms2, the gate of the PMOS tube Ms2 is respectively connected to the drain of the PMOS tube Ms2, the gate of the NMOS tube Ms3 and the drain of the NMOS tube Ms4, the drain of the PMOS tube M1 is respectively connected to the gate of the PMOS tube M1, the gate of the PMOS tube M2 and the drain of the NMOS tube Ms4, the drain of the PMOS tube M1 is respectively connected to the gate of the PMOS tube M1, the gate of the PMOS tube M2 and the drain of the NMOS tube Ms3, and the drain of the NMOS tube Ms4. The gate of the PMOS tube M2 is connected to the gate of the NMOS tube M3, the gate of the PMOS tube M20, the gate of the PMOS tube M23, the drain of the NMOS tube Ms3 and the drain of the NMOS tube M3, the source of the NMOS tube M3 is connected to the drain of the NMOS tube M5, the source of the NMOS tube M5 is connected to one end of the resistor R1, the other end of the resistor R1 is respectively connected to the source of the NMOS tube Ms4, the source of the NMOS tube Ms3, the source of the NMOS tube M6 and the external ground GND, the drain of the PMOS tube M2 is respectively connected to the gate of the NMOS tube M3, the gate of the NMOS tube M4 and the drain of the NMOS tube M4, the source of the NMOS tube M4 is respectively connected to the gate of the NMOS tube Ms4, the gate of the NMOS tube M5, the gate of the NMOS tube M6 and the drain of the NMOS tube M6.

[0007] Furthermore, the (μ n ) -3 (V THn ) -2The bias current generating circuit includes: a PMOS tube Ms5, a PMOS tube Ms6, an NMOS tube Ms7, an NMOS tube Ms8, a PMOS tube M7, an NMOS tube M8, a PMOS tube M9, an NMOS tube M10, an NMOS tube M11, a PMOS tube M12, an NMOS tube M13, a PMOS tube M14, a PMOS tube M15, a PMOS tube M16, a PMOS tube M17, a PMOS tube M18, a PMOS tube M19, a PMOS tube M20, a PMOS tube M21, an amplifier A3, a resistor R2, a capacitor C1 and a capacitor C2, wherein the source of the PMOS tube Ms5 is respectively connected to the source of the PMOS tube M7, the source of the PMOS tube M9, one end of the capacitor C2, The source of the PMOS tube M12, the source of the PMOS tube M14, the PMOS tube M16, the PMOS tube M18, the PMOS tube M20 and the external power supply VDD are connected, the gate of the PMOS tube Ms5 is respectively connected to the drain of the PMOS tube Ms5 and the source of the PMOS tube Ms6, the gate of the PMOS tube Ms6 is respectively connected to the drain of the PMOS tube Ms6, the gate of the NMOS tube Ms7 and the drain of the NMOS tube Ms8, the gate of the PMOS tube M7 is respectively connected to the gate of the PMOS tube M12, one end of the resistor R2, the gate of the PMOS tube M14, the drain of the PMOS tube M7, the drain of the NMOS tube Ms7 and the drain of the NMOS tube M8, the gate of the PMOS tube M9 is respectively connected to the gate of the PMOS tube M12, one end of the resistor R2, the gate of the PMOS tube M14, the drain of the PMOS tube M7, the drain of the NMOS tube Ms7 and the drain of the NMOS tube M8, the gate of the PMOS tube M9 is respectively connected to the gate of the PMOS tube M12, the one end of the resistor R2, the gate of the PMOS tube M14, the drain of the PMOS tube M7, the drain of the NMOS tube Ms7 and the drain of the NMOS tube M8 The gate is respectively connected to the other end of the capacitor C2 and the other end of the resistor R2, the drain of the PMOS tube M9 is respectively connected to the drain of the NMOS tube M10, the gate of the NMOS tube M8, the gate of the NMOS tube Ms8 and one end of the capacitor C1, the other end of the capacitor C1 is respectively connected to the source of the NMOS tube Ms8, the source of the NMOS tube Ms7, the source of the NMOS tube M8, the source of the NMOS tube M11, the source of the NMOS tube M13, the drain of the PMOS tube M15, the gate of the PMOS tube M15, the drain of the PMOS tube M17, the drain of the PMOS tube M19, the gate of the PMOS tube M21, the drain of the PMOS tube M21 and the external ground GND, the The gate is respectively connected to the gate of the NMOS tube M13, the drain of the NMOS tube M13 and the drain of the PMOS tube M12, the source of the NMOS tube M10 is respectively connected to the drain of the NMOS tube M11 and the gate of the NMOS tube M11, the drain of the PMOS tube M14 is respectively connected to the gate of the PMOS tube M17 and the source of the PMOS tube M15, the gate of the PMOS tube M16 is respectively connected to the output end of the amplifier A3 and the gate of the PMOS tube M24, the drain of the PMOS tube M16 is respectively connected to the non-inverting input end of the amplifier A3 and the source of the PMOS tube M17, the drain of the PMOS tube M18 is respectively connected to the inverting input end of the amplifier A3 and the source of the PMOS tube M19,The drain of the PMOS tube M20 is connected to the gate of the PMOS tube M19 and the source of the PMOS tube M21 respectively.

[0008] Further, the bandgap reference core circuit includes: PMOS tube Ms8, PMOS tube Ms9, NMOS tube Ms10, NMOS tube Ms11, NMOS tube Ms12, PMOS tube M22, PMOS tube M23, PMOS tube M24, PMOS tube M25, PMOS tube M26, PMOS tube M27, amplifier A1, amplifier A2, resistor R3, resistor R4, resistor R5, PNP transistor Q1 and PNP transistor Q2, wherein the source of PMOS tube Ms8 is connected to the source of PMOS tube M22 and the source of PMOS tube M23 respectively. , the source of the PMOS tube M24, the source of the PMOS tube M25, the source of the PMOS tube M26, the source of the PMOS tube M27 and the external power supply VDD, the gate of the PMOS tube Ms8 is respectively connected to the drain of the PMOS tube Ms8 and the source of the PMOS tube Ms9, the gate of the PMOS tube Ms9 is respectively connected to the drain of the PMOS tube Ms9, the drain of the NMOS tube Ms10, the gate of the NMOS tube Ms11 and the gate of the NMOS tube Ms12, the gate of the PMOS tube M22 is respectively connected to the drain of the NMOS tube Ms12, the output terminal of the amplifier A1 and the output terminal of the amplifier A2. The gate of the PMOS tube M25 is connected to the gate of the PMOS tube M27, the output end of the amplifier A2 and the drain of the NMOS tube Ms11. The drain of the PMOS tube M25 is connected to the gate of the PMOS tube M27, the output end of the amplifier A2 and the drain of the NMOS tube Ms11. The drain of the PMOS tube M25 is connected to the gate of the PMOS tube M27, the output end of the amplifier A2 and the drain of the NMOS tube Ms11. The drain of the PMOS tube M25 is connected to the gate of the PMOS tube M27, the output end of the amplifier A2 and the drain of the NMOS tube Ms11. The phase input terminal is connected to one end of the resistor R4, the other end of the resistor R4 is connected to the emitter of the PNP transistor Q2, the drain of the PMOS tube M26 is respectively connected to the drain of the PMOS tube M27, one end of the resistor R5 and the circuit output terminal VREF, the other end of the resistor R5 is respectively connected to the source of the NMOS tube Ms10, the source of the NMOS tube Ms11, the source of the NMOS tube Ms12, the other end of the resistor R3, the base of the PNP transistor Q1, the collector of the PNP transistor Q1, the base of the PNP transistor Q2, the collector of the PNP transistor Q2 and the external ground GND.

[0009] Furthermore, the (μ n ) -1In the bias current generating circuit, the PMOS tube M1 is exactly the same as the PMOS tube M2, the NMOS tube M3 is exactly the same as the NMOS tube M4, the channel width-to-length ratio of the NMOS tube M5 is β times that of the NMOS tube M6, and the drain current I1 of the PMOS tube M1 is Among them, μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, (W / L)6 is the channel width-to-length ratio of the NMOS tube M6, and R1 is the resistance value of the resistor R1.

[0010] Furthermore, the (μ n ) -3 (V THn ) -2 In the bias current generating circuit, NMOS tube M8, PMOS tube M7, PMOS tube M12, NMOS tube M13 and NMOS tube M10 form a negative feedback loop, NMOS tube M8, PMOS tube M7 and PMOS tube M9 form a positive feedback loop, capacitor C1 ensures that the gate of NMOS tube M8 is the low-frequency main pole in the negative feedback loop, resistor R2 and capacitor C2 form a low-pass filter and reduce the positive feedback loop gain, so that the positive feedback loop gain is less than the negative feedback loop gain, ensuring the stability of the circuit. PMOS tube M7, PMOS tube M9 and PMOS tube M12 have the same channel width-to-length ratio, NMOS tube M8 and NMOS tube M13 have the same channel width-to-length ratio, so that NMOS tube M10 and NMOS tube M13 have the same gate, then the drain current I7 of PMOS tube M7 has Among them, (W / L) 13 is the channel width-to-length ratio of the NMOS tube M13, (W / L) 11 is the channel width-to-length ratio of the NMOS tube M11, (W / L) 10 is the channel width-to-length ratio of the NMOS tube M10, V THn is the threshold voltage of the NMOS tube. PMOS tubes M15, M17, M19 and M21 are identical and all operate in the subthreshold region. The low-frequency gain A of amplifier A3 is d >>1. PMOS tube M14 and PMOS tube M7 have the same channel width-to-length ratio, PMOS tube M18, PMOS tube M20 and PMOS tube M1 have the same channel width-to-length ratio, then the drain current I of PMOS tube M16 16 For I 16 =(I1) 2 / I7.

[0011] Furthermore, in the bandgap reference core circuit, all resistors are made of the same material, the channel width-to-length ratio of the PMOS tube M23 is K1 times that of the PMOS tube M1, the channel width-to-length ratio of the PMOS tube M24 is K2 times that of the PMOS tube M16, and the emitter area of ​​the PNP transistor Q2 is N times that of the PNP transistor Q1. Then, the emitter current I of the PNP transistor Q1 is Q1 =K1I1+K2I 16 , the emitter current I of the PNP transistor Q2 Q2 = Among them, V t is the thermal voltage, R4 is the resistance value of resistor R4. The gain of amplifier A1 is much greater than 1 and the voltage of the in-phase input terminal of the forced amplifier is equal to the voltage of the inverting input terminal. The channel width-to-length ratio of PMOS tube M26 is K3 times that of PMOS tube M22, and the channel width-to-length ratio of PMOS tube M27 is K4 times that of PMOS tube M25. Then the output voltage V of the circuit output terminal VREF is REF for Among them, V EB1 is the emitter-base voltage of PNP transistor Q1, R3 is the resistance value of resistor R3, and R5 is the resistance value of resistor R5. In fact, the electron mobility μ n With temperature T n ∝T -1.5 , NMOS threshold voltage V THn With temperature T, V THn =V TH0 -a0(T-T0), where T0 is the reference temperature, V TH0 is the reference temperature T 0处 The threshold voltage, a0 is the temperature coefficient of the threshold voltage, so I Q2 Has high-order temperature characteristics, which can effectively compensate for V EB1 The temperature high-order nonlinearity is reduced, thereby obtaining a high-order compensated bandgap reference voltage.

[0012] The advantages and beneficial effects of the present invention are as follows:

[0013] The present invention provides a high-order temperature compensation bandgap reference circuit for a low-voltage difference linear regulator chip, adopts NMOS tube M8, PMOS tube M7, PMOS tube M12, PMOS tube M13 and NMOS tube M10 to form a negative feedback loop, adopts NMOS tube M8, PMOS tube M7 and PMOS tube M9 to form a positive feedback loop, and resistor R2 and capacitor C2 form a low-pass filter and reduce the positive feedback loop gain to ensure circuit stability; adopts (μ n ) -1 Bias current generating circuit and (μ n ) -3 (V TH )-2 The bias current generation circuit provides bias current for the bandgap reference core circuit and generates a current I with high-order temperature characteristics. Q2 , effectively compensates for V EB1 The temperature high-order nonlinearity is reduced, so as to obtain a high-order compensated bandgap reference voltage, and then realize a high-order temperature compensated bandgap reference circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is the schematic diagram of the traditional bandgap reference circuit;

[0015] Figure 2 A schematic diagram of a high-order temperature compensation bandgap reference circuit for a low voltage drop linear regulator chip is provided for a preferred embodiment of the present invention;

[0016] Figure 3 A temperature characteristic simulation diagram of a high-order temperature compensation bandgap reference circuit for a low voltage drop linear regulator chip is provided for a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following will describe the technical solutions in the embodiments of the present invention in detail in conjunction with the accompanying drawings in the embodiments of the present invention. The described embodiments are only part of the embodiments of the present invention.

[0018] The technical solution of the present invention to solve the above technical problems is:

[0019] In the embodiment of the present application, NMOS tube M8, PMOS tube M7, PMOS tube M12, PMOS tube M13 and NMOS tube M10 are used to form a negative feedback loop, and NMOS tube M8, PMOS tube M7 and PMOS tube M9 are used to form a positive feedback loop. Resistor R2 and capacitor C2 form a low-pass filter and reduce the positive feedback loop gain to ensure circuit stability; (μ n ) -1 Bias current generating circuit and (μ n ) -3 (V TH ) -2 The bias current generation circuit provides bias current for the bandgap reference core circuit and generates a current I with high-order temperature characteristics. Q2 , effectively compensates for V EB1 The temperature high-order nonlinearity is reduced, so as to obtain a high-order compensated bandgap reference voltage, and then realize a high-order temperature compensated bandgap reference circuit.

[0020] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0021] Example

[0022] A high-order temperature-compensated bandgap reference circuit for low-dropout linear regulator chips, such as Figure 2 As shown, including (μ n ) -1 Bias current generating circuit 1, (μ n ) -3 (V THn ) -2 A bias current generating circuit 2 and a bandgap reference core circuit 3;

[0023] Among them, the (μ n ) -1 The signal output terminals of the bias current generating circuit 1 are respectively connected to the (μ n ) -3 (V THn ) -2 The bias current generating circuit 2 and the signal input end of the bandgap reference core circuit 3, the (μ n ) -3 (V THn ) -2 The signal output end of the bias current generating circuit 2 and the signal input end of the bandgap reference core circuit 3; the (μ n ) -1 Bias current generating circuit 1 and (μ n ) -3 (V THn ) -2 The bias current generating circuit 2 provides a bias current related to temperature for the bandgap reference core circuit 3 , and the bandgap reference core circuit 3 generates a bandgap reference voltage with high performance characteristics at the output terminal VREF.

[0024] As a preferred technical solution, Figure 2 As shown, the (μ n ) -1The bias current generating circuit 1 comprises: a PMOS tube Ms1, a PMOS tube Ms2, an NMOS tube Ms3, an NMOS tube Ms4, a PMOS tube M1, a PMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6 and a resistor R1, wherein the source of the PMOS tube Ms1 is respectively connected to the source of the PMOS tube M1, the source of the PMOS tube M2 and an external power supply VDD, the gate of the PMOS tube Ms1 is respectively connected to the drain of the PMOS tube Ms1 and the source of the PMOS tube Ms2, the gate of the PMOS tube Ms2 is respectively connected to the drain of the PMOS tube Ms2, the gate of the NMOS tube Ms3 and the drain of the NMOS tube Ms4, the drain of the PMOS tube M1 is respectively connected to the gate of the PMOS tube M1, the gate of the PMOS tube M2 and the drain of the NMOS tube Ms4, the drain of the PMOS tube M1 is respectively connected to the gate of the PMOS tube M1, the gate of the PMOS tube M2 and the drain of the NMOS tube Ms4. The gate of the PMOS tube M2 is connected to the gate of the NMOS tube M3, the gate of the PMOS tube M20, the gate of the PMOS tube M23, the drain of the NMOS tube Ms3 and the drain of the NMOS tube M3, the source of the NMOS tube M3 is connected to the drain of the NMOS tube M5, the source of the NMOS tube M5 is connected to one end of the resistor R1, the other end of the resistor R1 is respectively connected to the source of the NMOS tube Ms4, the source of the NMOS tube Ms3, the source of the NMOS tube M6 and the external ground GND, the drain of the PMOS tube M2 is respectively connected to the gate of the NMOS tube M3, the gate of the NMOS tube M4 and the drain of the NMOS tube M4, the source of the NMOS tube M4 is respectively connected to the gate of the NMOS tube Ms4, the gate of the NMOS tube M5, the gate of the NMOS tube M6 and the drain of the NMOS tube M6.

[0025] The (μ n ) -3 (V THn ) -2The bias current generating circuit 2 includes: a PMOS tube Ms5, a PMOS tube Ms6, an NMOS tube Ms7, an NMOS tube Ms8, a PMOS tube M7, an NMOS tube M8, a PMOS tube M9, an NMOS tube M10, an NMOS tube M11, a PMOS tube M12, an NMOS tube M13, a PMOS tube M14, a PMOS tube M15, a PMOS tube M16, a PMOS tube M17, a PMOS tube M18, a PMOS tube M19, a PMOS tube M20, a PMOS tube M21, an amplifier A3, a resistor R2, a capacitor C1 and a capacitor C2, wherein the source of the PMOS tube Ms5 is respectively connected to the source of the PMOS tube M7, the source of the PMOS tube M9 and one end of the capacitor C2. , the source of the PMOS tube M12, the source of the PMOS tube M14, the PMOS tube M16, the PMOS tube M18, the PMOS tube M20 and the external power supply VDD, the gate of the PMOS tube Ms5 is respectively connected to the drain of the PMOS tube Ms5 and the source of the PMOS tube Ms6, the gate of the PMOS tube Ms6 is respectively connected to the drain of the PMOS tube Ms6, the gate of the NMOS tube Ms7 and the drain of the NMOS tube Ms8, the gate of the PMOS tube M7 is respectively connected to the gate of the PMOS tube M12, one end of the resistor R2, the gate of the PMOS tube M14, the drain of the PMOS tube M7, the drain of the NMOS tube Ms7 and the drain of the NMOS tube M8, the gate of the PMOS tube M9 ... the source of the PMOS tube M14, the drain of the PMOS tube M7, the drain of the NMOS tube Ms7 and the drain of the NMOS tube M8, the gate of the PMOS tube M9 is respectively connected to the gate of the PMOS tube M12, the source of the PMOS tube M14, the drain of the PMOS tube M7, the drain of the NMOS tube Ms7 and the drain of the NMOS tube The gate is respectively connected to the other end of the capacitor C2 and the other end of the resistor R2, the drain of the PMOS tube M9 is respectively connected to the drain of the NMOS tube M10, the gate of the NMOS tube M8, the gate of the NMOS tube Ms8 and one end of the capacitor C1, the other end of the capacitor C1 is respectively connected to the source of the NMOS tube Ms8, the source of the NMOS tube Ms7, the source of the NMOS tube M8, the source of the NMOS tube M11, the source of the NMOS tube M13, the drain of the PMOS tube M15, the gate of the PMOS tube M15, the drain of the PMOS tube M17, the drain of the PMOS tube M19, the gate of the PMOS tube M21, the drain of the PMOS tube M21 and the external ground GND, the The gate is respectively connected to the gate of the NMOS tube M13, the drain of the NMOS tube M13 and the drain of the PMOS tube M12, the source of the NMOS tube M10 is respectively connected to the drain of the NMOS tube M11 and the gate of the NMOS tube M11, the drain of the PMOS tube M14 is respectively connected to the gate of the PMOS tube M17 and the source of the PMOS tube M15, the gate of the PMOS tube M16 is respectively connected to the output end of the amplifier A3 and the gate of the PMOS tube M24, the drain of the PMOS tube M16 is respectively connected to the non-inverting input end of the amplifier A3 and the source of the PMOS tube M17, the drain of the PMOS tube M18 is respectively connected to the inverting input end of the amplifier A3 and the source of the PMOS tube M19,The drain of the PMOS tube M20 is connected to the gate of the PMOS tube M19 and the source of the PMOS tube M21 respectively.

[0026] The bandgap reference core circuit 3 includes: PMOS tube Ms8, PMOS tube Ms9, NMOS tube Ms10, NMOS tube Ms11, NMOS tube Ms12, PMOS tube M22, PMOS tube M23, PMOS tube M24, PMOS tube M25, PMOS tube M26, PMOS tube M27, amplifier A1, amplifier A2, resistor R3, resistor R4, resistor R5, PNP transistor Q1 and PNP transistor Q2, wherein the source of PMOS tube Ms8 is connected to the source of PMOS tube M22, the source of PMOS tube M23 ...7, PMOS tube M28, PMOS tube M29, PMOS tube M30, PMOS tube M31, PMOS tube M32, PMOS tube M33, PMOS tube M34, PMOS tube M35, PMOS tube M36, PMOS tube M37, amplifier A1, amplifier A2, resistor R3, resistor R4, resistor R5, PNP transistor Q1 and PNP transistor Q2, The source of the OS tube M24, the source of the PMOS tube M25, the source of the PMOS tube M26, the source of the PMOS tube M27 and the external power supply VDD are connected, the gate of the PMOS tube Ms8 is respectively connected to the drain of the PMOS tube Ms8 and the source of the PMOS tube Ms9, the gate of the PMOS tube Ms9 is respectively connected to the drain of the PMOS tube Ms9, the drain of the NMOS tube Ms10, the gate of the NMOS tube Ms11 and the gate of the NMOS tube Ms12, the gate of the PMOS tube M22 is respectively connected to the drain of the NMOS tube Ms12, the output end of the amplifier A1 and the The gate of the PMOS tube M26 is connected to the gate of the PMOS tube M22, the drain of the PMOS tube M22 is respectively connected to the non-inverting input terminal of the amplifier A1, the gate of the NMOS tube Ms10 and one end of the resistor R3, the drain of the PMOS tube M23 is respectively connected to the drain of the PMOS tube M24, the inverting input terminal of the amplifier A2, the inverting input terminal of the amplifier A1 and the emitter of the PNP transistor Q1, the gate of the PMOS tube M25 is respectively connected to the gate of the PMOS tube M27, the output terminal of the amplifier A2 and the drain of the NMOS tube Ms11, the drain of the PMOS tube M25 is respectively connected to the non-inverting input terminal of the amplifier A2, the gate of the NMOS tube Ms11 and the drain of the PMOS tube M27. The input end is connected to one end of the resistor R4, the other end of the resistor R4 is connected to the emitter of the PNP transistor Q2, the drain of the PMOS tube M26 is respectively connected to the drain of the PMOS tube M27, one end of the resistor R5 and the circuit output end VREF, the other end of the resistor R5 is respectively connected to the source of the NMOS tube Ms10, the source of the NMOS tube Ms11, the source of the NMOS tube Ms12, the other end of the resistor R3, the base of the PNP transistor Q1, the collector of the PNP transistor Q1, the base of the PNP transistor Q2, the collector of the PNP transistor Q2 and the external ground GND.

[0027] The (μ n ) -1In the bias current generating circuit 1, the PMOS tube M1 is identical to the PMOS tube M2, the NMOS tube M3 is identical to the NMOS tube M4, the channel width-to-length ratio of the NMOS tube M5 is β times that of the NMOS tube M6, and the drain current I1 of the PMOS tube M1 is

[0028]

[0029] In the formula, μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, (W / L)6 is the channel width-to-length ratio of the NMOS tube M6, and R1 is the resistance value of the resistor R1.

[0030] The (μ n ) -3 (V THn ) -2 In the bias current generating circuit 3, the NMOS tube M8, the PMOS tube M7, the PMOS tube M12, the NMOS tube M13 and the NMOS tube M10 form a negative feedback loop, the NMOS tube M8, the PMOS tube M7 and the PMOS tube M9 form a positive feedback loop, the capacitor C1 ensures that the gate of the NMOS tube M8 is the low-frequency main pole in the negative feedback loop, the resistor R2 and the capacitor C2 form a low-pass filter and reduce the positive feedback loop gain, so that the positive feedback loop gain is less than the negative feedback loop gain, ensuring the circuit stability. The PMOS tubes M7, the PMOS tubes M9 and the PMOS tubes M12 have the same channel width-to-length ratio, the NMOS tubes M8 and the NMOS tubes M13 have the same channel width-to-length ratio, so that the NMOS tubes M10 and the NMOS tubes M13 have the same gate, then the drain current I7 of the PMOS tube M7 is

[0031]

[0032] Where, (W / L) 13 is the channel width-to-length ratio of the NMOS tube M13, (W / L) 11 is the channel width-to-length ratio of the NMOS tube M11, (W / L) 10 is the channel width-to-length ratio of the NMOS tube M10, V THn is the threshold voltage of the NMOS tube. The PMOS tubes M15, M17, M19 and M21 are identical and all operate in the subthreshold region. The drain current I D With its gate-source voltage V GS for

[0033]

[0034] Where I0 is a parameter proportional to the channel width-to-length ratio of the MOS tube operating in the subthreshold region, ξ is a non-ideal factor greater than 1, and V t is the thermal voltage. The low frequency gain A of amplifier A3 d >>1, then the gate-source voltage of PMOS tube M15 is V GS15 , the gate-source voltage V of the PMOS tube M17 GS17 , the gate-source voltage V of the PMOS tube M19 GS19 The gate-source voltage V GS21 Yes |V GS15 |+|V GS17 |=|V GS19 |+|V GS21 |; PMOS tube M14 and PMOS tube M7 have the same channel width-to-length ratio, PMOS tube M18, PMOS tube M20 and PMOS tube M1 have the same channel width-to-length ratio, then the drain current I of PMOS tube M16 16 for

[0035]

[0036] In the bandgap reference core circuit 3, all resistors are made of the same material, the channel width-to-length ratio of the PMOS tube M23 is K1 times that of the PMOS tube M1, the channel width-to-length ratio of the PMOS tube M24 is K2 times that of the PMOS tube M16, and the emitter area of ​​the PNP transistor Q2 is N times that of the PNP transistor Q1. Then, the emitter current I of the PNP transistor Q1 is Q1 The emitter current I of the PNP transistor Q2 Q2 for

[0037]

[0038]

[0039] In the formula, R4 is the resistance value of resistor R4. The gain of amplifier A1 is much greater than 1 and the voltage of the in-phase input terminal of the forced amplifier is equal to the voltage of the inverting input terminal, then the drain current I of PMOS tube M22 22 for

[0040]

[0041] Where V EB1 is the emitter-base voltage of the PNP transistor Q1, and R3 is the resistance value of the resistor R3. The channel width-to-length ratio of the PMOS tube M26 is K3 times that of the PMOS tube M22, and the channel width-to-length ratio of the PMOS tube M27 is K4 times that of the PMOS tube M25. Then the output voltage V REF for

[0042]

[0043] In the formula, R5 is the resistance value of R5. In fact, the electron mobility μ n With temperature T n ∝T -1.5 , NMOS threshold voltage V THn With temperature T, V THn =V TH0 -a0(T-T0), where T0 is the reference temperature, V TH0 is the threshold voltage at reference temperature T0, and a0 is the temperature coefficient of the threshold voltage. From equations (5) to (8), we can see that I Q2 Has high-order temperature characteristics, which can effectively compensate for V EB1 The temperature high-order nonlinearity is reduced, thereby obtaining a high-order compensated bandgap reference voltage.

[0044] Figure 3 This is a temperature characteristic simulation curve of a high-order temperature compensation bandgap reference circuit for a low voltage drop linear regulator chip of the present invention, where the horizontal axis is the temperature T and the vertical axis is the output voltage waveform. The simulation results show that in the range of -40 to 125°C, the output voltage V REF The temperature coefficient is 0.71ppm / ℃.

[0045] In the above embodiment of the present application, a high-order temperature compensation bandgap reference circuit for a low voltage drop linear regulator chip includes (μ n ) -1 Bias current generating circuit, (μ n ) -3 (V THn ) -2 Bias current generating circuit and bandgap reference core circuit. The embodiment of the present application uses NMOS tube M8, PMOS tube M7, PMOS tube M12, PMOS tube M13 and NMOS tube M10 to form a negative feedback loop, uses NMOS tube M8, PMOS tube M7 and PMOS tube M9 to form a positive feedback loop, and resistor R2 and capacitor C2 form a low-pass filter and reduce the positive feedback loop gain to ensure circuit stability; (μ n ) -1 Bias current generating circuit and (μ n ) -3 (V THn ) -2 The bias current generation circuit provides bias current for the bandgap reference core circuit and generates a current I with high-order temperature characteristics. Q2 , effectively compensates for V EB1 The temperature high-order nonlinearity is reduced, so as to obtain a high-order compensated bandgap reference voltage, and then realize a high-order temperature compensated bandgap reference circuit.

[0046] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products having certain functions. It should also be noted that the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, commodity or device including the elements.

[0047] The above embodiments should be understood to be only used to illustrate the present invention and not to limit the protection scope of the present invention. After reading the contents of the present invention, technicians can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A high-order temperature-compensated bandgap reference circuit for a low-dropout linear regulator chip, characterized in that: include: (μ n ) -1 Bias current generating circuit (1), (μ n ) -3 (V THn ) -2 Bias current generating circuit (2) and bandgap reference core circuit (3), wherein the (μ n ) -1 The signal output terminals of the bias current generating circuit (1) are respectively connected to the (μ n ) -3 (V THn ) -2 The bias current generating circuit (2) and the signal input end of the bandgap reference core circuit (3), μ n represents electron mobility, V THn Represents the threshold voltage of the NMOS tube, the (μ n ) -3 (V THn ) -2 The signal output end of the bias current generating circuit (2) is connected to the signal input end of the bandgap reference core circuit (3); the (μ n ) -1 Bias current generating circuit (1) and (μ n ) -3 (V THn ) -2 The bias current generating circuit (2) provides a temperature-dependent bias current for the bandgap reference core circuit (3), and the bandgap reference core circuit (3) generates a high-performance bandgap reference voltage at an output terminal VREF; The (μ n ) -1 The bias current generating circuit (1) comprises: a PMOS tube Ms1, a PMOS tube Ms2, an NMOS tube Ms3, an NMOS tube Ms4, a PMOS tube M1, a PMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6 and a resistor R1, wherein the source of the PMOS tube Ms1 is respectively connected to the source of the PMOS tube M1, the source of the PMOS tube M2 and an external power supply VDD, the gate of the PMOS tube Ms1 is respectively connected to the drain of the PMOS tube Ms1 and the source of the PMOS tube Ms2, the gate of the PMOS tube Ms2 is respectively connected to the drain of the PMOS tube Ms2, the gate of the NMOS tube Ms3 and the drain of the NMOS tube Ms4, the drain of the PMOS tube M1 is respectively connected to the gate of the PMOS tube M1, the gate of the PMOS tube M2 and the drain of the NMOS tube Ms4, and the drain of the PMOS tube M1 is respectively connected to the gate of the PMOS tube M1, the gate of the PMOS tube M2 and the drain of the NMOS tube The gate of the PMOS transistor M18 is connected to the gate of the PMOS transistor M18, the gate of the PMOS transistor M20, the gate of the PMOS transistor M23, the drain of the NMOS transistor Ms3, and the drain of the NMOS transistor M3 are connected. The source of the NMOS transistor M3 is connected to the drain of the NMOS transistor M5. The source of the NMOS transistor M5 is connected to one end of the resistor R1. The other end of the resistor R1 is respectively connected to the source of the NMOS transistor Ms4, the source of the NMOS transistor Ms3, the source of the NMOS transistor M6, and the external ground GND. The drain of the PMOS transistor M2 is respectively connected to the gate of the NMOS transistor M3, the gate of the NMOS transistor M4, and the drain of the NMOS transistor M4. The source of the NMOS transistor M4 is respectively connected to the gate of the NMOS transistor Ms4, the gate of the NMOS transistor M5, the gate of the NMOS transistor M6, and the drain of the NMOS transistor M6. The (μ n ) -3 (V THn ) -2 The bias current generating circuit (2) comprises: a PMOS transistor Ms5, a PMOS transistor Ms6, an NMOS transistor Ms7, an NMOS transistor Ms8, a PMOS transistor M7, an NMOS transistor M8, a PMOS transistor M9, an NMOS transistor M10, an NMOS transistor M11, a PMOS transistor M12, an NMOS transistor M13, a PMOS transistor M14, a PMOS transistor M15, a PMOS transistor M16, a PMOS transistor M17, a PMOS transistor M18, a PMOS transistor M19, a PMOS transistor M20, a PMOS transistor M21, an amplifier A3, a resistor R2, a capacitor C1 and a capacitor C2, wherein the source of the PMOS transistor Ms5 is connected to the source of the PMOS transistor M7, the source of the PMOS transistor M9 and the source of the capacitor C2 respectively. The gate of the PMOS tube Ms5 is connected to the drain of the PMOS tube Ms5 and the source of the PMOS tube Ms6 respectively. The gate of the PMOS tube Ms6 is connected to the drain of the PMOS tube Ms6, the gate of the NMOS tube Ms7 and the drain of the NMOS tube Ms8 respectively. The gate of the PMOS tube M7 is connected to the gate of the PMOS tube M12, one end of the resistor R2, the gate of the PMOS tube M14, the drain of the PMOS tube M7, the drain of the NMOS tube Ms7 and the drain of the NMOS tube M8 respectively. The gate of the PMOS tube M9 is connected to the gate of the PMOS tube M12, one end of the resistor R2, the gate of the PMOS tube M14, the drain of the PMOS tube M7, the drain of the NMOS tube Ms7 and the drain of the NMOS tube M8 respectively. The gates of the PMOS transistors M9 and M10 are connected to the other end of the capacitor C2 and the other end of the resistor R2, respectively. The drain of the PMOS transistor M9 is connected to the drain of the NMOS transistor M10, the gate of the NMOS transistor M8, the gate of the NMOS transistor Ms8, and one end of the capacitor C1, respectively. The other end of the capacitor C1 is connected to the source of the NMOS transistor Ms8, the source of the NMOS transistor Ms7, the source of the NMOS transistor M8, the source of the NMOS transistor M11, the source of the NMOS transistor M13, the drain of the PMOS transistor M15, the gate of the PMOS transistor M15, the drain of the PMOS transistor M17, the drain of the PMOS transistor M19, the gate of the PMOS transistor M21, the drain of the PMOS transistor M21, and the external ground GND, respectively. The drain of the NMOS transistor M10 is connected to the gate of the NMOS transistor M10, the gate of the NMOS transistor M8, the gate of the NMOS transistor Ms8, and the external ground GND, respectively. The gate is connected to the gate of the NMOS transistor M13, the drain of the NMOS transistor M13 and the drain of the PMOS transistor M12 respectively; the source of the NMOS transistor M10 is connected to the drain of the NMOS transistor M11 and the gate of the NMOS transistor M11 respectively; the drain of the PMOS transistor M14 is connected to the gate of the PMOS transistor M17 and the source of the PMOS transistor M15 respectively; the gate of the PMOS transistor M16 is connected to the output end of the amplifier A3 and the gate of the PMOS transistor M24 respectively; the drain of the PMOS transistor M16 is connected to the non-inverting input end of the amplifier A3 and the source of the PMOS transistor M17 respectively; the drain of the PMOS transistor M18 is connected to the inverting input end of the amplifier A3 and the source of the PMOS transistor M19 respectively.The drain of the PMOS tube M20 is connected to the gate of the PMOS tube M19 and the source of the PMOS tube M21 respectively; The bandgap reference core circuit (3) comprises: a PMOS transistor Ms8, a PMOS transistor Ms9, an NMOS transistor Ms10, an NMOS transistor Ms11, an NMOS transistor Ms12, a PMOS transistor M22, a PMOS transistor M23, a PMOS transistor M24, a PMOS transistor M25, a PMOS transistor M26, a PMOS transistor M27, an amplifier A1, an amplifier A2, a resistor R3, a resistor R4, a resistor R5, a PNP transistor Q1 and a PNP transistor Q2, wherein the source of the PMOS transistor Ms8 is connected to the source of the PMOS transistor M22, the source of the PMOS transistor M23, the source of the PMOS transistor M24, the source of the PMOS transistor M25, the source of the PMOS transistor M26, the source of the PMOS transistor M27 ... The source of the PMOS tube M24, the source of the PMOS tube M25, the source of the PMOS tube M26, the source of the PMOS tube M27 and the external power supply VDD are connected. The gate of the PMOS tube Ms8 is respectively connected to the drain of the PMOS tube Ms8 and the source of the PMOS tube Ms9. The gate of the PMOS tube Ms9 is respectively connected to the drain of the PMOS tube Ms9, the drain of the NMOS tube Ms10, the gate of the NMOS tube Ms11 and the gate of the NMOS tube Ms12. The gate of the PMOS tube M22 is respectively connected to the drain of the NMOS tube Ms12, the output end of the amplifier A1 and the gate of the NMOS tube Ms11. The drain of the PMOS tube M22 is respectively connected to the non-inverting input terminal of the amplifier A1, the gate of the NMOS tube Ms10 and one end of the resistor R3. The drain of the PMOS tube M23 is respectively connected to the drain of the PMOS tube M24, the inverting input terminal of the amplifier A2, the inverting input terminal of the amplifier A1 and the emitter of the PNP transistor Q1. The gate of the PMOS tube M25 is respectively connected to the gate of the PMOS tube M27, the output terminal of the amplifier A2 and the drain of the NMOS tube Ms11. The drain of the PMOS tube M25 is respectively connected to the non-inverting input terminal of the amplifier A2. The input terminal is connected to one end of the resistor R4, the other end of the resistor R4 is connected to the emitter of the PNP transistor Q2, the drain of the PMOS transistor M26 is respectively connected to the drain of the PMOS transistor M27, one end of the resistor R5, and the circuit output terminal VREF, and the other end of the resistor R5 is respectively connected to the source of the NMOS transistor Ms10, the source of the NMOS transistor Ms11, the source of the NMOS transistor Ms12, the other end of the resistor R3, the base of the PNP transistor Q1, the collector of the PNP transistor Q1, the base of the PNP transistor Q2, the collector of the PNP transistor Q2, and the external ground GND; The (μ n ) -1 In the bias current generating circuit (1), the PMOS tube M1 is identical to the PMOS tube M2, the NMOS tube M3 is identical to the NMOS tube M4, the channel width-to-length ratio of the NMOS tube M5 is β times that of the NMOS tube M6, and the drain current I1 of the PMOS tube M1 is Among them, μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, (W / L)6 is the channel width-to-length ratio of the NMOS transistor M6, and R1 is the resistance value of the resistor R1; The (μ n ) -3 (V THn ) -2 In the bias current generating circuit (2), the NMOS transistor M8, the PMOS transistor M7, the PMOS transistor M12, the NMOS transistor M13 and the NMOS transistor M10 form a negative feedback loop, the NMOS transistor M8, the PMOS transistor M7 and the PMOS transistor M9 form a positive feedback loop, the capacitor C1 ensures that the gate of the NMOS transistor M8 is the low-frequency main pole in the negative feedback loop, the resistor R2 and the capacitor C2 form a low-pass filter and reduce the positive feedback loop gain, so that the positive feedback loop gain is less than the negative feedback loop gain, ensuring circuit stability; the PMOS transistors M7, the PMOS transistors M9 and the PMOS transistor M12 have the same channel width-to-length ratio, the NMOS transistors M8 and the NMOS transistor M13 have the same channel width-to-length ratio, so that the NMOS transistors M10 and the NMOS transistors M13 have the same gate, then the drain current I7 of the PMOS transistor M7 = Among them, μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, V THn is the threshold voltage of the NMOS tube, (W / L) 13 is the channel width-to-length ratio of the NMOS transistor M13, (W / L) 11 is the channel width-to-length ratio of the NMOS transistor M11, (W / L) 10 is the channel width-to-length ratio of the NMOS tube M10; the PMOS tubes M15, M17, M19 and M21 are identical and all operate in the subthreshold region. The low-frequency gain A of the amplifier A3 is d >>1. PMOS tubes M14 and M7 have the same channel width-to-length ratio. PMOS tubes M18, M20 and M1 have the same channel width-to-length ratio. Then the drain current I of PMOS tube M16 is 16 =(I1) 2 / I7, where I1 is the drain current of PMOS tube M1; In the bandgap reference core circuit (3), all resistors are made of the same material, the channel width-to-length ratio of the PMOS tube M23 is K1 times that of the PMOS tube M1, the channel width-to-length ratio of the PMOS tube M24 is K2 times that of the PMOS tube M16, and the emitter area of ​​the PNP transistor Q2 is N times that of the PNP transistor Q1. Then, the emitter current I of the PNP transistor Q1 is Q1 =K1I1+K2I 16 , the emitter current of PNP transistor Q2 Among them, I1 is the drain current of PMOS tube M1, I 16 is the drain current of PMOS tube M16, V t is the thermal voltage, R4 is the resistance value of resistor R4; In the bandgap reference core circuit (3), the gain of the amplifier A1 is much greater than 1 and the voltage of the non-inverting input terminal of the forced amplifier is equal to the voltage of the inverting input terminal. The channel width-to-length ratio of the PMOS tube M26 is K3 times that of the PMOS tube M22, and the channel width-to-length ratio of the PMOS tube M27 is K4 times that of the PMOS tube M25. Then, the output voltage V REF V REF =(K3V EB1 / R3+K4I Q2 )R5, where V EB1 is the emitter-base voltage of the PNP transistor Q1, R3 is the resistance value of the resistor R3, R5 is the resistance value of the resistor R5, I Q2 is the emitter current of PNP transistor Q2, and the electron mobility μ n With temperature T μ n ∝T -1.5 , NMOS tube threshold voltage V THn V with temperature T THn =V TH0 -a0(T-T0), where T0 is the reference temperature, V TH0 is the reference temperature T 0处 The threshold voltage, a0 is the temperature coefficient of the threshold voltage, so I Q2 It has high-order temperature characteristics and can effectively compensate for V EB1 The temperature high-order nonlinearity is reduced, thereby obtaining a high-order compensated bandgap reference voltage.

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