Communication data processing method, device, equipment and storage medium based on PCIE
By prefetching read requested data and write requested data into the cache in PCIE devices, the problems of increased latency and low transmission efficiency caused by direct access to memory are solved, and more efficient data transmission is achieved.
Patent Information
- Application Number
- CN202310057520.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-01-17
- Publication Date
- 2025-01-03
- Estimated Expiration
- 2043-01-17
AI Technical Summary
In a data center multi-core server system, when PCIE devices communicate with the CPU in data, the delay caused by direct access to memory increases and data transmission efficiency is low.
When receiving a PCIE request, the subsequent read request is predicted and the data is prefetched into the cache, or the write data is written into the matching cache based on the preset tag information, reducing the number of accesses to the memory.
By prefetching and writing data to the cache, the number of memory access is reduced and the transmission efficiency of communication data is improved.
Smart Images
Figure CN116055429B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of data communication technology, and in particular to a communication data processing method, device, equipment and storage medium based on PCIE. Background Art
[0002] At present, with the continuous enhancement of computer processing power and the continuous improvement of application requirements, the amount of data calculation processed by applications is increasing, and the amount of data read and written (Input / Output, I / O) from the file system is also increasing.
[0003] In a multi-core server system in a data center, when a PCIE device performs communication data processing such as reading and writing with the CPU, it is usually implemented by direct memory access. However, when performing data communication, whether to access the memory and the number of accesses are different behaviors taken by the system bus according to the different cache line states, which makes the delay of communication data processing unstable and cannot achieve high data transmission efficiency.
[0004] The above contents are only used to assist in understanding the technical solution of the present invention, and do not constitute an admission that the above contents are related technologies. Summary of the invention
[0005] The main purpose of the present invention is to provide a communication data processing method, device, equipment and storage medium based on PCIE, aiming to solve the technical problems of increased delay and low data transmission efficiency caused by direct access to memory when performing communication data processing.
[0006] To achieve the above object, the present invention provides a communication data processing method based on PCIE, the method comprising the following steps:
[0007] When receiving a request based on the PCIE, obtaining a request type of the request, where the request type includes a read request or a write request;
[0008] When the request type is the read request, predicting a subsequent read request based on the request, and pre-fetching data corresponding to the subsequent read request into a first preset cache;
[0009] When the request type is the write request, the data corresponding to the request is written into a second preset cache according to preset tag information, and the second preset cache matches the preset tag information.
[0010] Optionally, when the request type is the read request, predicting a subsequent read request based on the request, and pre-fetching data corresponding to the subsequent read request into a first preset cache includes:
[0011] When the request type is the read request, predicting the to-be-read data corresponding to the subsequent read request based on the request, and acquiring the target address of the to-be-read data;
[0012] A pre-fetch address is generated according to the target address, and the to-be-read data obtained based on the pre-fetch address is placed into a first preset cache.
[0013] Optionally, when the request type is the read request, after the step of predicting the to-be-read data corresponding to the subsequent read request based on the request and acquiring the target address of the to-be-read data, the method further comprises:
[0014] When the target address is a non-cacheable type address, stop acquiring the target address of the data to be read.
[0015] Optionally, generating a prefetch address according to the target address, and placing the to-be-read data obtained based on the prefetch address into a first preset cache includes:
[0016] Acquire the target data address, and generate a pre-fetch address according to the target data address according to a preset step size;
[0017] The to-be-read data is placed into a first preset cache based on the pre-fetch address.
[0018] Optionally, before the step of placing the to-be-read data into a first preset cache based on the pre-fetch address, the step includes:
[0019] Determine the request length and request quantity of the pre-fetch address according to the Burst information of the data to be read;
[0020] When the request length of the pre-fetch address exceeds a preset length or the request quantity exceeds a preset quantity, the pre-fetch address of the preset length is deleted or the pre-fetch address of the preset quantity is discarded.
[0021] Optionally, when the request type is the write request, writing the data corresponding to the request into a second preset cache according to preset tag information includes:
[0022] When the request type is the write request, determining whether the to-be-written data corresponding to the request is cacheable data;
[0023] When the data to be written is data of a cacheable type, writing the data to be written into a second preset cache according to preset tag information;
[0024] The preset tag information is used to mark the second preset cache into which the data is written.
[0025] Optionally, when the data to be written is data of a cacheable type, writing the data to be written into a second preset cache according to preset tag information includes:
[0026] When the data to be written is cacheable data, updating the target address of the data to be written according to preset tag information to obtain a pre-written address;
[0027] The data to be written is written into a second preset cache according to the pre-write address.
[0028] In addition, to achieve the above object, the present invention also proposes a communication data processing device based on PCIE, the device comprising:
[0029] A request receiving module, configured to obtain a request type of the request upon receiving a request from the PCIE, wherein the request type includes a read request or a write request;
[0030] A data pre-fetching module, configured to, when the request type is the read request, predict a subsequent read request based on the request, and pre-fetch data corresponding to the subsequent read request into a first preset cache;
[0031] A data pre-writing module is used to write the data corresponding to the request into a second preset cache according to preset tag information when the request type is the write request, and the second preset cache matches the preset tag information.
[0032] In addition, to achieve the above-mentioned purpose, the present invention also proposes a PCIE-based communication data processing device, the device comprising: a memory, a processor, and a PCIE-based communication data processing program stored in the memory and executable on the processor, the PCIE-based communication data processing program being configured to implement the steps of the PCIE-based communication data processing method as described above.
[0033] In addition, to achieve the above-mentioned purpose, the present invention also proposes a storage medium, on which a PCIE-based communication data processing program is stored. When the PCIE-based communication data processing program is executed by a processor, the steps of the PCIE-based communication data processing method described above are implemented.
[0034] The present invention obtains the request type of the request when receiving a request based on PCIE, and the request type includes a read request or a write request; when the request type is the read request, a subsequent read request is predicted based on the request, and the data corresponding to the subsequent read request is pre-fetched into a first preset cache; when the request type is the write request, the data corresponding to the request is written into a second preset cache according to preset tag information, and the second preset cache matches the preset tag information. Since the present invention pre-fetches the data to be fetched into the cache, and directly writes the data to be written into the cache, the data can be directly obtained from the preset cache when transmitting communication data, thereby reducing the number of times the memory is accessed and improving the transmission efficiency of the communication data. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 It is a structural diagram of a communication data processing device based on PCIE in a hardware operating environment involved in an embodiment of the present invention;
[0036] Figure 2 It is a flow chart of a first embodiment of a communication data processing method based on PCIE of the present invention;
[0037] Figure 3 It is a flow chart of a second embodiment of a communication data processing method based on PCIE of the present invention;
[0038] Figure 4 It is a flow chart of a third embodiment of a communication data processing method based on PCIE of the present invention;
[0039] Figure 5 It is a structural block diagram of the first embodiment of the communication data processing device based on PCIE of the present invention.
[0040] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0041] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.
[0042] Reference Figure 1 , Figure 1 The present invention is a schematic diagram of the structure of a communication data processing device based on PCIE in the hardware operating environment involved in the embodiment of the present invention.
[0043] like Figure 1As shown, the PCIE-based communication data processing device may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a wireless fidelity (Wireless-Fidelity, Wi-Fi) interface). The memory 1005 may be a high-speed random access memory (Random Access Memory, RAM), or a stable non-volatile memory (Non-Volatile Memory, NVM), such as a disk memory. The memory 1005 may also be a storage device independent of the aforementioned processor 1001.
[0044] Those skilled in the art will understand that Figure 1 The structure shown in the figure does not constitute a limitation on the communication data processing device based on PCIE, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.
[0045] like Figure 1 As shown, the memory 1005 as a storage medium may include an operating system, a network communication module, a user interface module, and a communication data processing program based on PCIE.
[0046] exist Figure 1 In the PCIE-based communication data processing device shown, the network interface 1004 is mainly used for data communication with a network server; the user interface 1003 is mainly used for data interaction with a user; the processor 1001 and the memory 1005 in the PCIE-based communication data processing device of the present invention can be set in the PCIE-based communication data processing device, and the PCIE-based communication data processing device calls the PCIE-based communication data processing program stored in the memory 1005 through the processor 1001, and executes the PCIE-based communication data processing method provided in an embodiment of the present invention.
[0047] The embodiment of the present invention provides a communication data processing method based on PCIE, referring to Figure 2 , Figure 2 It is a flowchart of the first embodiment of the communication data processing method based on PCIE of the present invention.
[0048] In this embodiment, the communication data processing method based on PCIE includes the following steps:
[0049] Step S10: when receiving a PCIE-based request, obtaining a request type of the request, where the request type includes a read request or a write request.
[0050] It should be noted that the execution subject of the method of this embodiment can be a computing service device that can realize data processing, network communication and program running functions of asynchronous I / O technology based on the PCIE interface, such as Host (host server), PC (Personal Computer), tablet computer, portable computer, etc., and can also be other electronic devices that can realize the same or similar functions for transmitting port information based on the PCIE port installed on the device, and this embodiment does not limit this. Here, the communication data processing host server (hereinafter referred to as the data processing host) that realizes asynchronous I / O technology will be taken as an example to illustrate the various embodiments of the communication data processing method based on PCIE of the present invention.
[0051] It is understandable that PCIE (Peripheral Component Interconnect-Express) is a high-speed serial computer expansion bus standard and is the third-generation I / O technology that replaces the PCI / PCI-X bus. The standard of this bus is formulated by the AWG (Arapahoe Working Group) supported by Intel. The PCIE bus uses a serial bus for point-to-point transmission and supports bidirectional transmission mode and data channel transmission mode.
[0052] It should be understood that asynchronous I / O technology uses I / O-specific processes / threads other than computing processes / threads to complete data I / O operations, so that the device can continue to perform other calculations without waiting for the completion of the I / O operation, thereby overlapping the device's calculation and I / O processing. In asynchronous I / O technology, two major steps are usually required to implement the data I / O process, where the first step is to initiate an asynchronous I / O request, and the second step is to confirm that the asynchronous I / O request has been completed (called the wait instruction of the asynchronous I / O request).
[0053] It should be noted that the communication request received by the data processing host may include a read request for the memory and a write request for the memory, and the memory of the host may contain data required to execute the request. According to different request categories, the data processing host may execute corresponding operations of reading the memory data and writing the data into the memory.
[0054] It can be understood that the above communication request is sent by the PCIE device based on the PCIE interface installed on the data processing host. The PCIE device is a peripheral device (hereinafter referred to as the peripheral device) connected to the data processing host through the PCIE interface.
[0055] In a specific implementation, when a data processing host receives a communication request sent by a peripheral device based on a PCIE interface, it obtains the communication request type based on an asynchronous I / O request. The communication request type includes a data read request and a data write request. The data processing host can perform corresponding read or write operations on memory data according to different communication request types.
[0056] Step S20: when the request type is the read request, predict a subsequent read request based on the request, and pre-fetch data corresponding to the subsequent read request into a first preset cache.
[0057] It is understandable that when data is transmitted, the sending and receiving requests are usually not transmitted in isolation, and there is a certain logical relationship between multiple requests. Therefore, when the data processing host receives and starts to execute a single current request, the request of the next peripheral device can be predicted based on the target request data content and target address corresponding to the current request, and the target data content corresponding to the next request can be pre-fetched according to the target address corresponding to the next request.
[0058] It should be noted that prefetching is a technology that can be used by the data processing host to accelerate the data transmission process. The main principle is to pre-read the next operation request data and address based on the current request when executing the current operation request, and obtain the pre-read content to avoid multiple repeated operations that waste a lot of time.
[0059] It should be understood that the first preset cache can be one or more target cache locations for pre-fetched data preset in advance by the user before executing communication data transmission, such as: LLC (system shared cache), MemoryControllerBuffer (memory controller cache), internal caches of different processors, etc., which can be set according to the actual storage capacity of different data processing hosts or user preferences, and this embodiment does not limit this.
[0060] In a specific implementation, when a data processing host receives a read request sent by a peripheral device based on a PCIE interface, it monitors the target address of the request and subsequent read requests, and pre-fetches the to-be-read data corresponding to the above request stored at the target address into one or more pre-set target cache locations according to the monitored target address.
[0061] Step S30: when the request type is the write request, writing the data corresponding to the request into a second preset cache according to preset tag information, and the second preset cache matches the preset tag information.
[0062] It should be noted that the target address of the write request may be classified as preset tag information by configuring Hint, and the storage location to be written of the write request may be determined according to the Hint information.
[0063] It should be understood that a configuration information table with a mapping relationship can be preset, in which the key fields used to configure the Hint statement have a one-to-one mapping relationship with different preset cache locations. The mapping relationship can be preset by the user according to the actual storage capacity and internal storage space distribution of the current data processing host before executing the read request. This embodiment does not limit this.
[0064] It can be understood that the second preset cache can be one or more target cache locations for pre-fetched data preset in advance by the user before executing communication data transmission, such as: CPU internal cache, LLC (system shared cache), MemoryController Buffer (memory controller cache), and cache (Cache) close to the CPU or even the BUFFER of the PCIE root node. It can be set according to the actual storage capacity of different data processing devices or user preferences, and this embodiment does not limit this.
[0065] In a specific implementation, when a data processing host receives a write request sent by a peripheral device based on a PCIE interface, it obtains the write target address corresponding to the write data request according to the key field of the configuration Hint statement, and directly writes the data to be written corresponding to the write request into the write target address so that data can be directly obtained from the target address during subsequent data processing.
[0066] In this embodiment, upon receiving a communication request sent by a peripheral device based on a PCIE interface, the request type of the request is obtained, and the request type includes a read request or a write request; when the request type is the read request, a subsequent read request is predicted based on the request, and the data corresponding to the subsequent read request is pre-fetched into a first preset cache; when the request type is the write request, the data corresponding to the request is written into a second preset cache according to preset tag information, and the second preset cache matches the preset tag information. Since the present embodiment pre-fetches the data to be fetched into the cache, and directly writes the data to be written into the cache, the data can be directly obtained from the preset cache when transmitting the communication data, thereby reducing the number of times the memory is accessed and improving the transmission efficiency of the communication data.
[0067] Reference Figure 3, Figure 3 It is a flow chart of the second embodiment of the communication data processing method based on PCIE of the present invention.
[0068] Based on the above first embodiment, in this embodiment, step S20 includes:
[0069] Step S21: when the request type is the read request, predicting the to-be-read data corresponding to the subsequent read request based on the request, and acquiring the target address of the to-be-read data.
[0070] In a specific implementation, when receiving a read request sent by a peripheral device based on a PCIE interface, the data processing host monitors the target address, target address type, and Burst information of the request and subsequent read requests.
[0071] Furthermore, after step S21, the following steps are further included:
[0072] Step S21 ′: when the target address is a non-cacheable type address, stop acquiring the target address of the data to be read.
[0073] It should be noted that the target address corresponding to the data to be read can be a cacheable address or a non-cacheable address. When the address corresponding to the data to be read is a cacheable address, the data to be read can be stored in the cache for direct reading; when the target address corresponding to the data to be read is a non-cacheable address, the data to be read cannot be stored in the cache for reading.
[0074] Step S22: generating a pre-fetch address according to the target address, and placing the to-be-read data obtained based on the pre-fetch address into a first preset cache.
[0075] Further, step S22 may include:
[0076] Step S221: Acquire the target data address, and generate a pre-fetch address according to the target data address in accordance with a preset step size.
[0077] It should be noted that, when obtaining the target address to be read, the pre-fetch address may be generated in combination with the stride of the preset configuration and the Burst information of the data to be read.
[0078] It is understandable that the Burst information required to obtain the data to be read may be generated according to the Burst type and length of the read request, and the Burst information may include the Burst length of the data to be read.
[0079] In a specific implementation, the target address can be aligned according to the Cache Line size (usually 64 bytes), and then added with the configured stride (0 < stride < 64), the request Burst length, and the target address to obtain the prefetch address.
[0080] Further, when the read request Burst length is in [0, 16], the Burst length required to obtain the data to be read can be set to 1, and when the read request Burst length is greater than 16, the Burst length required to obtain the data to be read can be all current Cache Lines.
[0081] Further, the request length and the number of requests for the prefetch address can be determined according to the above-mentioned Burst information required for the data to be read. When the request length of the prefetch address exceeds the preset length or the number of requests exceeds the preset number, the prefetch addresses of the preset length are deleted or the preset number of prefetch addresses are discarded.
[0082] Step S222: Put the data to be read into a first preset cache based on the prefetch address.
[0083] It should be noted that the data to be read can be put into the first preset cache according to the bus protocol. The bus protocol can be, for example: AMBA protocol, ACE protocol, and CHI protocol, etc. This embodiment does not limit this, and the ACE5-Lite bus protocol is selected to illustrate this embodiment here.
[0084] In a specific implementation, when obtaining the prefetch address and the Burst information required for the data to be read, the data to be read can be put into the first preset cache based on the ACE5-Lite bus protocol on the ARM platform.
[0085] In this embodiment, when the request type is a read request, based on the current request, the to-be-read data corresponding to the subsequent read request is predicted and the target address of the to-be-read data is obtained. When the target address type of the to-be-read data is a non-cacheable type address, the acquisition of the target address of the to-be-read data is stopped, the target data address is obtained, and a pre-fetch address is obtained in combination with a preset step length and Burst information. The request length and the request quantity of the pre-fetch address are determined according to the Burst information of the to-be-read data. When the request length of the pre-fetch address exceeds the preset length or the request quantity exceeds the preset quantity, the pre-fetch address of the preset length is deleted or the pre-fetch address of the preset quantity is discarded. Then, according to the bus standard, the to-be-read data is pre-fetched into a preset first preset cache based on the pre-fetch address so that the to-be-read data can be directly obtained from the cache during subsequent data communication, thereby reducing the number of accesses to the memory and realizing the dynamic length setting of the to-be-read data based on the pre-fetch address, ensuring the optimal pre-fetch for each transmission, reducing the waste rate of bus resources, and reducing the delay when reading data, thereby improving the information transmission rate.
[0086] Reference Figure 4 , Figure 4 It is a flow chart of the third embodiment of the communication data processing method based on PCIE of the present invention.
[0087] Based on the above embodiment, in this embodiment, step S30 includes:
[0088] Step S31: when the request type is the write request, determine whether the to-be-written data corresponding to the request is cacheable data.
[0089] In a specific implementation, when a write request based on a PCIE interface is received from a peripheral device, when Hint configuration is enabled, the target address of the data to be written sent by the peripheral device is monitored to determine whether the type of the target address is a cacheable type.
[0090] Furthermore, when it is determined that the target address of the data to be written is of a non-cacheable type, the write request is directly transparently transmitted to the target address so that the data to be written is directly written into the non-cacheable target address.
[0091] Step S32: when the data to be written is of a cacheable type, write the data to be written into a second preset cache according to preset tag information.
[0092] It can be understood that the preset tag information is used to mark and distinguish the second preset cache where the data to be written is written.
[0093] It should be noted that the Hint information can be converted into bus command-based parameters to generate a configuration information table. By querying the configuration information table, the preset tag information of the current write request can be obtained, thereby obtaining the second preset cache corresponding to the data to be written.
[0094] It can be understood that the initial target address of the data to be written is the memory, and the target address of the data to be written can be updated to obtain an updated target address, namely a pre-write address. The pre-write address is the address of the second preset cache. The location of the second preset cache can be determined based on the size of the data to be written and the location of the internal controller of the data processing host that subsequently reads and processes the data, and can be pre-set and stored in the configuration information table. This embodiment does not impose any restrictions on this.
[0095] In a specific implementation, when the target address of the data to be written is of a cacheable type, the target address of the data to be written is updated by querying the preset tag information obtained from the configuration information table to obtain a pre-write address, and the data to be written is written into the second preset cache corresponding to the address according to the pre-write address.
[0096] This embodiment, when receiving a write request sent by a peripheral device based on a PCIE interface, monitors the target address of the data to be written sent by the peripheral device connected to the data processing host through the PCIE interface, determines whether the type of the target address is a cacheable type, and when the target address is a non-cacheable type, directly transparently transmits the write request to the target address so that the data to be written is directly written to the non-cacheable target address, and when the target address is a cacheable type, updates the target address of the data to be written according to the preset tag information obtained by querying the configuration information table, obtains a pre-write address, and writes the data to be written into the second preset cache corresponding to the address according to the pre-write address. Thus, the problem of data being directly written into the memory of the data processing device by the request device with PCIE, and then the data processing host reading the data from the memory when processing the data is solved, and at the same time, the bandwidth occupation of the memory is reduced, so that data can be directly obtained from the preset cache when transmitting communication data, thereby reducing the number of memory accesses and further improving the transmission efficiency of communication data.
[0097] In addition, an embodiment of the present invention further proposes a storage medium, on which a PCIE-based communication data processing program is stored. When the PCIE-based communication data processing program is executed by a processor, the steps of the PCIE-based communication data processing method described above are implemented.
[0098] Reference Figure 5 , Figure 5 It is a structural block diagram of the first embodiment of the communication data processing device based on PCIE of the present invention.
[0099] like Figure 5 As shown, the PCIE-based communication data processing device proposed in an embodiment of the present invention includes:
[0100] The request receiving module 501 is used to obtain the request type of the request when receiving a request based on PCIE, and the request type includes a read request or a write request;
[0101] A data pre-fetching module 502, configured to, when the request type is the read request, predict a subsequent read request based on the request, and pre-fetch data corresponding to the subsequent read request into a first preset cache;
[0102] The data pre-writing module 503 is used to write the data corresponding to the request into a second preset cache according to preset tag information when the request type is the write request, and the second preset cache matches the preset tag information.
[0103] This embodiment obtains the request type of the request when receiving a request based on PCIE, and the request type includes a read request or a write request; when the request type is the read request, a subsequent read request is predicted based on the request, and the data corresponding to the subsequent read request is pre-fetched into a first preset cache; when the request type is the write request, the data corresponding to the request is written into a second preset cache according to preset tag information, and the second preset cache matches the preset tag information. Since this embodiment pre-fetches the data to be fetched into the cache, and directly writes the data to be written into the cache, the data can be directly obtained from the preset cache when transmitting communication data, thereby reducing the number of times the memory is accessed and improving the transmission efficiency of the communication data.
[0104] Other embodiments or specific implementations of the PCIE-based communication data processing device of the present invention may refer to the above-mentioned method embodiments and will not be described in detail here.
[0105] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.
[0106] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.
[0107] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory / random access memory, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present invention.
[0108] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A communication data processing method based on PCIE, characterized in that: The method comprises: When receiving a request based on the PCIE, obtaining a request type of the request, where the request type includes a read request or a write request; When the request type is the read request, predicting a subsequent read request based on the request, and pre-fetching data corresponding to the subsequent read request into a first preset cache, where the first preset cache is at least one of a system shared cache, a memory controller cache, and a processor internal cache; When the request type is the write request, writing the data corresponding to the write request into a second preset cache according to preset tag information, the second preset cache matching the preset tag information; Wherein, when the request type is the read request, predicting a subsequent read request based on the request, and pre-fetching data corresponding to the subsequent read request into a first preset cache includes: When the request type is the read request, predicting the to-be-read data corresponding to the subsequent read request based on the request, and acquiring the target address of the to-be-read data; Generate a pre-fetch address according to the target address, and put the to-be-read data obtained based on the pre-fetch address into a first preset cache; Wherein, when the request type is the write request, writing the data corresponding to the write request into the second preset cache according to the preset tag information includes: When the request type is the write request, determining whether the to-be-written data corresponding to the request is cacheable data; When the data to be written is data of a cacheable type, writing the data to be written into a second preset cache according to preset tag information; The preset tag information is used to mark the second preset cache into which the data is written, and the preset tag information is a configuration Hint statement.
2. The PCIE-based communication data processing method according to claim 1, characterized in that: After the step of predicting the to-be-read data corresponding to the subsequent read request based on the request when the request type is the read request, and acquiring the target address of the to-be-read data, the method further comprises: When the target address is a non-cacheable type address, stop acquiring the target address of the data to be read.
3. The PCIE-based communication data processing method according to claim 2, characterized in that: The generating a prefetch address according to the target address, and placing the to-be-read data obtained based on the prefetch address into a first preset cache, comprises: Generate a pre-fetch address according to the target address in a preset step size; The to-be-read data is placed into a first preset cache based on the pre-fetch address.
4. The PCIE-based communication data processing method according to claim 3, characterized in that: Before the step of placing the to-be-read data into a first preset cache based on the pre-fetch address, the method includes: Determine the request length and request quantity of the pre-fetch address according to the Burst information of the data to be read; When the request length of the pre-fetch address exceeds a preset length or the request quantity exceeds a preset quantity, the pre-fetch address of the preset length is deleted or the pre-fetch address of the preset quantity is discarded.
5. The PCIE-based communication data processing method according to claim 1, characterized in that: When the data to be written is data of a cacheable type, writing the data to be written into a second preset cache according to preset tag information includes: When the data to be written is cacheable data, updating the target address of the data to be written according to preset tag information to obtain a pre-written address; The data to be written is written into a second preset cache according to the pre-write address.
6. A communication data processing device based on PCIE, characterized in that: The device comprises: A request receiving module, configured to obtain a request type of the request when receiving a request based on the PCIE, wherein the request type includes a read request or a write request; a data prefetch module, configured to, when the request type is the read request, predict a subsequent read request based on the request, and prefetch data corresponding to the subsequent read request into a first preset cache, wherein the first preset cache is at least one of a system shared cache, a memory controller cache, and a processor internal cache; a data pre-writing module, configured to, when the request type is the write request, write the data corresponding to the write request into a second preset cache according to preset tag information, wherein the second preset cache matches the preset tag information; The data prefetch module is further configured to, when the request type is the read request, predict the to-be-read data corresponding to the subsequent read request based on the request, and obtain the target address of the to-be-read data; generate a prefetch address according to the target address, and put the to-be-read data obtained based on the prefetch address into a first preset cache; The data pre-write module is also used to determine whether the data to be written corresponding to the request is cacheable data when the request type is the write request; when the data to be written is cacheable data, write the data to be written into a second preset cache according to preset tag information; wherein the preset tag information is used to mark the second preset cache where the data is written, and the preset tag information is a configuration Hint statement.
7. A communication data processing device based on PCIE, characterized in that: The device includes: a memory, a processor, and a PCIE-based communication data processing program stored in the memory and executable on the processor, wherein the PCIE-based communication data processing program is configured to implement the steps of the PCIE-based communication data processing method as described in any one of claims 1 to 5.
8. A storage medium, characterized in that: The storage medium stores a PCIE-based communication data processing program, and when the PCIE-based communication data processing program is executed by the processor, the steps of the PCIE-based communication data processing method as described in any one of claims 1 to 5 are implemented.