Power factor correction converter, controller and digital peak hold circuit therefor

CN116094307BActive Publication Date: 2026-02-27RICHTEK TECH
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Patent Information

Application Number
CN202210695955.8
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2021-11-08
Filing Date
2022-06-20
Publication Date
2026-02-27
Estimated Expiration
2042-06-20

AI Technical Summary

Technical Problem

Existing power factor correction converters suffer from problems such as large circuit size, high cost, and high overall power consumption during operation. This is mainly due to the large voltage difference between the rectified voltage and the output voltage, which necessitates the use of large-size energy storage components and switches to prevent circuit burnout.

Method used

A digital peak hold circuit is adopted, which consists of a delay circuit, a digital rise sensor, a tracking register, a digital fall sensor, and a hold register. The digital peak hold circuit dynamically adjusts the output voltage to follow the peak change of the rectified voltage, reduces the voltage difference between the rectified voltage and the output voltage, and optimizes the operation of the power factor correction controller by combining an analog-to-digital converter, an error amplifier, and a pulse width modulation circuit.

Benefits of technology

It effectively reduces the circuit size and overall power consumption of the power factor correction converter, reduces the need for large-size energy storage components and switches, and lowers costs and power losses.

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Abstract

A power factor correction converter, a controller and a digital peak hold circuit thereof. The power factor correction converter includes a rectifier, a power factor correction controller, a power stage circuit and a feedback circuit, wherein the power factor correction converter is used to convert an AC voltage to an output voltage. The power factor correction controller includes an analog-to-digital converter, a digital peak hold circuit, a reference voltage generator, an error amplifier and a pulse width modulation circuit, wherein the power factor correction controller is used to generate a drive signal according to a rectified signal and a feedback signal. The digital peak hold circuit includes a delay circuit, a digital up-sense, a tracking register, a digital down-sense and a hold register, wherein the digital peak hold circuit is used to generate a peak signal according to a digital input signal.
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Citation Information

Patent Citations

  • Power factor correction control circuit for reducing EMI (electro magnetic interference)

    CN102332814A

  • Peak detection circuit, input feed-forward compensating circuit and power factor correction circuit

    CN103117734A