Power factor correction converter, controller and digital peak hold circuit therefor
Patent Information
- Application Number
- CN202210695955.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2021-11-08
- Filing Date
- 2022-06-20
- Publication Date
- 2026-02-27
- Estimated Expiration
- 2042-06-20
AI Technical Summary
Existing power factor correction converters suffer from problems such as large circuit size, high cost, and high overall power consumption during operation. This is mainly due to the large voltage difference between the rectified voltage and the output voltage, which necessitates the use of large-size energy storage components and switches to prevent circuit burnout.
A digital peak hold circuit is adopted, which consists of a delay circuit, a digital rise sensor, a tracking register, a digital fall sensor, and a hold register. The digital peak hold circuit dynamically adjusts the output voltage to follow the peak change of the rectified voltage, reduces the voltage difference between the rectified voltage and the output voltage, and optimizes the operation of the power factor correction controller by combining an analog-to-digital converter, an error amplifier, and a pulse width modulation circuit.
It effectively reduces the circuit size and overall power consumption of the power factor correction converter, reduces the need for large-size energy storage components and switches, and lowers costs and power losses.
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Figure CN116094307B_ABST
Abstract
Citation Information
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