Adjustment Method, Device, Equipment and Medium for Composite Video Signal CVBS

Abstract

The present application provides a method, device, equipment and medium for adjusting a composite video signal CVBS. The method performs digital-to-analog conversion on a video stream through a digital-to-analog conversion circuit to obtain the composite video signal CVBS. Furthermore, a proportional parameter of the signal level is determined according to the signal frequency and the amplitude of the signal level, and whether to adjust the digital-to-analog conversion circuit is determined according to the comparison result between the proportional parameter and a threshold value. During the adjustment, the register parameters of the digital-to-analog conversion circuit are adjusted iteratively for multiple rounds based on the proportional parameter. In each round of iteration, the proportional parameter is re-determined according to the digital-to-analog conversion circuit after the previous round of adjustment, and whether the adjustment is completed is determined according to the comparison result between the re-determined proportional parameter and the threshold value. The above process can adaptively adjust the register parameters of the digital-to-analog conversion circuit according to the comparison result between the proportional parameter and the threshold value, without manual debugging, improving the debugging efficiency and accuracy.

Description

Technical Field

[0001] The present application relates to the technical field of signal processing, and particularly relates to a method, device, equipment and medium for adjusting a composite video signal CVBS. Background Art

[0002] Most camera devices convert the collected video stream into a composite video broadcast signal (CVBS) through a digital-to-analog converter (DAC) to avoid the problem of mixed interference of audio and video signals. During the digital-to-analog conversion process, due to changes in the signal transmission path and the usage environment, the signal level of the CVBS may not reach the level standard value specified by the protocol, which may cause image quality problems such as overexposure and underexposure.

[0003] There is a register in the digital-to-analog conversion circuit for gain processing of the signal. To avoid the above problems, it is necessary to adjust the register parameters of the digital-to-analog conversion circuit so that the signal level of the CVBS reaches the protocol standard. Currently, the CVBS signal is mostly collected by an oscilloscope, and then the signal waveform curve in the oscilloscope is observed by the human eye to determine whether the signal level meets the protocol standard. When the requirements are not met, it is necessary to manually adjust the register parameters and determine whether the newly generated CVBS signal meets the protocol standard. If not, continue to adjust and re-determine until the protocol standard is met. The above process requires manual observation of the signal waveform curve and manual participation in debugging. There are problems of long debugging cycle and low accuracy. Summary of the Invention

[0004] Embodiments of the present application provide a method, device, equipment and medium for adjusting a composite video signal CVBS. It is used to adaptively adjust the register parameters of the digital-to-analog conversion circuit according to the comparison result of the proportional parameter and the threshold, without manual participation in debugging, and improve the debugging efficiency and accuracy.

[0005] To achieve the above object, the technical solution of the embodiments of the present application is realized as follows:

[0006] In a first aspect, an embodiment of the present application provides a method for adjusting a composite video signal CVBS, the method includes:

[0007] Controlling a digital-to-analog conversion circuit to perform digital-to-analog conversion on a video stream to generate a composite video signal CVBS, and obtaining the signal frequency of the CVBS and the level amplitude of each signal level; wherein, there is a register in the digital-to-analog conversion circuit for gain processing of the signal, and the register parameters of the register are used to determine the level amplitude of the signal level;

[0008] For each signal level, determine a proportionality parameter of the signal level according to the signal frequency and the level amplitude;

[0009] If the absolute value of the proportionality parameter is between a first threshold and a second threshold, perform multiple rounds of iterative adjustment on the register parameters of the digital-to-analog conversion circuit based on the proportionality parameter; in each round of iteration, regenerate the CVBS according to the adjusted digital-to-analog conversion circuit and determine the proportionality parameter of the CVBS until the absolute value of the proportionality parameter is less than the first threshold, then end the iterative adjustment;

[0010] Control the digital-to-analog conversion circuit to generate the CVBS of the video stream based on the register parameters after iterative adjustment.

[0011] In some possible embodiments, the determining the proportionality parameter of the signal level according to the signal frequency and the level amplitude includes:

[0012] Determine a standard value of the signal level according to the signal frequency;

[0013] Determine the proportionality parameter according to the standard value, the level amplitude, and circuit parameters; wherein the circuit parameters include the output current value of the digital-to-analog conversion circuit, the circuit resistance value, and the level conversion coefficient.

[0014] In some possible embodiments, the determining the proportionality parameter according to the standard value, the level amplitude, and circuit parameters includes:

[0015] Determine an output level value of the digital-to-analog conversion circuit according to the output current value, the circuit resistance value, and the level conversion coefficient;

[0016] Determine the difference between the standard value of the signal level and the level amplitude, and determine the proportionality parameter of the signal level according to the difference and the output level value.

[0017] In some possible embodiments, the signal level includes a peak level; the method further includes:

[0018] Before detecting whether the absolute value of the proportionality parameter is between a first threshold and a second threshold, determine the proportionality parameter of the peak level according to the level amplitude of the peak level, the standard value of the peak level, and the circuit parameters;

[0019] If the absolute value of the proportionality parameter of the peak level is greater than or equal to the second threshold, determine a target resistance value according to the standard value of the peak level and the circuit parameters, and adjust the circuit resistance value to be the same as the target resistance value.

[0020] In some possible embodiments, the digital-to-analog conversion circuit is provided with corresponding registers for each signal level;

[0021] Among them, the register parameters of any register are used to determine the level amplitude of the target signal level of CVBS; the target signal level is the signal level corresponding to the register.

[0022] In some possible embodiments, the register parameters of the target register are adjusted iteratively in multiple rounds in the following manner:

[0023] Determine the adjustment value for this round according to the current iteration round number; among them, the adjustment value for this round is determined according to the number of bits of the target register, and the larger the current iteration round number, the smaller the adjustment value for this round; the target register has the same signal level as the proportional parameter;

[0024] Use the adjustment value for this round to adjust the register parameters multiple times in the target adjustment manner; after each adjustment of the register parameters, control the digital-to-analog conversion circuit to regenerate CVBS based on the register parameters after this adjustment and determine the proportional parameter of the CVBS until the absolute value of the proportional parameter is less than the first threshold, and then end the iterative adjustment.

[0025] In some possible embodiments, the method further includes:

[0026] After each adjustment of the register parameters, if the absolute value of the proportional parameter determined this time is not less than the first threshold, then detect whether the proportional parameter before this adjustment is greater than the third threshold;

[0027] If it is greater than the third threshold, and the proportional parameter determined this time is not greater than the third threshold, then end this round of iteration and enter the next round of iteration;

[0028] If it is not greater than the third threshold, and the proportional parameter determined this time is greater than the third threshold, then end this round of iteration and enter the next round of iteration.

[0029] In some possible embodiments, the step of using the adjustment value for this round to adjust the register parameters multiple times in the target adjustment manner includes:

[0030] Detect whether the proportional parameter before the iterative adjustment is greater than the third threshold;

[0031] If it is greater than the third threshold, and the current iteration round number is odd, perform multiple decreasing adjustments on the register parameters; if the current iteration round number is even, perform multiple increasing adjustments on the register parameters;

[0032] If it is not greater than the third threshold and the current iteration round is odd, the register parameter is adjusted incrementally multiple times; if the current iteration round is even, the register parameter is adjusted decrementally multiple times.

[0033] In a second aspect, an embodiment of the present application provides an adjustment device for a composite video signal CVBS. The device includes:

[0034] An information acquisition module, configured to control a digital-to-analog conversion circuit to perform digital-to-analog conversion on a video stream to generate a composite video signal CVBS, and acquire the signal frequency of the CVBS and the level amplitude of each signal level; wherein, a register for performing gain processing on the signal is provided in the digital-to-analog conversion circuit, and the register parameter of the register is used to determine the level amplitude of the signal level;

[0035] A parameter determination module, configured to perform, for each signal level, determine a proportional parameter of the signal level according to the signal frequency and the level amplitude;

[0036] A parameter adjustment module, configured to perform if the absolute value of the proportional parameter is between a first threshold and a second threshold, then perform multiple rounds of iterative adjustment on the register parameter of the digital-to-analog conversion circuit based on the proportional parameter; in each round of iteration, regenerate the CVBS according to the adjusted digital-to-analog conversion circuit and determine the proportional parameter of the CVBS until the absolute value of the proportional parameter is less than the first threshold to end the iterative adjustment;

[0037] A signal generation module, configured to control the digital-to-analog conversion circuit to generate the CVBS of the video stream based on the register parameter after iterative adjustment.

[0038] In some possible embodiments, when performing the determination of the proportional parameter of the signal level according to the signal frequency and the level amplitude, the parameter determination module is configured to:

[0039] Determine a standard value of the signal level according to the signal frequency;

[0040] Determine the proportional parameter according to the standard value, the level amplitude, and circuit parameters; wherein, the circuit parameters include the output current value of the digital-to-analog conversion circuit, the circuit resistance value, and the level conversion coefficient.

[0041] In some possible embodiments, when performing the determination of the proportional parameter according to the standard value, the level amplitude, and circuit parameters, the parameter determination module is configured to:

[0042] Determine the output level value of the digital-to-analog conversion circuit according to the output current value, the circuit resistance value, and the level conversion coefficient;

[0043] Determine the difference between the standard value of the signal level and the level amplitude, and determine the proportional parameter of the signal level according to the difference and the output level value.

[0044] In some possible embodiments, the signal level includes a peak level; the parameter adjustment module is further configured to:

[0045] Before detecting whether the absolute value of the proportional parameter is between the first threshold and the second threshold, determine the proportional parameter of the peak level according to the level amplitude of the peak level, the standard value of the peak level, and the circuit parameters;

[0046] If the absolute value of the proportional parameter of the peak level is greater than or equal to the second threshold, determine the target resistance value according to the standard value of the peak level and the circuit parameters, and adjust the circuit resistance value to be the same as the target resistance value.

[0047] In some possible embodiments, the digital-to-analog conversion circuit is provided with corresponding registers for each signal level; wherein, the register parameters of any register are used to determine the level amplitude of the target signal level of CVBS; the target signal level is the signal level corresponding to the register.

[0048] In some possible embodiments, the register parameters of the target register are adjusted iteratively in multiple rounds by the following method:

[0049] Determine the adjustment value for this round according to the current iteration round number; wherein, the adjustment value for this round is determined according to the number of bits of the target register, and the larger the current iteration round number, the smaller the adjustment value for this round; the target register is the same as the signal level corresponding to the proportional parameter;

[0050] Adjust the register parameters multiple times in the target adjustment manner by using the adjustment value for this round; after each adjustment of the register parameters, control the digital-to-analog conversion circuit to regenerate CVBS based on the register parameters after this adjustment and determine the proportional parameter of the CVBS until the absolute value of the proportional parameter is less than the first threshold, and then end the iterative adjustment.

[0051] In some possible embodiments, the parameter adjustment module is further configured to:

[0052] After each adjustment of the register parameters, if the absolute value of the proportional parameter determined this time is not less than the first threshold, detect whether the proportional parameter before this adjustment is greater than the third threshold;

[0053] If it is greater than the third threshold, and the proportional parameter determined this time is not greater than the third threshold, end this round of iteration and enter the next round of iteration;

[0054] If it is not greater than the third threshold and the ratio parameter determined this time is greater than the third threshold, end the current iteration and enter the next iteration.

[0055] In some possible embodiments, when performing the multiple adjustments to the register parameters by using the adjustment value of the current round in the target adjustment manner, the parameter adjustment module is configured to:

[0056] Detect whether the ratio parameter before the iterative adjustment is greater than the third threshold;

[0057] If it is greater than the third threshold and the current iteration number is odd, perform multiple decreasing adjustments to the register parameters; if the current iteration number is even, perform multiple increasing adjustments to the register parameters;

[0058] If it is not greater than the third threshold and the current iteration number is odd, perform multiple increasing adjustments to the register parameters; if the current iteration number is even, perform multiple decreasing adjustments to the register parameters.

[0059] In a third aspect, an embodiment of the present application further provides an electronic device, including a memory and a processor. A computer program that can run on the processor is stored on the memory. When the computer program is executed by the processor, the processor implements any of the methods in the first aspect above.

[0060] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium. A computer program is stored in the computer-readable storage medium. When the computer program is executed by a processor, any of the methods in the first aspect above is implemented.

[0061] In a fifth aspect, a computer program product according to an embodiment of the present application includes computer instructions, and the computer instructions are stored in a computer-readable storage medium; when a processor of a computer device reads the computer instructions from the computer-readable storage medium, the processor executes the computer instructions, so that the computer device executes any of the methods in the first aspect above.

[0062] In the embodiments of the present application, the digital-to-analog conversion circuit is controlled to perform digital-to-analog conversion on the video stream to obtain a composite video signal CVBS. Furthermore, the proportional parameter of the signal level is determined according to the signal frequency and the amplitude of the signal level, and whether to adjust the digital-to-analog conversion circuit is determined according to the comparison result between the proportional parameter and the threshold. During the adjustment, the register parameters of the digital-to-analog conversion circuit are iteratively adjusted multiple times based on the proportional parameter. In each iteration process, the proportional parameter is re-determined according to the digital-to-analog conversion circuit after the previous adjustment, and whether the adjustment is completed is determined according to the comparison result between the re-determined proportional parameter and the threshold. The above process can adaptively adjust the register parameters of the digital-to-analog conversion circuit according to the comparison result between the proportional parameter and the threshold, without manual debugging, improving the debugging efficiency and accuracy.

[0063] Other features and advantages of the present application will be described in the following specification, and, in part, will be obvious from the specification, or will be understood by implementing the present disclosure. The objectives and other advantages of the present application can be achieved and obtained by the structures specifically pointed out in the written specification, claims, and drawings. Brief Description of the Drawings

[0064] Figure 1 is a schematic structural diagram of the digital-to-analog conversion circuit provided by the embodiments of the present application;

[0065] Figure 2 is an overall flowchart of the adjustment method for the composite video signal CVBS provided by the embodiments of the present application;

[0066] Figure 3 is a schematic structural diagram of the detection circuit provided by the embodiments of the present application;

[0067] Figure 4 is a schematic connection diagram of the digital-to-analog conversion circuit and the detection circuit provided by the embodiments of the present application;

[0068] Figure 5 is a schematic diagram of a four-bit register provided by the embodiments of the present application;

[0069] Figure 6 is a schematic diagram of the iterative adjustment process provided by the embodiments of the present application;

[0070] Figure 7 is another schematic diagram of the iterative adjustment process provided by the embodiments of the present application;

[0071] Figure 8 is a structural diagram of the adjustment device 800 for the composite video signal CVBS provided by the embodiments of the present application;

[0072] Figure 9 is a structural diagram of an electronic device provided by the embodiments of the present application. Detailed Embodiments

[0073] To make the objectives, technical solutions, and advantages of this application clearer and more understandable, the following will, in combination with the accompanying drawings in the embodiments of this application, clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts fall within the scope of protection of this application. Without conflict, the embodiments in this application and the features in the embodiments can be combined arbitrarily with each other. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0074] The terms "first" and "second" in the description and claims of this application and the above accompanying drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices. "Multiple" in this application can represent at least two, for example, it can be two, three, or more, and the embodiments of this application do not make limitations.

[0075] As previously mentioned, most imaging devices convert the collected video stream into a composite video broadcast signal through a digital-to-analog conversion circuit to avoid the problem of audio-video signal mixing interference. Specifically Figure 1 As shown, the imaging device inputs the collected video stream into the digital-to-analog conversion circuit, and the digital-to-analog conversion circuit obtains the CVBS signal through digital-to-analog conversion processing of the video frame image. To ensure the image quality, the protocol stipulates the standard values of each signal level in the CVBS signal. Since the CVBS signal is a composite signal, when obtaining each signal level of it, it is necessary to separate the CVBS signal to obtain its corresponding peak signal, synchronization signal, and color synchronization signal, and then obtain the peak level of the peak signal, the synchronization level of the synchronization signal, and the color synchronization level of the color synchronization signal.

[0076] The structure of the digital-to-analog conversion circuit is as Figure 1 shown. The circuit mainly includes a grounding resistor 100 and multiple registers 101 for signal gain processing inside. Each register 101 affects one signal level of the CVBS signal. When the level amplitude of the CVBS signal generated by the circuit does not meet the protocol standard, there will be problems such as overexposure and underexposure in the image quality. At this time, it is necessary to adjust the register parameters to make the level amplitude of the CVBS signal reach the protocol standard.

[0077] The existing parameter adjustment method mainly obtains the waveform curve of the CVBS signal through an oscilloscope, observes the waveform curve with the human eye to obtain the amplitude value of each signal level of the CVBS signal, and then determines whether it meets the protocol standard. When the protocol standard is not met, the register parameters need to be adjusted manually, and it is necessary to determine whether the newly generated CVBS signal meets the protocol standard. If it does not meet the standard, continue to adjust and re-judge until the protocol standard is met. The above process requires manual observation of the waveform curve of the signal and manual participation in debugging. There are problems of long debugging cycle and low accuracy.

[0078] To solve the above problems, the inventive concept of the embodiment of the present application is as follows: the digital-to-analog conversion circuit is controlled to perform digital-to-analog conversion on the video stream to obtain the composite video signal CVBS. Furthermore, the proportional parameter of the signal level is determined according to the signal frequency and the amplitude value of the signal level. And it is determined whether it is necessary to adjust the digital-to-analog conversion circuit according to the comparison result between the proportional parameter and the threshold value.

[0079] During the adjustment process, the register parameters of the digital-to-analog conversion circuit are adjusted iteratively for multiple rounds based on the proportional parameter. In each round of iteration, the proportional parameter is re-determined according to the digital-to-analog conversion circuit after the previous round of adjustment, and it is determined whether the adjustment is completed according to the comparison result between the re-determined proportional parameter and the threshold value. The above process can adaptively adjust the register parameters of the digital-to-analog conversion circuit according to the comparison result between the proportional parameter and the threshold value, without manual participation in debugging, improving the debugging efficiency and accuracy.

[0080] Next, as Figure 2 shown, Figure 2 shows the overall process of an adjustment method for a composite video signal CVBS provided by an embodiment of the present application, which specifically includes:

[0081] Step 201: Control the digital-to-analog conversion circuit to perform digital-to-analog conversion on the video stream to generate the composite video signal CVBS, and obtain the signal frequency of the CVBS and the amplitude value of each signal level; wherein, a register for performing gain processing on the signal is provided in the digital-to-analog conversion circuit, and the register parameter of the register is used to determine the amplitude value of the signal level;

[0082] In the embodiment of the present application, a detection circuit is externally connected to the digital-to-analog conversion circuit, and the detection circuit is used to identify the signal frequency of the CVBS signal and the amplitude value of each signal level in the CVBS signal. The detection circuit is used to detect the signal frequency and the amplitude value of the CVBS signal. Figure 3 shows the structural diagram of the detection circuit in the embodiment of the present application, as Figure 3As shown in the figure, the detection circuit includes a light-shielding circuit 300, a discrimination circuit 301, a motor control circuit 302, a signal separation circuit 304, and a grounding resistance 305. The light-shielding circuit 300 is used to control the shutter to block the camera of the imaging device. When extracting the level amplitude, the light-shielding circuit 300 controls the shutter to lift, allowing a large amount of light flux to enter the camera. What is not shown in the figure is that the light-shielding circuit 300 consists of a shutter and a light source. When the circuit controls the shutter to block the input optical path of the camera, the light source is turned off; when the shutter is lifted, the light source directly irradiates the input optical path of the camera.

[0083] The discrimination circuit 301 is used to determine whether the level amplitude of the collected CVBS signal reaches the maximum. If it does not reach the maximum, it sends an indication signal to the motor control circuit 302, instructing it to control the light-shielding circuit 300 to lower and quickly lift the shutter, so that a large amount of light flux enters the camera, and then the level amplitude of the re-collected signal reaches the maximum. Correspondingly, when the level amplitude reaches the maximum, the CVBS signal is transmitted to the signal separation circuit 304.

[0084] As previously mentioned, the CVBS signal is a composite signal, and the video signal level defines the signal levels corresponding to different parts of the CVBS signal. Therefore, when obtaining each signal level, the CVBS signal needs to be separated to obtain its corresponding peak signal, synchronization signal, and color synchronization signal. Then, the level amplitude of the peak level is determined according to the peak signal, the level amplitude of the synchronization level is determined according to the synchronization signal, and the level amplitude of the color synchronization level is determined according to the color synchronization signal.

[0085] Figure 3 The signal separation circuit 304 shown in the figure separates the CVBS signal to obtain its signal frequency and amplitude information, and reconverts it from an analog signal to a digital signal. The amplitude information includes the level amplitude corresponding to each signal level of the CVBS signal, and the signal levels include the above-mentioned peak level, synchronization level, and color synchronization level.

[0086] Step 202: For each signal level, determine the proportional parameter of the signal level according to the signal frequency and the level amplitude;

[0087] In implementation, the standard value of each signal level is determined according to the signal frequency of the CVBS signal, and then the proportional parameter is determined according to the standard value, the level amplitude, and the circuit parameters. The above-mentioned standard value is the level standard value of the signal level specified in the protocol mentioned above. The obtained proportional parameter characterizes the difference between the level amplitude of this signal level and the standard value specified in the protocol. The larger the absolute value of the obtained proportional parameter, the more it indicates the difference from the protocol standard.

[0088] Next, the above circuit parameters will be described. The digital-to-analog conversion circuit needs to transmit the CVBS signal to the detection circuit through a coaxial cable to obtain the signal frequency and amplitude information. The above circuit parameters include the output current value I of the digital-to-analog conversion circuit CVBS , the circuit resistance value R s1 , and the level conversion coefficient β.

[0089] Taking the detection circuit shown above Figure 3 as an example, specifically as Figure 4 shown, Figure 4 the digital-to-analog conversion circuit shown is connected to the detection circuit through a coaxial cable 400. The digital-to-analog conversion circuit is used to transmit the output CVBS signal to the detection circuit through the coaxial cable 400. I in the above circuit parameters CVBS is the current value of the CVBS signal output by the digital-to-analog conversion circuit, and R s1 is the ground resistance inside the digital-to-analog conversion circuit. β is determined according to the resistance R of the coaxial cable and the ground resistance R s2 of the detection circuit. Specifically, it is expressed as β = R s2 / (R + R s2 ).

[0090] During implementation, the output level value of the digital-to-analog conversion circuit can be determined according to the output current value I CVBS , the circuit resistance value R s1 , and the level conversion coefficient R s1 . Then, the proportional parameter of the signal level can be determined according to the difference between the standard value and the level amplitude of the signal level and the output level value. The specific calculation process can be shown as the following formula (1):

[0091]

[0092] where α is the proportional parameter, U0 is the standard value of the signal level, U m is the level amplitude of the signal level, and I CVBS ×R S1 ×β represents the output level value of the digital-to-analog conversion circuit.

[0093] Step 203: If the absolute value of the proportional parameter is between the first threshold and the second threshold, then perform multiple rounds of iterative adjustment on the register parameters of the digital-to-analog conversion circuit based on the proportional parameter; during each round of iteration, regenerate the CVBS according to the adjusted digital-to-analog conversion circuit and determine the proportional parameter of the CVBS until the absolute value of the proportional parameter is less than the first threshold to end the iterative adjustment;

[0094] As mentioned above, the proportionality parameter is used to characterize the difference between the amplitude of the signal level and the standard value specified by the protocol, and the larger the absolute value of the proportionality parameter, the greater the difference from the protocol standard. After determining the proportionality parameter corresponding to the signal level in step 202, if the absolute value of the proportionality parameter is between the first threshold and the second threshold, it indicates that the CVBS signal currently generated by the digital-to-analog conversion circuit does not meet the protocol standard, and the register parameters of the circuit need to be adjusted to bring the CVBS signal generated by the circuit into compliance with the protocol standard. In the embodiment of the present application, the first threshold is set to 0.005, and the second threshold is set to 0.1.

[0095] If the absolute value of the ratio parameter is less than 0.005, it means that the level amplitude meets the protocol standard. If the absolute value of the ratio parameter falls between 0.005 and 0.1, it means that the register parameters in the digital-to-analog conversion circuit need to be adjusted. It should be noted that the embodiment of the present application does not change the original digital-to-analog conversion circuit structure. The application is the aforementioned Figure 1 The digital-to-analog conversion circuit shown. That is, in the digital-to-analog conversion circuit of the present application, a corresponding register is provided for each signal level. The register parameter of any register is used to determine the level amplitude of the target signal level of CVBS. The target signal level is the signal level corresponding to the register. Therefore, taking the above three signal levels as an example, assuming that the proportional parameter of the synchronization level falls between 0.005 and 0.1, and the proportional parameters of the other two signal levels are both less than 0.005, it means that only the parameters of the register corresponding to the synchronization level need to be adjusted.

[0096] Considering the ground resistance in the digital-to-analog conversion circuit (i.e. the above R S1 ) will affect the level amplitude of each signal level of the CVBS signal. Before executing the above step 203, the proportional parameter corresponding to the peak level can be determined by formula (1). If the proportional parameter corresponding to the peak level is ≥ 0.1, it means that the CVBS signal generated by the current digital-to-analog conversion circuit is significantly different from the protocol standard. In this case, the CVBS signal can be generated by adjusting R S1 The resistance value is used to achieve coarse adjustment of the digital-to-analog conversion circuit.

[0097] During implementation, before executing step 203, the proportional parameter of the peak level must be compared with the second threshold. If it is less than the second threshold, the process of step 203 is executed. If it is greater than or equal to the second threshold, the target resistance value is determined according to the standard value of the peak level and the circuit parameters, and the circuit resistance value is adjusted to be the same as the target resistance value. The above process adjusts the circuit resistance value of the digital-to-analog conversion circuit to achieve the purpose of coarse adjustment of the register parameters. The proportional parameter corresponding to the CVBS signal generated by the digital-to-analog conversion circuit after this adjustment can fall between 0.005 and 0.1. Among them, the calculation process of the above target resistance value is shown in the following formula (2):

[0098]

[0099] Among them, Rs is the target resistance value, U p is the standard value of the peak level, I CVBS is the output current value of the digital-to-analog conversion circuit, and β is the level conversion coefficient.

[0100] When performing the above step 203, first determine the target register according to the current ratio parameter. The target register has the same signal level as the ratio parameter. As mentioned above, there is a corresponding register for each signal level in the digital-to-analog conversion circuit. Therefore, if the ratio parameter of the current synchronization level falls between 0.005 and 0.1, it means that the register corresponding to the synchronization level needs to be adjusted. At this time, the register corresponding to the synchronization level is the target register. In implementation, the register parameters of the target register can be adjusted iteratively in multiple rounds through the following method:

[0101] Determine the adjustment value for this round according to the current iteration round number; among them, the adjustment value for this round is determined according to the number of bits of the target register. The larger the current iteration round number, the smaller the adjustment value for this round;

[0102] Use the adjustment value for this round to adjust the register parameters in multiple times in the target adjustment manner; after each adjustment of the register parameters, control the digital-to-analog conversion circuit to regenerate CVBS based on the register parameters after this adjustment and determine the ratio parameter of CVBS until the absolute value of the ratio parameter is less than the first threshold, and then end the iterative adjustment.

[0103] In any iteration round, the target adjustment manner for each adjustment is determined through the following method. First, detect whether the ratio parameter before this iterative adjustment is greater than the third threshold. The third threshold in this application is 0. If it is greater than the third threshold and the current iteration round number is odd, perform multiple decreasing adjustments on the register parameters; when the current iteration round number is even, perform multiple increasing adjustments on the register parameters. If it is not greater than the third threshold and the current iteration round number is odd, perform multiple increasing adjustments on the register parameters; when the current iteration round number is even, perform multiple decreasing adjustments on the register parameters.

[0104] In addition, after each adjustment of the register parameters, if the absolute value of the ratio parameter determined this time is not less than the first threshold, detect whether the ratio parameter before this adjustment is greater than the above third threshold. If it is greater than the third threshold and the ratio parameter determined this time is not greater than the third threshold, end this iteration round and enter the next iteration round. If it is not greater than the third threshold and the ratio parameter determined this time is greater than the third threshold, end this iteration round and enter the next iteration round.

[0105] The above iterative adjustment process will be explained below by taking a four-bit register as an example. Specifically,Figure 5 As shown. The register includes a total of four bits, P1 to P4, with each bit incrementing in hexadecimal, and the minimum count value is 1. Based on the number of bits in the register, the iterative process is divided into 5 rounds of iteration. The specific division method is that the adjustment value in the first round is 16, the second round is 8, the third round is 4, the fourth round is 2, and the last round is the minimum count value of 1. This can gradually reduce the adjustment range of each round of iteration and make the final result more accurate.

[0106] Taking the case where the ratio parameter before iteration is greater than the third threshold as an example, in the first round of iteration, if the ratio parameter is greater than the third threshold, then as Figure 6 shown on the left, in the first round of iteration, the register parameter value is decreased multiple times, each time by 16, until the re-determined ratio parameter is less than or equal to the third threshold and then enters the second round of iteration. In the second round of iteration, the register parameter value is increased by 8 each time until the re-determined ratio parameter is greater than the third threshold again and then enters the third round of iteration. In the third round of iteration, the register parameter value is decreased by 4 each time until the re-determined ratio parameter is less than or equal to the third threshold again and then enters the fourth round of iteration. In the fourth round of iteration, the register parameter value is increased by 2 each time until the re-determined ratio parameter is less than or equal to the third threshold again and then enters the fifth round of iteration. In the fifth round of iteration, the register parameter value is decreased by 1 each time. Since the adjustment range at this time is already the minimum count unit of the register parameter, a ratio parameter that meets the condition (i.e., the absolute value of the ratio parameter ≤ 0.005) will surely appear in this round.

[0107] After each adjustment of the register parameter, the control digital-to-analog conversion circuit performs digital-to-analog conversion on the video stream according to the adjusted register parameter to regenerate the CVBS signal, and re-determines the ratio parameter corresponding to the CVBS signal through the above step 202. If the absolute value of the re-determined ratio parameter after a certain adjustment is ≤ 0.005, it means that the level assignment of the signal level corresponding to the current ratio parameter meets the protocol standard and no adjustment is required. At this time, fix the parameter of the target register as the current register parameter and exit the iterative process. Another example is Figure 6 shown. If the ratio parameter before iterative adjustment is less than or equal to the third threshold, the target adjustment method for each round changes from increasing to decreasing. The determination method for entering the next round of iteration changes from the re-determined ratio parameter being greater than 0 to being less than or equal to 0.

[0108] For ease of understanding the above iterative adjustment process, Figure 7 the flowchart of the above iterative adjustment is shown, including:

[0109] Step 701: Detect whether the ratio parameter is greater than the third threshold;

[0110] That is, before the first round of iterative adjustment, first detect whether the ratio parameter is greater than the third threshold 0;

[0111] Step 702: Determine the adjustment value and target adjustment method for this round according to the detection result;

[0112] If the ratio parameter before iterative adjustment is greater than the third threshold, it indicates that the register parameter needs to be adjusted reversely first and then forwardly. That is, the target adjustment method for odd-numbered rounds of iteration is decreasing adjustment. The so-called decreasing adjustment means subtracting the adjustment value for this round from the current value of the register parameter each time (the adjustment value for the first round is 16, the third round is 4, and the fifth round is 1). The target adjustment method for even-numbered rounds of iteration is increasing adjustment. The so-called increasing adjustment means adding the adjustment value for this round to the current value of the register parameter each time (the adjustment value for the second round is 8, and the fourth round is 2).

[0113] Correspondingly, if the ratio parameter before iterative adjustment is not greater than the third threshold, the register parameter needs to be adjusted forwardly first and then reversely. That is, the target adjustment method for odd-numbered rounds of iteration is increasing adjustment. The target adjustment method for even-numbered rounds of iteration is decreasing adjustment.

[0114] Step 703: Based on the adjustment value for this round, adjust the target register value using the target adjustment method;

[0115] Step 704: Control the digital-to-analog conversion circuit to perform digital-to-analog conversion on the video stream according to the adjusted register parameter to regenerate the CVBS signal, and re-determine the ratio parameter of the signal level;

[0116] After each adjustment of the register parameter, control the digital-to-analog conversion circuit to perform digital-to-analog conversion on the video stream according to the adjusted register parameter to regenerate the CVBS signal, and re-determine the ratio parameter corresponding to the CVBS signal through the aforementioned step 202.

[0117] Step 705: Detect whether the absolute value of the re-determined ratio parameter is greater than the first threshold;

[0118] It should be noted here that as mentioned above, before performing iterative adjustment in this application, it is necessary to determine whether it is necessary to adjust the circuit resistance value of the digital-to-analog conversion circuit to achieve rough adjustment by whether the absolute value of the ratio parameter of the peak level is greater than the second threshold.

[0119] Assume that rough adjustment is required. After adjusting the register parameter of the digital-to-analog conversion circuit after rough adjustment, the absolute value of the ratio parameter newly determined according to the adjusted circuit will not be ≥0.1. That is, at this time, the absolute value of the re-determined ratio parameter can only be ≤0.005 or still be between 0.005 and 0.1.

[0120] Step 706: If it is less than or equal to the first threshold, end the iterative adjustment process.

[0121] If ≤ 0.005, it indicates that the level assignment of the signal level corresponding to the current ratio parameter meets the protocol standard and no adjustment is required. At this time, the parameters of the target register can be fixed as the current register parameters.

[0122] Step 707: If it is greater than the first threshold, detect whether the comparison result of the absolute value of the re-determined ratio parameter and the first threshold has changed;

[0123] In specific implementation, detect whether the comparison result of the absolute value of the re-determined ratio parameter in this iteration and the first threshold has changed compared with the previous iteration. If it has changed, it indicates that the register parameters need to be adjusted in the reverse direction, that is, enter the next iteration. Otherwise, continue to adjust the register parameters according to the adjustment value of this round.

[0124] The purpose of performing the above detection is to determine whether the register parameters have been adjusted too far. Specifically, in one round of iterative adjustment process, the register parameters are adjusted multiple times in the target adjustment manner. Whether the target adjustment manner uses incremental adjustment or decremental adjustment is determined according to the ratio parameter of the previous round. Taking the ratio parameter before iteration > 0 as an example, for example, if the ratio parameter in the previous iteration > 0, it indicates that the target adjustment manner in the previous round is decremental adjustment. When the ratio parameter of the previous round is adjusted to ≤ 0, this round of iterative adjustment is entered. This round of iterative adjustment needs to adjust the register parameters in the reverse direction, that is, change to incremental adjustment.

[0125] In addition, as shown in the aforementioned step 704, after each adjustment, it is necessary to detect whether the re-determined ratio parameter is less than 0.005. If it is less than 0.005, it indicates that the protocol standard has been reached and there is no need to adjust the register parameters of the target register again.

[0126] Step 708: If it has changed, enter the next iteration; otherwise, return to the aforementioned step 703.

[0127] Step 204: Control the digital-to-analog conversion circuit to generate the CVBS of the video stream based on the register parameters after iterative adjustment.

[0128] After adjusting each register parameter that needs to be adjusted through the above process, it can be ensured that in the CVBS signal generated by the digital-to-analog conversion circuit based on the adjusted register parameters, the level amplitude of each signal level meets the protocol standard.

[0129] The above process controls the digital-to-analog conversion circuit to perform digital-to-analog conversion on the video stream to obtain the composite video signal CVBS, and then obtains the signal frequency of the CVBS and the amplitude of each signal level. For each signal level, the proportional parameter of the signal level is determined according to the standard value, amplitude and circuit parameters of the signal level. Furthermore, whether to adjust the digital-to-analog conversion circuit is determined according to the comparison result between the proportional parameter and the threshold. When adjusting, the register parameters of the digital-to-analog conversion circuit are adjusted iteratively for multiple rounds based on the proportional parameter. In each round of iteration, the proportional parameter is re-determined according to the digital-to-analog conversion circuit after the previous adjustment, and whether the adjustment is completed is determined according to the comparison result between the re-determined proportional parameter and the threshold. Thus, the register parameters of the digital-to-analog conversion circuit are adaptively adjusted without manual debugging, improving the debugging efficiency and accuracy.

[0130] Based on the same inventive concept, an embodiment of the present application provides an adjustment device 800 for a composite video signal CVBS, specifically as Figure 8 shown, including:

[0131] An information acquisition module 801, configured to control a digital-to-analog conversion circuit to perform digital-to-analog conversion on a video stream to generate a composite video signal CVBS, and acquire the signal frequency of the CVBS and the amplitude of each signal level; wherein, a register for performing gain processing on the signal is provided in the digital-to-analog conversion circuit, and the register parameter of the register is used to determine the amplitude of the signal level;

[0132] A parameter determination module 802, configured to execute, for each signal level, determine the proportional parameter of the signal level according to the signal frequency and the amplitude;

[0133] A parameter adjustment module 803, configured to execute if the absolute value of the proportional parameter is between a first threshold and a second threshold, then perform multiple rounds of iterative adjustment on the register parameter of the digital-to-analog conversion circuit based on the proportional parameter; in each round of iteration, regenerate CVBS according to the adjusted digital-to-analog conversion circuit and determine the proportional parameter of the CVBS until the absolute value of the proportional parameter is less than the first threshold to end the iterative adjustment;

[0134] A signal generation module 804, configured to control the digital-to-analog conversion circuit to generate the CVBS of the video stream based on the register parameter after iterative adjustment.

[0135] In some possible embodiments, when executing to determine the proportional parameter of the signal level according to the signal frequency and the amplitude, the parameter determination module is configured to:

[0136] Determine the standard value of the signal level according to the signal frequency;

[0137] Determine the proportional parameter according to the standard value, the level amplitude, and the circuit parameters; wherein, the circuit parameters include the output current value of the digital-to-analog conversion circuit, the circuit resistance value, and the level conversion coefficient.

[0138] In some possible embodiments, when performing the determination of the proportional parameter according to the standard value, the level amplitude, and the circuit parameters, the parameter determination module is configured to:

[0139] Determine the output level value of the digital-to-analog conversion circuit according to the output current value, the circuit resistance value, and the level conversion coefficient;

[0140] Determine the difference between the standard value and the level amplitude of the signal level, and determine the proportional parameter of the signal level according to the difference and the output level value.

[0141] In some possible embodiments, the signal level includes a peak level; the parameter adjustment module is further configured to:

[0142] Before detecting whether the absolute value of the proportional parameter is between the first threshold and the second threshold, determine the proportional parameter of the peak level according to the level amplitude of the peak level, the standard value of the peak level, and the circuit parameters;

[0143] If the absolute value of the proportional parameter of the peak level is greater than or equal to the second threshold, determine the target resistance value according to the standard value of the peak level and the circuit parameters, and adjust the circuit resistance value to be the same as the target resistance value.

[0144] In some possible embodiments, the digital-to-analog conversion circuit has a corresponding register for each signal level; wherein, the register parameter of any register is used to determine the level amplitude of the target signal level of CVBS; the target signal level is the signal level corresponding to the register.

[0145] In some possible embodiments, the register parameters of the target register are adjusted iteratively in multiple rounds in the following manner:

[0146] Determine the adjustment value for this round according to the current iteration round number; wherein, the adjustment value for this round is determined according to the number of bits of the target register, and the larger the current iteration round number, the smaller the adjustment value for this round; the target register is the same as the signal level corresponding to the proportional parameter;

[0147] Adjust the register parameters multiple times using the adjustment value of this round in the target adjustment manner; after each adjustment of the register parameters, control the digital-to-analog conversion circuit to regenerate the CVBS based on the register parameters after this adjustment and determine the ratio parameter of the CVBS, until the absolute value of the ratio parameter is less than the first threshold to end the iterative adjustment.

[0148] In some possible embodiments, the parameter adjustment module is further configured to:

[0149] After each adjustment of the register parameters, if the absolute value of the ratio parameter determined this time is not less than the first threshold, detect whether the ratio parameter before this adjustment is greater than the third threshold;

[0150] If it is greater than the third threshold and the ratio parameter determined this time is not greater than the third threshold, end this round of iteration and enter the next round of iteration;

[0151] If it is not greater than the third threshold and the ratio parameter determined this time is greater than the third threshold, end this round of iteration and enter the next round of iteration.

[0152] In some possible embodiments, when performing the multiple adjustments of the register parameters using the adjustment value of this round in the target adjustment manner, the parameter adjustment module is configured to:

[0153] Detect whether the ratio parameter before the iterative adjustment is greater than the third threshold;

[0154] If it is greater than the third threshold and the current iteration round number is odd, perform multiple decreasing adjustments on the register parameters; when the current iteration round number is even, perform multiple increasing adjustments on the register parameters;

[0155] If it is not greater than the third threshold and the current iteration round number is odd, perform multiple increasing adjustments on the register parameters; when the current iteration round number is even, perform multiple decreasing adjustments on the register parameters.

[0156] Next, refer to Figure 9 to describe an electronic device 130 according to this embodiment of the present application. Figure 9 The shown electronic device 130 is only an example and should not bring any limitation to the functions and usage scope of the embodiments of the present application.

[0157] As Figure 9 shown, the electronic device 130 is presented in the form of a general electronic device. The components of the electronic device 130 may include but are not limited to: the at least one processor 131 described above, the at least one memory 132 described above, and a bus 133 connecting different system components (including the memory 132 and the processor 131).

[0158] The bus 133 represents one or more of several types of bus architectures, including a memory bus or memory controller, a peripheral bus, a processor, or a local bus using any of the multiple bus architectures.

[0159] The memory 132 may include a readable medium in the form of volatile memory, such as random access memory (RAM) 1321 and / or cache memory 1322, and may further include read-only memory (ROM) 1323.

[0160] The memory 132 may also include a program / utilities 1325 having a set (at least one) of program modules 1324. Such program modules 1324 include, but are not limited to: an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment.

[0161] The electronic device 130 may also communicate with one or more external devices 134 (such as a keyboard, a pointing device, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 130, and / or may communicate with any device that enables the electronic device 130 to communicate with one or more other electronic devices (such as a router, a modem, etc.). Such communication may be carried out through an input / output (I / O) interface 135. Moreover, the electronic device 130 may also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through a network adapter 136. As shown in the figure, the network adapter 136 communicates with other modules for the electronic device 130 through the bus 133. It should be understood that although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 130, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0162] In an exemplary embodiment, a computer-readable storage medium including instructions is also provided, such as the memory 132 including instructions, and the above instructions can be executed by the processor 131 of the above device to complete the above method. Optionally, the computer-readable storage medium may be ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage devices, etc.

[0163] In an exemplary embodiment, a computer program product is also provided, including a computer program / instructions, and when the computer program / instructions are executed by the processor 131, any of the methods in a method for adjusting a composite video signal CVBS provided in this application is implemented.

[0164] In an exemplary embodiment, various aspects of an adjustment method for a composite video signal CVBS provided by the present application can also be implemented in the form of a program product, which includes program code. When the program product runs on a computer device, the program code is used to cause the computer device to execute the steps in an adjustment method for a composite video signal CVBS according to various exemplary embodiments described above in this specification.

[0165] The program product can adopt any combination of one or more readable media. The readable media can be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (non-exhaustive list) of the readable storage medium include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0166] The program product for the adjustment of the composite video signal CVBS according to the embodiments of the present application can adopt a portable compact disk read-only memory (CD-ROM) and include program code, and can run on an electronic device. However, the program product of the present application is not limited to this. In this document, the readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system, apparatus, or device.

[0167] The readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries the readable program code. Such a propagated data signal can take various forms, including - but not limited to - an electromagnetic signal, an optical signal, or any suitable combination of the above. The readable signal medium can also be any readable medium other than the readable storage medium, and this readable medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device.

[0168] The program code contained on the readable medium can be transmitted using any appropriate medium, including - but not limited to - wireless, wired, optical cable, RF, etc., or any suitable combination of the above.

[0169] The program code for performing the operations of the present application can be written in any combination of one or more programming languages. The programming languages include object-oriented programming languages such as Java, C++, etc., and also include conventional procedural programming languages such as C or similar programming languages. The program code can be executed entirely on the user's electronic device, partially on the user's device, executed as a stand-alone software package, partially on the user's electronic device and partially on a remote electronic device, or entirely on a remote electronic device or server. In cases involving a remote electronic device, the remote electronic device can be connected to the user's electronic device through any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external electronic device (e.g., by using an Internet service provider to connect through the Internet).

[0170] It should be noted that although several units or subunits of the apparatus are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of the two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units.

[0171] In addition, although the operations of the method of the present application are described in a specific order in the drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, some steps can be omitted, multiple steps can be combined into one step for execution, and / or one step can be decomposed into multiple steps for execution.

[0172] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

[0173] This application is described with reference to the flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processors of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable image scaling devices to generate a machine, such that the instructions executed by the processors of the computer or other programmable image scaling devices generate means for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0174] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable image scaling device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means that implement the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0175] These computer program instructions can also be loaded onto a computer or other programmable image scaling device, such that a series of operational steps are executed on the computer or other programmable device to generate a computer-implemented process, thereby providing steps for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0176] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0177] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these changes and modifications.

Claims

1. A method for adjusting a composite video signal CVBS, characterized in that, The method includes: Controlling a digital-to-analog conversion circuit to perform digital-to-analog conversion on a video stream to generate a composite video signal CVBS, and obtaining the signal frequency of the CVBS and the level amplitude of each signal level; wherein, a register for performing gain processing on the signal is provided in the digital-to-analog conversion circuit, and the register parameters of the register are used to determine the level amplitude of the signal level; For each signal level, determining a standard value of the signal level according to the signal frequency, and determining a proportionality parameter of the signal level according to the standard value, the level amplitude, and circuit parameters; the circuit parameters include the output current value of the digital-to-analog conversion circuit, the circuit resistance value, and the level conversion coefficient; If the absolute value of the proportionality parameter is between a first threshold and a second threshold, performing multiple rounds of iterative adjustment on the register parameters of the digital-to-analog conversion circuit based on the proportionality parameter; in each round of iteration, regenerating the CVBS according to the adjusted digital-to-analog conversion circuit and determining the proportionality parameter of the CVBS until the absolute value of the proportionality parameter is less than the first threshold to end the iterative adjustment; Controlling the digital-to-analog conversion circuit to generate the CVBS of the video stream based on the register parameters after iterative adjustment.

2. The method according to claim 1, wherein The determining the proportionality parameter according to the standard value, the level amplitude, and the circuit parameters includes: Determining an output level value of the digital-to-analog conversion circuit according to the output current value, the circuit resistance value, and the level conversion coefficient; Determining the difference between the standard value and the level amplitude of the signal level, and determining the proportionality parameter of the signal level according to the difference and the output level value.

3. The method according to claim 1, characterized in that, The signal level includes a peak level; the method further includes: Before detecting whether the absolute value of the proportionality parameter is between the first threshold and the second threshold, determining the proportionality parameter of the peak level according to the level amplitude of the peak level, the standard value of the peak level, and the circuit parameters; If the absolute value of the proportionality parameter of the peak level is greater than or equal to the second threshold, determining a target resistance value according to the standard value of the peak level and the circuit parameters, and adjusting the circuit resistance value to be the same as the target resistance value.

4. The method according to claim 1, characterized in that The digital-to-analog conversion circuit is provided with a corresponding register for each signal level; Wherein, the register parameters of any register are used to determine the level amplitude of the target signal level of the CVBS; the target signal level is the signal level corresponding to the register.

5. The method according to claim 4, wherein Performing multiple rounds of iterative adjustment on the register parameters of the target register in the following manner: Determining the adjustment value of this round according to the current iteration round number; wherein, the adjustment value of this round is determined according to the number of bits of the target register, and the larger the current iteration round number, the smaller the adjustment value of this round; the target register is the same as the signal level corresponding to the proportionality parameter; Using the adjustment value of this round to perform multiple adjustments on the register parameters in a target adjustment manner; after each adjustment of the register parameters, controlling the digital-to-analog conversion circuit to regenerate the CVBS based on the register parameters after this adjustment and determining the proportionality parameter of the CVBS until the absolute value of the proportionality parameter is less than the first threshold to end the iterative adjustment.

6. The method according to claim 5, wherein The method further includes: After each adjustment of the register parameter, if the absolute value of the determined proportional parameter this time is not less than the first threshold, it is detected whether the proportional parameter before this adjustment is greater than the third threshold; If it is greater than the third threshold and the determined proportional parameter this time is not greater than the third threshold, this round of iteration is ended and the next round of iteration is entered; If it is not greater than the third threshold and the determined proportional parameter this time is greater than the third threshold, this round of iteration is ended and the next round of iteration is entered.

7. The method according to claim 5 or 6, characterized in that, The multiple adjustments of the register parameter in the target adjustment manner using the adjustment value of this round include: Detecting whether the proportional parameter before the iterative adjustment is greater than the third threshold; If it is greater than the third threshold and the current iteration round number is odd, the register parameter is adjusted multiple times in a decreasing manner; when the current iteration round number is even, the register parameter is adjusted multiple times in an increasing manner; If it is not greater than the third threshold and the current iteration round number is odd, the register parameter is adjusted multiple times in an increasing manner; when the current iteration round number is even, the register parameter is adjusted multiple times in a decreasing manner.

8. An electronic device, characterized in that, It includes: A memory for storing program instructions; A processor for calling the program instructions stored in the memory and executing the steps included in the method according to any one of claims 1-7 according to the obtained program instructions.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program includes program instructions, and when the program instructions are executed by a computer, the computer is made to execute the method according to any one of claims 1-7.

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