Group iii element nitride semiconductor substrate

Abstract

The present application provides a Group III element nitride semiconductor substrate having a first surface and a second surface, wherein, even if the size of a device formed on the first surface is increased, the variation in device characteristics among devices within the same substrate is suppressed. The Group III element nitride semiconductor substrate according to an embodiment of the present application is a Group III element nitride semiconductor substrate having a first surface and a second surface, wherein at least one of the following (1) to (3) is satisfied. (1) The maximum height Wz of the surface roughness curve of the first surface is 150 nm or less. (2) The root mean square height Wq of the surface roughness curve of the first surface is 25 nm or less. (3) The average length WSm of the surface roughness curve elements of the first surface is 0.5 mm or more.

Description

TECHNICAL FIELD

[0001] The present application relates to a Group III element nitride semiconductor substrate. More specifically, it relates to a Group III element nitride semiconductor substrate having a first surface and a second surface, wherein a quality variation in the first surface of the Group III element nitride semiconductor substrate is suppressed. BACKGROUND

[0002] As a substrate of various semiconductor devices, a Group III element nitride semiconductor substrate such as a gallium nitride (GaN) wafer, an aluminum nitride (AIN) wafer, an indium nitride (InN) wafer, etc. is used (for example, Patent Document 1, etc.).

[0003] The semiconductor substrate has a first surface and a second surface. When the first surface is set as a main surface and the second surface is set as a back surface, the main surface is typically a Group III element polar surface, and the back surface is typically a nitrogen polar surface. An epitaxial crystal can be grown on the main surface, and in addition, various devices can be fabricated.

[0004] There is a report of a technique in which, by making the surface roughness of a Group III element nitride semiconductor substrate small, the crystallinity of a growth film of an epitaxial crystal formed on the main surface becomes good, the performance of a device formed on the main surface becomes good, or the performance variation of a device formed on the main surface is reduced (Patent Documents 2 to 4).

[0005] Patent Document 2 reports a nitride semiconductor substrate characterized in that the diameter is 45 mm or more, there is a uniform warping having one maximum point or minimum point, the height H of the central portion is 12 μm or less, or the curvature radius of the warping is 21 m or more, by CMP polishing, the surface roughness is made to be 0.1 nm ≤ RMS ≤ 5 nm, the back surface roughness is made to be 0.1 nm ≤ RMS ≤ 5000 nm, and the in-plane thickness variation (TTV) measured by measuring points every 0.1 mm is 10 μm or less. In this Patent Document 2, it is reported that by making the RMS measured by AFM in a 10 μm square to be 0.1 nm ≤ RMS ≤ 5 nm (paragraph 0059), and the TTV measured every 0.1 mm to be 10 μm or less, the morphology after epitaxial growth can be made good (paragraph 0061).

[0006] Patent Document 3 reports a method in which, in an Al x Ga y In z N wafer, the surface roughness of the Ga side in a 10 x 10 μm 2The surface roughness, characterized by root mean square (RMS) surface roughness, is less than 1 nm within the area. Patent document 3 reports that, in order to improve the quality of the AlGaInN crystals subsequently grown on the substrate, the surface roughness RMS (measured in the range of 10 × 10 μm) is optimized. 2 It is very important that the size is less than 1nm.

[0007] Patent Document 4 reports the following GaN crystalline substrate (regarding the symbol for warpage, + indicates a convex growth surface and - indicates a concave growth surface), wherein the back-side warpage W(R) of the GaN substrate is -35μm≤W(R)≤45μm, and the surface roughness Ra is Ra≤5nm. Patent Document 4 also reports that by achieving a surface roughness Ra of 5nm or less, a semiconductor layer with good crystallinity can be grown (using 3D-SEM at an 80×110μm depth). 2 The range was measured using a laser displacement meter at 700×750μm. 2 (Section 0068)

[0008] In the past, it was desirable to make the substrate surface 10×10μm... 2 80×110μm 2 700×750μm 2 The reduced surface roughness of such microscopic regions improves the crystallinity of the epitaxial growth film formed on the main surface of the group III nitride semiconductor substrate, thereby improving the performance of the device formed on the main surface or reducing the performance deviation of the device formed on the main surface.

[0009] Here, group III nitride semiconductor substrates are used as base substrates for light-emitting devices such as LEDs and LDs. In recent years, their application in high-frequency / high-power electronic devices has also attracted much attention. In particular, in high-power devices, due to the increase in component size, there is a need for group III nitride semiconductor substrates to be made larger in diameter, from the current mainstream 2 inches (50.8 mm in diameter) to 4 inches (approximately 100 mm) and 6 inches (approximately 150 mm).

[0010] However, as the size of devices fabricated on the main surface of group III nitride semiconductor substrates increases, the problems of deteriorating device characteristics and increasing deviations in device characteristics between devices within the same substrate become more pronounced.

[0011] Existing technical documents

[0012] Patent documents

[0013] Patent Document 1: Japanese Patent Application Publication No. 2005-263609

[0014] Patent Document 2: Japanese Patent No. 3581145

[0015] Patent Document 3: Japanese Patent No. 4350505

[0016] Patent Document 4: Japanese Patent No. 4380791 Summary of the Invention

[0017] The objective of this invention is to provide a group III nitride semiconductor substrate having a first surface and a second surface, wherein even if the size of the device fabricated on the first surface increases, the deviation of device characteristics between devices within the same substrate is suppressed.

[0018] One embodiment of the present invention relates to a group III nitride semiconductor substrate having a first surface and a second surface, wherein...

[0019] The maximum height Wz of the surface undulation curve of the first surface is below 150 nm.

[0020] One embodiment of the present invention relates to a group III nitride semiconductor substrate having a first surface and a second surface, wherein...

[0021] The root mean square height Wq of the surface undulation curve of the first surface is less than 25 nm.

[0022] One embodiment of the present invention relates to a group III nitride semiconductor substrate having a first surface and a second surface, wherein...

[0023] The average length WSm of the surface undulation curve element of the first surface is greater than 0.5 mm.

[0024] In one embodiment, the root mean square roughness Rms of the first surface of the group III nitride semiconductor substrate is less than 10 nm.

[0025] In one embodiment, the diameter of the aforementioned group III element nitride semiconductor substrate is 75 mm or more.

[0026] Invention Effects

[0027] According to the present invention, a group III element nitride semiconductor substrate is provided, which has a first surface and a second surface, such that even if the size of the device fabricated on the first surface increases, the deviation of device characteristics between devices within the same substrate is suppressed. Attached Figure Description

[0028] Figure 1 This is a representative schematic cross-sectional view of a group III element nitride semiconductor substrate involved in the embodiments of the present invention.

[0029] Figure 2 This is a schematic diagram illustrating a method for manufacturing a group III nitride semiconductor substrate according to an embodiment of the present invention. Detailed Implementation

[0030] When the term "weight" is used in this specification, it can be replaced with "mass," which is the SI unit commonly used to represent components.

[0031] Typically, the group III nitride semiconductor substrate involved in the embodiments of the present invention is a self-standing substrate formed by crystallizing group III nitrides. In the description of the present invention, "self-standing substrate" refers to a substrate that will not deform or break due to its own weight during operation and can be operated in the form of a solid. Self-standing substrates can be used as substrates for various semiconductor devices such as light-emitting elements and power control elements.

[0032] Typically, the group III nitride semiconductor substrate involved in the embodiments of the present invention is wafer-shaped (generally circular). However, it can be processed into other shapes, such as rectangular shapes, as needed.

[0033] Regarding the diameter of the group III nitride semiconductor substrate involved in the embodiments of the present invention, any suitable diameter can be used within the range that does not impair the effects of the present invention. In terms of better demonstrating the effects of the present invention, the diameter of the group III nitride semiconductor substrate involved in the embodiments of the present invention is preferably 50 mm or more, more preferably 75 mm or more, and even more preferably 100 mm or more. In particular, if the group III nitride semiconductor substrate involved in the embodiments of the present invention is a so-called large-diameter group III nitride semiconductor substrate with a diameter of 75 mm or more, then the application of the group III nitride semiconductor substrate involved in the embodiments of the present invention in high-frequency / high-power electronic devices becomes easier, especially in high-power devices with larger component sizes.

[0034] As large-aperture group III nitride semiconductor substrates, specific examples include 4-inch wafers, 6-inch wafers, 8-inch wafers, and 12-inch wafers.

[0035] The thickness of the group III nitride semiconductor substrate involved in the embodiments of the present invention (the thickness of the thickest part when the thickness is not constant) is preferably 300 μm to 1000 μm.

[0036] Representative examples of group III nitrides include gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), or mixtures thereof. These group III nitrides can be of a single element or two or more elements.

[0037] Specifically, the nitrides of group III elements are GaN, AlN, InN, and Ga. x Al 1－x N(1>x>0),Ga x In 1－x N(1>x>0), Al x In 1－x N(1>x>0),Ga x Al y In z N(1>x>0, 1>y>0, x+y+z=1). These group III nitrides can be doped with various n-type or p-type dopants.

[0038] Representative examples of p-type dopants include beryllium (Be), magnesium (Mg), strontium (Sr), and cadmium (Cd). There can be only one p-type dopant or two or more.

[0039] Representative examples of n-type dopants include silicon (Si), germanium (Ge), tin (Sn), and oxygen (O). There can be only one type of n-type dopant, or there can be two or more.

[0040] The surface orientation of a group III nitride semiconductor substrate can be a c-plane, a-plane, or a specific crystal plane inclined relative to the c-plane, a-plane, or m-plane, respectively. In particular, the effect of the present invention is more pronounced when the surface is set to the c-plane. Examples of specific crystal planes inclined relative to the c-plane, a-plane, or m-plane include so-called semi-polar planes such as the {11-22} plane and the {20-21} plane. Furthermore, as a surface orientation, not only are so-called positive planes perpendicular to the c-plane, a-plane, m-plane, or specific crystal planes inclined relative to these planes permissible, but also deflection angles within the range of ±5° are permissible.

[0041] The group III nitride semiconductor substrate according to the embodiments of the present invention is a group III nitride semiconductor substrate having a first surface and a second surface. When the first surface is designated as the main surface and the second surface as the back surface, if the surface orientation of the group III nitride semiconductor substrate is c-plane, then the main surface is representative of the group III element polar surface, and the back surface is representative of the nitrogen polar surface. However, the main surface can also be designated as the nitrogen polar surface, and the back surface as the group III element polar surface. Epitaxial crystal growth can be performed on the main surface, and various devices can be fabricated. The back surface is held by a substrate or the like, allowing the group III nitride semiconductor substrate according to the embodiments of the present invention to be transferred.

[0042] In the description of the group III nitride semiconductor substrate according to the embodiments of the present invention, the first surface is referred to as the main surface and the second surface as the back surface. Therefore, in this specification, "main surface" can be referred to as "first surface" and "main surface" can also be referred to as "main surface"; "back surface" can be referred to as "second surface" and "back surface" can also be referred to as "back surface".

[0043] The main surface can be either mirrored or non-mirrored. Preferably, the main surface is mirrored.

[0044] Regarding the main surface, from the viewpoint of semiconductor devices with good characteristics and minimal deviations in device characteristics between devices obtained by epitaxial growth of the device layer, the surface with low surface roughness in the microscopic region where the processing altered layer is substantially removed is preferred.

[0045] The back can be either mirrored or non-mirrored.

[0046] A mirror finish refers to a surface that has undergone mirror polishing. After mirror polishing, the surface roughness and unevenness are reduced to a level where light is reflected and an object's reflection can be visually observed and confirmed. In other words, the roughness and unevenness of a mirror-polished surface are reduced to a level that is negligible relative to the wavelength of visible light.

[0047] As a method for mirror finishing, any suitable method can be employed within the scope of not compromising the effects of the present invention. Examples of such methods include: mirror finishing using one or a combination of a polishing apparatus employing an abrasive belt, a fine polishing apparatus employing diamond abrasive grains, and a CMP (Chemical Mechanical Polish) apparatus employing a slurry such as colloidal silica and a non-woven fabric abrasive pad. If a processing-modified layer remains on the finished surface, the processing-modified layer is removed. Examples of methods for removing the processing-modified layer include: removing the processing-modified layer using RIE (Reactive Ion Etching) or a chemical solution, and annealing the substrate.

[0048] Non-mirror surfaces are those that have not undergone mirror finishing; a typical example is a rough surface obtained through roughening.

[0049] As a method for roughening the surface, any suitable method can be employed within the scope of not compromising the effects of the present invention. Examples of such methods include: grinding using a grinding stone, laser texturing, etching using various chemical solutions and gases, physical or chemical coating, and texturing using mechanical processing.

[0050] If residual stress caused by the processing altered layer is confirmed on the surface after back-side processing, it is preferable to remove the processing altered layer to eliminate the residual stress. Methods for removing the processing altered layer include, for example, removing the processing altered layer using RIE (Reactive Ion Etching) or chemical solutions, or annealing the substrate.

[0051] Figure 1 This is a representative schematic cross-sectional view of a group III element nitride semiconductor substrate involved in the embodiments of the present invention. Figure 1 As shown, representatively, the group III nitride semiconductor substrate 100 according to embodiments of the present invention has a main surface (group III element polar surface) 10 and a back surface (nitrogen polar surface) 20. The group III nitride semiconductor substrate 100 according to embodiments of the present invention may have a side surface 30.

[0052] The ends of the group III nitride semiconductor substrates according to embodiments of the present invention can be adopted in any suitable form without compromising the effects of the present invention. Examples of the ends of the group III nitride semiconductor substrates according to embodiments of the present invention include: chamfered portions on both the main surface and the back surface being chamfered into flat surfaces; chamfered portions on both the main surface and the back surface being chamfered into curved surfaces; chamfered portions on only the main surface of the end being chamfered into flat surfaces; and chamfered portions on only the back surface of the end being chamfered into flat surfaces.

[0053] In the case where the end of the group III nitride semiconductor substrate involved in the embodiments of the present invention is chamfered, the chamfered portion may be provided for the entire circumference of the outer periphery, or it may be provided only for a part of the outer periphery.

[0054] Typically, the group III nitride semiconductor substrate involved in the embodiments of the present invention is selected from at least one of the following (1) to (3).

[0055] (1) The maximum height Wz of the surface undulation curve of the main surface is less than 150nm.

[0056] (2) The root mean square height Wq of the surface undulation curve of the main surface is less than 25nm.

[0057] (3) The average length WSm of the surface undulation curve element of the main surface is 0.5 mm or more.

[0058] That is, in a representative sense, the group III nitride semiconductor substrate involved in the embodiments of the present invention is selected from the group of the following configurations: a configuration that satisfies (1) but not (2) and (3), a configuration that satisfies (2) but not (1) and (3), a configuration that satisfies (3) but not (1) and (2), a configuration that satisfies (1) and (2) but not (3), a configuration that satisfies (1) and (3) but not (2), a configuration that satisfies (2) and (3) but not (1), and a configuration that satisfies all of (1), (2) and (3).

[0059] In the group III nitride semiconductor substrates involved in the embodiments of the present invention, the more of the above-mentioned (1) to (3) conditions are satisfied, the more ideal it is.

[0060] When the group III nitride semiconductor substrate involved in the embodiments of the present invention is selected from at least one of the group consisting of (1) to (3) above, even if the size of the device fabricated on the main surface increases, the deviation of device characteristics between devices in the same substrate can be suppressed.

[0061] Regarding (1) above, in the group III nitride semiconductor substrate according to the embodiments of the present invention, the maximum height Wz of the surface undulation curve of the main surface is preferably 150 nm or less, more preferably 120 nm or less, further preferably 80 nm or less, and particularly preferably 50 nm or less. The smaller the lower limit of the maximum height Wz of the surface undulation curve of the main surface, the better. In the group III nitride semiconductor substrate according to the embodiments of the present invention, if the maximum height Wz of the surface undulation curve of the main surface is within the above range, even if the size of the device fabricated on the main surface increases, the deviation of device characteristics between devices within the same substrate can be suppressed. In the group III nitride semiconductor substrate according to the embodiments of the present invention, if the maximum height Wz of the surface undulation curve of the main surface deviates from the above range and is too large, when the size of the device fabricated on the main surface increases, the deviation of device characteristics between devices within the same substrate may increase.

[0062] Regarding (1) above, the method for measuring the maximum height Wz of the surface undulation curve of the main surface in the group III element nitride semiconductor substrate involved in the embodiments of the present invention will be described below.

[0063] Regarding (2) above, in the group III nitride semiconductor substrate according to the embodiments of the present invention, the root mean square height Wq of the surface undulation curve of the main surface is preferably 25 nm or less, more preferably 20 nm or less, further preferably 12 nm or less, and particularly preferably 10 nm or less. The smaller the lower limit value of the root mean square height Wq of the surface undulation curve of the main surface, the better. In the group III nitride semiconductor substrate according to the embodiments of the present invention, if the root mean square height Wq of the surface undulation curve of the main surface is within the above range, even if the size of the device fabricated on the main surface increases, the deviation of device characteristics between devices in the same substrate can be suppressed. In the group III nitride semiconductor substrate according to the embodiments of the present invention, if the root mean square height Wq of the surface undulation curve of the main surface deviates from the above range and is too large, when the size of the device fabricated on the main surface increases, the deviation of device characteristics between devices in the same substrate may increase.

[0064] Regarding (2) above, the method for measuring the root mean square height Wq of the surface undulation curve of the main surface in the group III element nitride semiconductor substrate involved in the embodiments of the present invention will be described below.

[0065] Regarding (3) above, in the group III nitride semiconductor substrate according to the embodiments of the present invention, the average length WSm of the surface undulation curve element of the main surface is preferably 0.5 mm or more, more preferably 1.0 mm or more, further preferably 1.5 mm or more, and particularly preferably 3.0 mm or more. Considering the measurement limit, the upper limit of the average length WSm of the surface undulation curve element of the main surface is actually 10 mm or less. In the group III nitride semiconductor substrate according to the embodiments of the present invention, if the average length WSm of the surface undulation curve element of the main surface is within the above range, even if the size of the device fabricated on the main surface increases, the deviation of device characteristics between devices in the same substrate can be suppressed. In the group III nitride semiconductor substrate according to the embodiments of the present invention, if the average length WSm of the surface undulation curve element of the main surface deviates from the above range and is too small, when the size of the device fabricated on the main surface increases, the deviation of device characteristics between devices in the same substrate may increase.

[0066] Regarding (3) above, the method for measuring the average length WSm of the surface undulation curve element of the main surface in the group III element nitride semiconductor substrate involved in the embodiments of the present invention will be described below.

[0067] Regarding (1) to (3) above, it is preferable to measure the maximum height Wz of the surface undulation curve of the main surface, the root mean square height Wq of the surface undulation curve of the main surface, and the average length WSm of the surface undulation curve element of the main surface in the entire area of ​​the main surface, except for the chamfered part of the outer periphery where the device is not formed (the non-device forming area).

[0068] As described above, from the viewpoint of semiconductor devices that are fabricated by epitaxial growth of device layers and have good characteristics with minimal deviations in device characteristics between devices, the main surface is preferably a surface where the processing-modified layer is substantially removed and the surface roughness in the microscopic region is small. From this viewpoint, the root mean square roughness Rms of the main surface, measured by AFM with a square of 10 μm, is preferably 10 nm or less, more preferably 3 nm or less, and even more preferably 1 nm or less.

[0069] As the processing method for the main surface, any suitable method can be adopted within the scope of not compromising the effects of the present invention. Examples of such methods include: mirror finishing using one or a combination of a grinding apparatus using diamond grinding stones, a grinding apparatus using abrasive belts, a fine grinding apparatus using diamond abrasive grains, and a CMP (Chemical Mechanical Polish) apparatus using a slurry such as colloidal silica and a non-woven abrasive pad. If a processing-modified layer remains on the processed surface, the processing-modified layer is removed. Examples of such methods include: removing the processing-modified layer using RIE (Reactive Ion Etching) or a chemical solution, and annealing the substrate.

[0070] The group III nitride semiconductor substrates according to embodiments of the present invention can be manufactured using any suitable method without compromising the effects of the present invention. Hereinafter, a preferred method for manufacturing the group III nitride semiconductor substrates according to embodiments of the present invention will be described with regard to further demonstrating the effects of the present invention.

[0071] For the group III nitride semiconductor substrates involved in the embodiments of the present invention, typically, such as Figure 2 As shown in (a), a seed film 2 is formed on the main surface 1a of the substrate 1, and a group III element nitride layer 3 is formed on the group III element polar surface 2a of the seed film 2. Next, the group III element nitride layer (seed film 2 + group III element nitride layer 3), which will become a self-standing substrate, is separated from the substrate 1, as shown in (a). Figure 2 As shown in (b), a self-standing substrate 100' having a main surface 10' and a back surface 20' is obtained.

[0072] The substrate material can be any suitable material without compromising the effects of the present invention. Examples of suitable materials include: sapphire, crystalline oriented alumina, gallium oxide, and Al. x Ga 1－x N(0≤x≤1), GaAs, SiC, etc.

[0073] As the material for the seed film, any suitable material can be used within the range that does not impair the effects of the present invention. Examples of such materials include: Al. x Ga 1－x N(0≤x≤1), In x Ga 1－x N (0≤x≤1), preferably gallium nitride. As the material for the seed film, gallium nitride that can be confirmed by fluorescence microscopy to have a yellow luminescence effect is more preferred. Yellow luminescence refers to a peak (yellow luminescence (YL) or yellow band (YB)) appearing in the range of 2.2eV to 2.5eV, excluding the exciton transitions from the band to the band (UV).

[0074] As a method for forming the seed film, any suitable method can be used within the scope of not compromising the effects of the present invention. Examples of such methods include vapor phase growth, with preferred methods including: Metal-Organic Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Growth (HVPE), Pulse Excitation Deposition (PXD), MBE, and sublimation. Among these methods, Metal-Organic Chemical Vapor Deposition (MOCVD) is more preferred.

[0075] For example, preferably, after depositing a low-temperature growth buffer layer of 20 nm to 50 nm at 450 °C to 550 °C, a film layer of 2 μm to 4 μm thickness is stacked at 1000 °C to 1200 °C, thereby forming a seed film using the MOCVD method.

[0076] As the cultivation direction for the group III element nitride crystal layer, any suitable cultivation direction can be adopted within the range that does not impair the effects of the present invention. Examples of such cultivation directions include: the normal direction of the c-plane of the wurtzite structure, the normal directions of the a-plane and m-plane, and the normal directions of the planes inclined relative to the c-plane, a-plane, and m-plane, respectively.

[0077] As for the method of forming the crystallized layer of group III element nitrides, any suitable method can be used as long as the crystallization orientation roughly mimics that of the seed film. This method can be used within the scope of not compromising the effects of the present invention. Examples of such methods include: metal-organic chemical vapor deposition (MOCVD), hydride vapor deposition (HVPE), pulse-excited deposition (PXD), MBE, sublimation, and other vapor phase growth methods; liquid phase growth methods such as Na flux method, ammonothermal method, hydrothermal method, sol-gel method, etc.; powder growth methods utilizing solid-phase growth of powders; and combinations of these methods.

[0078] When the Na flux method is used as the method for forming the crystallized layer of group III element nitrides, it is preferable to carry out the Na flux method by appropriately adjusting the conditions in a way that can better demonstrate the effects of the present invention, according to the manufacturing method described in Japanese Patent No. 5244628.

[0079] Next, by separating the group III nitride crystal layer from the substrate, a self-standing substrate including the group III nitride crystal layer can be obtained.

[0080] As a method for separating the group III nitride crystal layer from the substrate, any suitable method can be employed within the scope of not compromising the effects of the present invention. Examples of such methods include: using thermal shrinkage difference to spontaneously separate the group III nitride crystal layer from the substrate during a cooling process after the group III nitride crystal layer has been grown; and separating the group III nitride crystal layer from the substrate by chemical etching. Figure 2 (a) shows a method for peeling the group III nitride crystal layer from the substrate 1 by laser ablation as shown by arrow A, and a method for peeling the group III nitride crystal layer from the substrate by grinding. Alternatively, the group III nitride crystal layer can be sliced ​​using a wire saw or the like to obtain a self-standing substrate including the group III nitride crystal layer.

[0081] Next, the outer periphery of the self-supporting substrate is ground to adjust it into a circle of the desired diameter.

[0082] Next, the main surface and / or back surface are removed by surface processing such as grinding, fine grinding, and lapping, thereby obtaining a self-standing substrate that has been thinned and planarized to the desired thickness.

[0083] When performing surface processing such as grinding, fine grinding, and lapping, the self-standing substrate is usually attached to the processing platform by means of wax or the like. At this time, if the pressure on which the self-standing substrate is attached to the processing platform, specifically the pressure applied to the self-standing substrate when it is attached to the processing platform, is appropriately adjusted, it is preferable that the group III nitride semiconductor substrate involved in the embodiments of the present invention can be at least one selected from the group consisting of (1) to (3) below.

[0084] (1) The maximum height Wz of the surface undulation curve of the main surface is less than 150nm.

[0085] (2) The root mean square height Wq of the surface undulation curve of the main surface is less than 25nm.

[0086] (3) The average length WSm of the surface undulation curve element of the main surface is 0.5 mm or more.

[0087] In the case of a self-standing substrate mainly composed of a low-hardness material such as silicon, even if the surface of the self-standing substrate is warped, by applying pressure to the entire self-standing substrate to make the surface flat, the entire surface of the self-standing substrate changes smoothly in accordance with the flatness of the surface of the processing platform, and the surface of the self-standing substrate is easily adhered to the processing platform in a uniformly flattened state.

[0088] On the other hand, in the case of self-standing substrates primarily composed of high-hardness materials such as group III nitrides, when the surface of the self-standing substrate warps, under pressure to flatten the surface, the overall surface does not uniformly mimic the flatness of the processing platform surface. Therefore, when viewed from a local viewpoint in millimeters, the self-standing substrate is attached to the processing platform with an undulating surface. Then, surface processing of the self-standing substrate is performed in this state, and when it is removed from the processing platform after surface processing, undulations remain on the surface of the self-standing substrate.

[0089] By increasing the pressure applied when attaching the self-standing substrate to the processing platform to a level greater than the pressure required to flatten the warped surface of the self-standing substrate, even substrates with locally warped shapes can be flattened during attachment. Furthermore, by pressing a flexible material such as a silicone sheet onto the self-standing substrate during attachment to the processing platform, more uniform pressure is applied to the entire self-standing substrate, enabling the flattening of surfaces with locally curved shapes. Surface processing of the self-standing substrate is performed in this state, resulting in a self-standing substrate with minimal surface undulations when removed from the processing platform. The preferred pressure for attaching the self-standing substrate to the processing platform is at least twice the pressure required to flatten the warped surface of the self-standing substrate.

[0090] The specific pressure value required to flatten the surface of the warped self-supporting substrate can be calculated using the following formula. It should be noted that, typically, the pressure value can be calculated based on the following formula; however, due to factors such as the thickness of the self-supporting substrate and areas of uneven crystal quality, the surface of the warped self-supporting substrate may not become sufficiently flat at the pressure value calculated based on the following formula. In such cases, the pressure can be further increased as needed.

[0091] S = 2.1 × 10 －11 ×B×T 3

[0092] (S is the pressure (in MPa), B is the warpage of the self-supporting substrate (in μm), and T is the thickness of the self-supporting substrate (in μm).)

[0093] However, if excessive pressure is applied to the self-supporting substrate when it is bonded to the processing platform, the self-supporting substrate may crack, or the amount of wax required to bond the self-supporting substrate and the processing platform may not remain between the self-supporting substrate and the processing platform. Therefore, it is very important to bond the self-supporting substrate at a pressure that does not cause cracks or fissures and that allows the self-supporting substrate and the processing platform to bond. The preferred pressure when bonding the self-supporting substrate to the processing platform is 10 MPa or less.

[0094] Therefore, as described above, the "preferred pressure when attaching the self-supporting substrate to the processing platform" is more than twice the pressure required to flatten the surface of the warped self-supporting substrate. Thus, the "preferred pressure when attaching the self-supporting substrate to the processing platform" is (2×S) or more, and more preferably (3×S) or more.

[0095] The thickness of the self-standing substrate (the thickness of the thickest part when the thickness is not constant) is preferably 300 μm to 1000 μm.

[0096] As needed, the outer periphery of the self-standing substrate is chamfered by grinding. If a processing-modified layer remains on the main surface, the processing-modified layer is substantially removed. In addition, if residual stress caused by the processing-modified layer remains on the back surface, the residual stress is removed, and finally, the group III element nitride semiconductor substrate 100 according to the embodiment of the present invention is obtained.

[0097] The obtained group III nitride semiconductor substrate 100 allows for epitaxial growth of crystals on its main surface (group III polar surface) 10, such as... Figure 2 As shown in (c), the functional layer 4 is deposited to obtain the functional element 5. 20 is the back side (nitrogen polar side).

[0098] Examples of epitaxial crystals grown on a obtained group III element nitride semiconductor substrate include gallium nitride, aluminum nitride, indium nitride, or mixtures thereof. Specifically, examples of such epitaxial crystals include GaN, AlN, InN, and Ga... x Al 1－x N(1>x>0),Ga x In 1－x N(1>x>0), Al x In 1－x N(1>x>0),Ga x Al y In z N(1>x>0, 1>y>0, x+y+z=1). Furthermore, besides the light-emitting layer, functional layers that can be provided on the obtained group III nitride semiconductor substrate include rectifier layers, switching element layers, and power semiconductor layers. Additionally, after providing the functional layer on the group III polar surface of the obtained group III nitride semiconductor substrate, processing the nitrogen polar surface, such as by grinding or polishing, can also reduce the thickness and thickness distribution of the self-contained substrate.

[0099] Example

[0100] The present invention will now be specifically described through examples; however, the present invention is not limited to these examples in any way. It should be noted that the testing and evaluation methods in the examples are as follows. It should be noted that when a quantity is described as "parts," unless otherwise specified, it refers to "parts by weight"; when a quantity is described as "%," unless otherwise specified, it refers to "% by weight."

[0101] <Measurement of Surface Unevenness>

[0102] The surface undulation curve of the main surface was measured based on ISO 4287:1997. The measurement length was set to 8 mm, the cutoff wavelength for removing long-wavelength components was set to 8 mm, and the cutoff wavelength for removing short-wavelength components was set to 0.25 mm. Regarding the measurement position, with the radius of the substrate set to R (mm), the coordinates of the following 9 points on the surface of the substrate were measured: (0, 0), (0, R-5), (R-5, 0), (0, -R+5), (-R+5, 0), (0, (R-5) / 2), ((R-5) / 2, 0), (0, (-R+5) / 2), ((-R+5) / 2, 0). Based on the surface undulation curves obtained at each point, the maximum height of the surface undulation curve, the root mean square height of the surface undulation curve, and the average length of the surface undulation curve element at each point are calculated. The maximum values ​​of each of the nine points are set as the maximum height Wz (nm) of the surface undulation curve of the main surface of the substrate, the root mean square height Wq (nm) of the surface undulation curve of the main surface, and the average length WSm (mm) of the surface undulation curve element of the main surface.

[0103] <Determination of the root mean square roughness Rms of the principal surface>

[0104] The root mean square roughness Rms of the main surface was measured using AFM (Atomic Force Microscope). The measurement range was set to 10 μm square.

[0105] <Device Characteristic Evaluation>

[0106] HEMT structures were epitaxially grown on a self-standing substrate using MOCVD. For the HEMT structure, a 2 μm i-type GaN layer, a 1 nm AlN layer, and a 25 nm AlGaN layer were sequentially deposited on the self-standing substrate, with the Al composition of the AlGaN layer set to 30%.

[0107] As drain and source electrodes, Ti / Al / Ni / Au (thicknesses 15nm / 7nm / 10nm / 50nm) were deposited by vapor deposition and then annealed at 700°C for 30 seconds using RTA. Subsequently, Pd / Ti / Au (thicknesses 40nm / 15nm / 80nm) was deposited as the gate electrode by vapor deposition. Patterning was then performed using photolithography.

[0108] During pattern formation, the unit gate width is 150 μm, the gate length is 2 μm, and the longitudinal length of the device is 1 mm. The lateral length of the device is varied within the range of 0.5 mm to 5 mm by changing the number of gate fingers. Afterwards, the device is separated to fabricate the HEMT device.

[0109] The device dimensions were varied, and the characteristics of 10 devices were evaluated for each dimension. The deviation of the maximum drain current among the 10 devices was compared across the different device dimensions.

[0110] The deviation of device characteristics is calculated as the absolute value of [(maximum value - minimum value) / (maximum value + minimum value)] × 100 (%).

[0111] [Example 1]

[0112] A seed film containing gallium nitride with a thickness of 2 μm was formed on a 4-inch diameter sapphire substrate using the MOCVD method to obtain a seed substrate.

[0113] The obtained seed substrate was placed in an alumina crucible inside a glove box under a nitrogen atmosphere.

[0114] Next, metallic gallium and metallic sodium were filled into the crucible at a ratio of Ga / (Ga+Na)(mol%) = 15 mol%. The crucible was placed in a heat-resistant metal container and then positioned on a rotating platform of a crystallization furnace. The crystallization furnace was heated and pressurized to 870°C and 4.0 MPa, and maintained for 100 hours, while the container was rotated to stir the solution and allow crystal growth. Afterward, the mixture was slowly cooled to room temperature and the pressure was reduced to atmospheric pressure. The culture container was then removed from the crystallization furnace.

[0115] The solidified metallic sodium in the crucible was removed by rinsing with alcohol, resulting in a crack-free gallium nitride crystal layer (1 mm thick) on the seed substrate.

[0116] The gallium nitride (GaN) crystal layer was separated by using the laser lift-off (LLO) method to obtain a GaN self-standing substrate.

[0117] The outer periphery of the gallium nitride self-standing substrate is ground to adjust it into a circular gallium nitride self-standing substrate with a diameter of 100 mm.

[0118] Using wax, the obtained self-supporting substrate was bonded to a ceramic processing platform, and the Ga polar surface was ground and finished. The final finishing process used diamond abrasive grains with a diameter of 0.1 μm to achieve a root mean square roughness (RMS) of less than 1 nm. Afterwards, the altered layer was removed using a refining process (RIE). It should be noted that when bonding the self-supporting substrate to the processing platform, a 2 mm thick silicone sheet was placed on the self-supporting substrate to completely cover its surface, and a load was applied. The pressure applied to the entire surface of the self-supporting substrate was set to 1.5 MPa.

[0119] After surface processing, the a-axis of the gallium nitride single crystal passing through the center of the substrate is set as the X-axis, and the m-axis orthogonal to the X-axis passing through the center of the substrate is set as the Y-axis. At the coordinate positions of 9 points (0, 0), (0, 45), (45, 0), (0, -45), (-45, 0), (0, 22.5), (22.5, 0), (0, -22.5), (-22.5, 0), the maximum height Wz of the surface undulation curve, the root mean square height Wq of the surface undulation curve, and the average length WSm of the surface undulation curve elements are measured. The maximum values ​​of each of the 9 points are 31 nm, 8 nm, and 4.2 mm.

[0120] Next, the self-standing substrate with the Ga polar surface processed is flipped over, and the nitrogen polar surface is ground and polished using wax on a ceramic processing platform. Finally, a mirror finish is achieved using diamond abrasive grains with a diameter of 0.1 μm. Afterwards, a refinishing process (RIE) is used to remove the altered layer.

[0121] In this way, a wafer (1) is fabricated as a gallium nitride self-standing substrate.

[0122] The thickness of the wafer (1) is 500 μm.

[0123] The results are shown in Table 1.

[0124] [Example 2]

[0125] When attaching the self-standing substrate to the processing platform, the pressure applied to the self-standing substrate is set to 1.2 MPa. Otherwise, the same procedure as in Example 1 is followed to fabricate a wafer (2) as a gallium nitride self-standing substrate.

[0126] The thickness of the wafer (2) is 500 μm.

[0127] The maximum values ​​of the surface undulation curve's maximum height Wz, root mean square height Wq, and average length WSm of the surface undulation curve's elements are: Wz = 59 nm, Wq = 10 nm, and WSm = 2.9 mm.

[0128] The results are shown in Table 1.

[0129] [Example 3]

[0130] When attaching the self-standing substrate to the processing platform, the pressure applied to the self-standing substrate is set to 0.9 MPa. Otherwise, the same procedure as in Example 1 is followed to fabricate a wafer (3) as a gallium nitride self-standing substrate.

[0131] The thickness of the wafer (3) is 500 μm.

[0132] The maximum values ​​of the surface undulation curve's maximum height Wz, root mean square height Wq, and average length WSm of the surface undulation curve's elements are: Wz = 113 nm, Wq = 17 nm, and WSm = 1.6 mm.

[0133] The results are shown in Table 1.

[0134] [Example 4]

[0135] When attaching the self-standing substrate to the processing platform, the pressure applied to the self-standing substrate is set to 0.6 MPa. Otherwise, the same procedure as in Example 1 is followed to fabricate a wafer (4) as a gallium nitride self-standing substrate.

[0136] The thickness of the wafer (4) is 500 μm.

[0137] The maximum values ​​of the surface undulation curve's maximum height Wz, root mean square height Wq, and average length WSm of the surface undulation curve's elements are: Wz = 147 nm, Wq = 23 nm, and WSm = 1.1 mm.

[0138] The results are shown in Table 1.

[0139] [Comparative Example 1]

[0140] When attaching the self-standing substrate to the processing platform, the pressure applied to the self-standing substrate is set to 0.3 MPa. Otherwise, the process is the same as in Example 1 to fabricate a wafer (C1) as a gallium nitride self-standing substrate.

[0141] The thickness of the wafer (C1) is 500 μm.

[0142] The maximum values ​​of the surface undulation curve's maximum height Wz, root mean square height Wq, and average length WSm of the surface undulation curve's elements are: Wz = 202 nm, Wq = 36 nm, and WSm = 0.4 mm.

[0143] The results are shown in Table 1.

[0144] [Table 1]

[0145]

[0146] In Examples 1-4 and Comparative Example 1, the root mean square roughness Rms was independent of the magnitude of surface undulations; its value was sufficiently small to allow for good epitaxial growth. The reason for considering it independent of the magnitude of surface undulations is that the surface roughness was measured locally.

[0147] In Examples 1-4, even when the component size of the device increases, the deviation of the device characteristics is sufficiently suppressed. On the other hand, as seen in Comparative Example 1, when the surface undulation of the substrate increases, the deviation of the device characteristics increases, and furthermore, as the component size of the device increases, the deviation of the device characteristics increases.

[0148] Industrial availability

[0149] The group III nitride semiconductor substrates involved in the embodiments of the present invention can be used as substrates for various semiconductor devices.

[0150] Symbol Explanation

[0151] Group III nitride semiconductor substrates

[0152] 100' free standing baseboard

[0153] 1. Substrate

[0154] 1a Main surface of substrate 1

[0155] 1b Back side of substrate 1

[0156] 2. Seed film

[0157] 2a Group III element polar surface of seed film 2

[0158] 3 Group III nitride layers

[0159] 4. Functional Layer

[0160] 5 Functional Components

[0161] 10 main sides

[0162] 10' Main side

[0163] 20 Back

[0164] 20' back

[0165] 30 side view

Claims

1. A group III element nitride semiconductor substrate, having a first surface and a second surface, The characteristic of the group III nitride semiconductor substrate is that... When a group III nitride semiconductor substrate is bonded to a processing platform for surface processing, the pressure at which the group III nitride semiconductor substrate is bonded to the processing platform is set to be more than twice the pressure required to flatten the warped surface of the group III nitride semiconductor substrate, but less than 10 MPa. The maximum height Wz of the surface undulation curve of the first surface is less than 150 nm, the root mean square height Wq of the surface undulation curve of the first surface is less than 25 nm, and the average length WSm of the surface undulation curve element of the first surface is more than 0.5 mm.

2. The group III nitride semiconductor substrate according to claim 1, characterized in that, The root mean square roughness Rms of the first surface of the group III element nitride semiconductor substrate is less than 10 nm.

3. The group III nitride semiconductor substrate according to claim 1 or 2, characterized in that, The diameter of the group III nitride semiconductor substrate is 75 mm or more.

4. The group III nitride semiconductor substrate according to claim 3, characterized in that, The diameter of the group III nitride semiconductor substrate is 75 mm or more.

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